/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* ALSA SoC Audio Layer - Rockchip SAI Controller driver
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*
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* Copyright (c) 2022 Rockchip Electronics Co. Ltd.
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*/
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#ifndef _ROCKCHIP_SAI_H
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#define _ROCKCHIP_SAI_H
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/* XCR Transmit / Receive Control Register */
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#define SAI_XCR_EDGE_SHIFT_MASK BIT(22)
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#define SAI_XCR_EDGE_SHIFT_1 BIT(22)
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#define SAI_XCR_EDGE_SHIFT_0 0
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#define SAI_XCR_CSR_MASK GENMASK(21, 20)
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#define SAI_XCR_CSR(x) ((x - 1) << 20)
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#define SAI_XCR_CSR_V(v) ((((v) & SAI_XCR_CSR_MASK) >> 20) + 1)
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#define SAI_XCR_SJM_MASK BIT(19)
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#define SAI_XCR_SJM_L BIT(19)
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#define SAI_XCR_SJM_R 0
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#define SAI_XCR_FBM_MASK BIT(18)
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#define SAI_XCR_FBM_LSB BIT(18)
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#define SAI_XCR_FBM_MSB 0
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#define SAI_XCR_SNB_MASK GENMASK(17, 11)
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#define SAI_XCR_SNB(x) ((x - 1) << 11)
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#define SAI_XCR_VDJ_MASK BIT(10)
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#define SAI_XCR_VDJ_L BIT(10)
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#define SAI_XCR_VDJ_R 0
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#define SAI_XCR_SBW_MASK GENMASK(9, 5)
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#define SAI_XCR_SBW(x) ((x - 1) << 5)
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#define SAI_XCR_SBW_V(v) ((((v) & SAI_XCR_SBW_MASK) >> 5) + 1)
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#define SAI_XCR_VDW_MASK GENMASK(4, 0)
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#define SAI_XCR_VDW(x) ((x - 1) << 0)
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/* FSCR Frame Sync Control Register */
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#define SAI_FSCR_EDGE_MASK BIT(24)
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#define SAI_FSCR_EDGE_DUAL BIT(24)
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#define SAI_FSCR_EDGE_RISING 0
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#define SAI_FSCR_FPW_MASK GENMASK(23, 12)
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#define SAI_FSCR_FPW(x) ((x - 1) << 12)
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#define SAI_FSCR_FW_MASK GENMASK(11, 0)
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#define SAI_FSCR_FW(x) ((x - 1) << 0)
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/* MONO_CR Mono Control Register */
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#define SAI_MCR_RX_MONO_SLOT_MASK GENMASK(8, 2)
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#define SAI_MCR_RX_MONO_SLOT_SEL(x) ((x - 1) << 2)
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#define SAI_MCR_RX_MONO_MASK BIT(1)
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#define SAI_MCR_RX_MONO_EN BIT(1)
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#define SAI_MCR_RX_MONO_DIS 0
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#define SAI_MCR_TX_MONO_MASK BIT(0)
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#define SAI_MCR_TX_MONO_EN BIT(0)
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#define SAI_MCR_TX_MONO_DIS 0
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/* XFER Transfer Start Register */
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#define SAI_XFER_RX_IDLE BIT(8)
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#define SAI_XFER_TX_IDLE BIT(7)
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#define SAI_XFER_FS_IDLE BIT(6)
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#define SAI_XFER_RX_CNT_MASK BIT(5)
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#define SAI_XFER_RX_CNT_EN BIT(5)
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#define SAI_XFER_RX_CNT_DIS 0
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#define SAI_XFER_TX_CNT_MASK BIT(4)
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#define SAI_XFER_TX_CNT_EN BIT(4)
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#define SAI_XFER_TX_CNT_DIS 0
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#define SAI_XFER_RXS_MASK BIT(3)
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#define SAI_XFER_RXS_EN BIT(3)
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#define SAI_XFER_RXS_DIS 0
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#define SAI_XFER_TXS_MASK BIT(2)
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#define SAI_XFER_TXS_EN BIT(2)
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#define SAI_XFER_TXS_DIS 0
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#define SAI_XFER_FSS_MASK BIT(1)
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#define SAI_XFER_FSS_EN BIT(1)
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#define SAI_XFER_FSS_DIS 0
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#define SAI_XFER_CLK_MASK BIT(0)
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#define SAI_XFER_CLK_EN BIT(0)
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#define SAI_XFER_CLK_DIS 0
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/* CLR Clear Logic Register */
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#define SAI_CLR_FSC BIT(2)
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#define SAI_CLR_RXC BIT(1)
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#define SAI_CLR_TXC BIT(0)
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/* CKR Clock Generation Register */
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#define SAI_CKR_MDIV_MASK GENMASK(14, 3)
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#define SAI_CKR_MDIV(x) ((x - 1) << 3)
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#define SAI_CKR_MSS_MASK BIT(2)
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#define SAI_CKR_MSS_SLAVE BIT(2)
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#define SAI_CKR_MSS_MASTER 0
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#define SAI_CKR_CKP_MASK BIT(1)
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#define SAI_CKR_CKP_INVERTED BIT(1)
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#define SAI_CKR_CKP_NORMAL 0
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#define SAI_CKR_FSP_MASK BIT(0)
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#define SAI_CKR_FSP_INVERTED BIT(0)
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#define SAI_CKR_FSP_NORMAL 0
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/* DMACR DMA Control Register */
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#define SAI_DMACR_RDE_MASK BIT(24)
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#define SAI_DMACR_RDE(x) ((x) << 24)
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#define SAI_DMACR_RDL_MASK GENMASK(20, 16)
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#define SAI_DMACR_RDL(x) ((x - 1) << 16)
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#define SAI_DMACR_RDL_V(v) ((((v) & SAI_DMACR_RDL_MASK) >> 16) + 1)
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#define SAI_DMACR_TDE_MASK BIT(8)
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#define SAI_DMACR_TDE(x) ((x) << 8)
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#define SAI_DMACR_TDL_MASK GENMASK(4, 0)
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#define SAI_DMACR_TDL(x) ((x) << 0)
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#define SAI_DMACR_TDL_V(v) (((v) & SAI_DMACR_TDL_MASK) >> 0)
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/* INTCR Interrupt Ctrl Register */
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#define SAI_INTCR_RXOIC BIT(18)
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#define SAI_INTCR_RXOIE_MASK BIT(17)
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#define SAI_INTCR_RXOIE(x) ((x) << 17)
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#define SAI_INTCR_TXUIC BIT(2)
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#define SAI_INTCR_TXUIE_MASK BIT(1)
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#define SAI_INTCR_TXUIE(x) ((x) << 1)
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/* INTSR Interrupt Status Register */
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#define SAI_INTSR_RXOI_INA 0
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#define SAI_INTSR_RXOI_ACT BIT(17)
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#define SAI_INTSR_TXUI_INA 0
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#define SAI_INTSR_TXUI_ACT BIT(1)
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/* XSHIFT: Transfer / Receive Frame Sync Shift Register */
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#define SAI_XSHIFT_SEL_MASK GENMASK(23, 0)
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#define SAI_XSHIFT_SEL(x) (x)
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/* XFIFOLR: Transfer / Receive FIFO Level Register */
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#define SAI_FIFOLR_XFL3_SHIFT 18
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#define SAI_FIFOLR_XFL3_MASK GENMASK(23, 18)
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#define SAI_FIFOLR_XFL2_SHIFT 12
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#define SAI_FIFOLR_XFL2_MASK GENMASK(17, 12)
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#define SAI_FIFOLR_XFL1_SHIFT 6
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#define SAI_FIFOLR_XFL1_MASK GENMASK(11, 6)
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#define SAI_FIFOLR_XFL0_SHIFT 0
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#define SAI_FIFOLR_XFL0_MASK GENMASK(5, 0)
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/* SAI Registers */
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#define SAI_TXCR (0x0000)
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#define SAI_FSCR (0x0004)
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#define SAI_RXCR (0x0008)
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#define SAI_MONO_CR (0x000c)
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#define SAI_XFER (0x0010)
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#define SAI_CLR (0x0014)
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#define SAI_CKR (0x0018)
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#define SAI_TXFIFOLR (0x001c)
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#define SAI_RXFIFOLR (0x0020)
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#define SAI_DMACR (0x0024)
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#define SAI_INTCR (0x0028)
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#define SAI_INTSR (0x002c)
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#define SAI_TXDR (0x0030)
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#define SAI_RXDR (0x0034)
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#define SAI_PATH_SEL (0x0038)
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#define SAI_TX_SLOT_MASK0 (0x003c)
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#define SAI_TX_SLOT_MASK1 (0x0040)
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#define SAI_TX_SLOT_MASK2 (0x0044)
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#define SAI_TX_SLOT_MASK3 (0x0048)
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#define SAI_RX_SLOT_MASK0 (0x004c)
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#define SAI_RX_SLOT_MASK1 (0x0050)
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#define SAI_RX_SLOT_MASK2 (0x0054)
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#define SAI_RX_SLOT_MASK3 (0x0058)
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#define SAI_TX_DATA_CNT (0x005c)
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#define SAI_RX_DATA_CNT (0x0060)
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#define SAI_TX_SHIFT (0x0064)
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#define SAI_RX_SHIFT (0x0068)
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#define SAI_VERSION (0x0070)
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#endif /* _ROCKCHIP_SAI_H */
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