/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Rockchip Audio PWM driver
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*
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* Copyright (C) 2020 Fuzhou Rockchip Electronics Co., Ltd
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*
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*/
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#ifndef _ROCKCHIP_AUDIO_PWM_H
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#define _ROCKCHIP_AUDIO_PWM_H
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/* AUDIO PWM REGS offset */
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#define AUDPWM_VERSION (0x0000)
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#define AUDPWM_XFER (0x0004)
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#define AUDPWM_SRC_CFG (0x0008)
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#define AUDPWM_PWM_CFG (0x0010)
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#define AUDPWM_PWM_ST (0x0014)
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#define AUDPWM_PWM_BUF_01 (0x0018)
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#define AUDPWM_PWM_BUF_23 (0x001c)
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#define AUDPWM_FIFO_CFG (0x0020)
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#define AUDPWM_FIFO_LVL (0x0024)
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#define AUDPWM_FIFO_INT_EN (0x0028)
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#define AUDPWM_FIFO_INT_ST (0x002c)
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#define AUDPWM_FIFO_ENTRY (0x0080)
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#define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK((h), (l)) << 16))
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/* Transfer Control Register */
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#define AUDPWM_XFER_LSTOP HIWORD_UPDATE(1, 1, 1)
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#define AUDPWM_XFER_START HIWORD_UPDATE(1, 0, 0)
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#define AUDPWM_XFER_STOP HIWORD_UPDATE(0, 0, 0)
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/* Source Data Configuration Register */
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#define AUDPWM_ALIGN_LEFT HIWORD_UPDATE(1, 5, 5)
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#define AUDPWM_ALIGN_RIGHT HIWORD_UPDATE(0, 5, 5)
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#define AUDPWM_SRC_WIDTH(x) HIWORD_UPDATE((x) - 1, 4, 0)
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/* PWM Configuration Register */
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#define AUDPWM_SAMPLE_WIDTH(x) HIWORD_UPDATE((x) - 8, 9, 8)
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#define AUDPWM_LINEAR_INTERP_EN HIWORD_UPDATE(1, 4, 4)
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#define AUDPWM_INTERP_RATE(x) HIWORD_UPDATE((x), 3, 0)
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/* FIFO Configuration Register */
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#define AUDPWM_DMA_EN HIWORD_UPDATE(1, 7, 7)
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#define AUDPWM_DMA_DIS HIWORD_UPDATE(0, 7, 7)
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#define AUDPWM_DMA_WATERMARK(x) HIWORD_UPDATE((x) - 1, 4, 0)
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#endif /* _ROCKCHIP_AUDIO_PWM_H */
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