/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* ASoC PXA SSP port support
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*/
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#ifndef _PXA_SSP_H
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#define _PXA_SSP_H
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/* SSP clock sources */
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#define PXA_SSP_CLK_PLL 0
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#define PXA_SSP_CLK_EXT 1
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#define PXA_SSP_CLK_NET 2
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#define PXA_SSP_CLK_AUDIO 3
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#define PXA_SSP_CLK_NET_PLL 4
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/* SSP audio dividers */
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#define PXA_SSP_AUDIO_DIV_ACDS 0
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#define PXA_SSP_AUDIO_DIV_SCDB 1
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#define PXA_SSP_DIV_SCR 2
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/* SSP ACDS audio dividers values */
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#define PXA_SSP_CLK_AUDIO_DIV_1 0
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#define PXA_SSP_CLK_AUDIO_DIV_2 1
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#define PXA_SSP_CLK_AUDIO_DIV_4 2
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#define PXA_SSP_CLK_AUDIO_DIV_8 3
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#define PXA_SSP_CLK_AUDIO_DIV_16 4
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#define PXA_SSP_CLK_AUDIO_DIV_32 5
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/* SSP divider bypass */
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#define PXA_SSP_CLK_SCDB_4 0
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#define PXA_SSP_CLK_SCDB_1 1
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#define PXA_SSP_CLK_SCDB_8 2
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#define PXA_SSP_PLL_OUT 0
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#endif
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