/* SPDX-License-Identifier: GPL-2.0+
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*
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* linux/sound/soc/hisilicon/hi3660-i2s.c
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*
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* I2S IP driver for hi3660.
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*
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* Copyright (c) 2001-2021, Huawei Tech. Co., Ltd.
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*
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*/
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#ifndef _HI3660_I2S_H
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#define _HI3660_I2S_H
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enum hisi_bits {
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HII2S_BITS_16,
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HII2S_BITS_18,
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HII2S_BITS_20,
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HII2S_BITS_24,
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};
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enum hisi_i2s_rates {
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HII2S_FS_RATE_8KHZ = 0,
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HII2S_FS_RATE_16KHZ = 1,
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HII2S_FS_RATE_32KHZ = 2,
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HII2S_FS_RATE_48KHZ = 4,
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HII2S_FS_RATE_96KHZ = 5,
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HII2S_FS_RATE_192KHZ = 6,
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};
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#define HI_ASP_CFG_R_RST_CTRLEN_REG 0x0
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#define HI_ASP_CFG_R_RST_CTRLDIS_REG 0x4
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#define HI_ASP_CFG_R_GATE_EN_REG 0xC
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#define HI_ASP_CFG_R_GATE_DIS_REG 0x10
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#define HI_ASP_CFG_R_GATE_CLKEN_REG 0x14
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#define HI_ASP_CFG_R_GATE_CLKSTAT_REG 0x18
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#define HI_ASP_CFG_R_GATE_CLKDIV_EN_REG 0x1C
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#define HI_ASP_CFG_R_CLK1_DIV_REG 0x20
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#define HI_ASP_CFG_R_CLK2_DIV_REG 0x24
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#define HI_ASP_CFG_R_CLK3_DIV_REG 0x28
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#define HI_ASP_CFG_R_CLK4_DIV_REG 0x2C
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#define HI_ASP_CFG_R_CLK5_DIV_REG 0x30
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#define HI_ASP_CFG_R_CLK6_DIV_REG 0x34
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#define HI_ASP_CFG_R_CLK_SEL_REG 0x38
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#define HI_ASP_CFG_R_SEC_REG 0x100
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#define HI_ASP_SIO_VERSION_REG (0x3C)
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#define HI_ASP_SIO_MODE_REG (0x40)
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#define HI_ASP_SIO_INTSTATUS_REG (0x44)
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#define HI_ASP_SIO_INTCLR_REG (0x48)
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#define HI_ASP_SIO_I2S_LEFT_XD_REG (0x4C)
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#define HI_ASP_SIO_I2S_RIGHT_XD_REG (0x50)
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#define HI_ASP_SIO_I2S_LEFT_RD_REG (0x54)
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#define HI_ASP_SIO_I2S_RIGHT_RD_REG (0x58)
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#define HI_ASP_SIO_CT_SET_REG (0x5C)
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#define HI_ASP_SIO_CT_CLR_REG (0x60)
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#define HI_ASP_SIO_RX_STA_REG (0x68)
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#define HI_ASP_SIO_TX_STA_REG (0x6C)
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#define HI_ASP_SIO_DATA_WIDTH_SET_REG (0x78)
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#define HI_ASP_SIO_I2S_START_POS_REG (0x7C)
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#define HI_ASP_SIO_I2S_POS_FLAG_REG (0x80)
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#define HI_ASP_SIO_SIGNED_EXT_REG (0x84)
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#define HI_ASP_SIO_I2S_POS_MERGE_EN_REG (0x88)
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#define HI_ASP_SIO_INTMASK_REG (0x8C)
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#define HI_ASP_SIO_I2S_DUAL_RX_CHN_REG (0xA0)
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#define HI_ASP_SIO_I2S_DUAL_TX_CHN_REG (0xC0)
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#define HI_ASP_CFG_R_CLK_SEL_EN BIT(2)
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#define HI_ASP_CFG_R_CLK_SEL 0x140010
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#define HI_ASP_CFG_R_CLK1_DIV_SEL 0xbcdc9a
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#define HI_ASP_CFG_R_CLK4_DIV_SEL 0x00ff000f
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#define HI_ASP_CFG_R_CLK6_DIV_SEL 0x00ff003f
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#define HI_ASP_CFG_SIO_MODE 0
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#define HI_ASP_SIO_MODE_SEL_EN BIT(0)
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#define HI_ASP_MASK 0xffffffff
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#define HI_ASP_SIO_RX_ENABLE BIT(13)
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#define HI_ASP_SIO_TX_ENABLE BIT(12)
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#define HI_ASP_SIO_RX_FIFO_DISABLE BIT(11)
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#define HI_ASP_SIO_TX_FIFO_DISABLE BIT(10)
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#define HI_ASP_SIO_RX_DATA_MERGE BIT(9)
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#define HI_ASP_SIO_TX_DATA_MERGE BIT(8)
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#define HI_ASP_SIO_RX_FIFO_THRESHOLD (0x5 << 4)
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#define HI_ASP_SIO_TX_FIFO_THRESHOLD (0xB << 0)
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#define HI_ASP_SIO_RX_FIFO_THRESHOLD_CLR (0xF << 4)
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#define HI_ASP_SIO_TX_FIFO_THRESHOLD_CLR (0xF << 0)
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#define HI_ASP_SIO_BURST (0x4)
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enum hisi_i2s_formats {
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HII2S_FORMAT_I2S,
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HII2S_FORMAT_PCM_STD,
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HII2S_FORMAT_PCM_USER,
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HII2S_FORMAT_LEFT_JUST,
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HII2S_FORMAT_RIGHT_JUST,
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};
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#endif/* _HI3660_I2S_H */
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