/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Rockchip Audio Codec Digital driver
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*
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* Copyright (C) 2020 Rockchip Electronics Co., Ltd
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*
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*/
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#ifndef _RK_CODEC_DIGITAL_H
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#define _RK_CODEC_DIGITAL_H
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#define SYSCTRL0 0x0000
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#define ADCVUCTL 0x0040
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#define ADCVUCTIME 0x0044
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#define ADCDIGEN 0x0048
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#define ADCCLKCTRL 0x004C
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#define ADCINT_DIV 0x0054
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#define ADCSCLKTXINT_DIV 0x006C
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#define ADCCFG1 0x0084
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#define ADCVOLL0 0x0088
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#define ADCVOLL1 0x008C
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#define ADCVOLR0 0x0098
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#define ADCVOGP 0x00A8
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#define ADCRVOLL0 0x00AC
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#define ADCRVOLL1 0x00B0
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#define ADCRVOLR0 0x00BC
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#define ADCALC0 0x00CC
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#define ADCALC1 0x00D0
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#define ADCALC2 0x00D4
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#define ADCNG 0x00D8
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#define ADCNGST 0x00DC
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#define ADCHPFEN 0x00E0
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#define ADCHPFCF 0x00E4
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#define ADCPGL0 0x00EC
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#define ADCPGL1 0x00F0
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#define ADCPGR0 0x00FC
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#define ADCLILMT0 0x010C
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#define ADCLILMT1 0x0110
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#define ADCDMICNG0 0x0114
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#define ADCDMICNG1 0x0118
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#define DACVUCTL 0x0140
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#define DACVUCTIME 0x0144
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#define DACDIGEN 0x0148
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#define DACCLKCTRL 0x014C
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#define DACINT_DIV 0x0154
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#define DACSCLKRXINT_DIV 0x0160
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#define DACPWM_DIV 0x0164
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#define DACPWM_CTRL 0x0168
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#define DACCFG1 0x0184
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#define DACMUTE 0x0188
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#define DACMUTEST 0x018C
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#define DACVOLL0 0x0190
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#define DACVOLR0 0x01A0
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#define DACVOGP 0x01B0
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#define DACRVOLL0 0x01B4
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#define DACRVOLR0 0x01C4
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#define DACLMT0 0x01D4
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#define DACLMT1 0x01D8
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#define DACLMT2 0x01DC
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#define DACMIXCTRLL 0x01E0
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#define DACMIXCTRLR 0x01E4
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#define DACHPF 0x01E8
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#define I2S_TXCR0 0x0300
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#define I2S_TXCR1 0x0304
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#define I2S_TXCR2 0x0308
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#define I2S_RXCR0 0x030C
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#define I2S_RXCR1 0x0310
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#define I2S_CKR0 0x0314
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#define I2S_CKR1 0x0318
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#define I2S_XFER 0x031C
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#define I2S_CLR 0x0320
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#define VERSION 0x0380
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/* SYSCTRL0 */
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#define ACDCDIG_SYSCTRL0_SYNC_SEL_MASK BIT(1)
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#define ACDCDIG_SYSCTRL0_SYNC_SEL_DAC BIT(1)
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#define ACDCDIG_SYSCTRL0_SYNC_SEL_ADC 0
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#define ACDCDIG_SYSCTRL0_GLB_CKE_MASK BIT(3)
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#define ACDCDIG_SYSCTRL0_GLB_CKE_EN BIT(3)
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#define ACDCDIG_SYSCTRL0_GLB_CKE_DIS 0
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#define ACDCDIG_SYSCTRL0_CLK_COM_SEL_MASK BIT(4)
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#define ACDCDIG_SYSCTRL0_CLK_COM_SEL_DAC BIT(4)
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#define ACDCDIG_SYSCTRL0_CLK_COM_SEL_ADC 0
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#define ACDCDIG_SYSCTRL0_SYNC_MODE_MASK BIT(5)
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#define ACDCDIG_SYSCTRL0_SYNC_MODE_SYNC BIT(5)
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#define ACDCDIG_SYSCTRL0_SYNC_MODE_ASYNC 0
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/* ADCVUCTL */
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#define ACDCDIG_ADCVUCTL_ADC_BYPS_MASK BIT(2)
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#define ACDCDIG_ADCVUCTL_ADC_BYPS BIT(2)
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/* ADCDIGEN */
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#define ACDCDIG_ADCDIGEN_ADCEN_L0R1_MASK BIT(0)
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#define ACDCDIG_ADCDIGEN_ADCEN_L0R1_EN BIT(0)
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#define ACDCDIG_ADCDIGEN_ADCEN_L0R1_DIS 0
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#define ACDCDIG_ADCDIGEN_ADCEN_L2_MASK BIT(1)
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#define ACDCDIG_ADCDIGEN_ADCEN_L2_EN BIT(1)
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#define ACDCDIG_ADCDIGEN_ADCEN_L2_DIS 0
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#define ACDCDIG_ADCDIGEN_ADC_GLBEN_MASK BIT(4)
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#define ACDCDIG_ADCDIGEN_ADC_GLBEN_EN BIT(4)
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#define ACDCDIG_ADCDIGEN_ADC_GLBEN_DIS 0
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/* ADCCLKCTRL */
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#define ACDCDIG_ADCCLKCTRL_ADC_SYNC_STATUS_MASK BIT(0)
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#define ACDCDIG_ADCCLKCTRL_ADC_SYNC_ENA_MASK BIT(1)
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#define ACDCDIG_ADCCLKCTRL_ADC_SYNC_ENA_EN BIT(1)
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#define ACDCDIG_ADCCLKCTRL_ADC_SYNC_ENA_DIS 0
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#define ACDCDIG_ADCCLKCTRL_FILTER_GATE_EN_MASK BIT(2)
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#define ACDCDIG_ADCCLKCTRL_FILTER_GATE_EN BIT(2)
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#define ACDCDIG_ADCCLKCTRL_CKE_BCLKTX_MASK BIT(3)
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#define ACDCDIG_ADCCLKCTRL_CKE_BCLKTX_EN BIT(3)
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#define ACDCDIG_ADCCLKCTRL_CKE_BCLKTX_DIS 0
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#define ACDCDIG_ADCCLKCTRL_I2STX_CKE_MASK BIT(4)
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#define ACDCDIG_ADCCLKCTRL_I2STX_CKE_EN BIT(4)
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#define ACDCDIG_ADCCLKCTRL_I2STX_CKE_DIS 0
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#define ACDCDIG_ADCCLKCTRL_ADC_CKE_MASK BIT(5)
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#define ACDCDIG_ADCCLKCTRL_ADC_CKE_EN BIT(5)
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#define ACDCDIG_ADCCLKCTRL_ADC_CKE_DIS 0
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#define ACDCDIG_ADCCLKCTRL_CIC_DS_RATIO_MASK GENMASK(7, 6)
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#define ACDCDIG_ADCCLKCTRL_CIC_DS_RATIO_16 (0x0 << 6)
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#define ACDCDIG_ADCCLKCTRL_CIC_DS_RATIO_8 (0x1 << 6)
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#define ACDCDIG_ADCCLKCTRL_CIC_DS_RATIO_4 (0x2 << 6)
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/* ADCINT_DIV */
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#define ACDCDIG_ADCINT_DIV_INT_DIV_CON_MASK GENMASK(7, 0)
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#define ACDCDIG_ADCINT_DIV_INT_DIV_CON(x) ((x) - 1)
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/* ADCSCLKTXINT_DIV */
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#define ACDCDIG_ADCSCLKTXINT_DIV_SCKTXDIV_MASK GENMASK(7, 0)
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#define ACDCDIG_ADCSCLKTXINT_DIV_SCKTXDIV(x) ((x) - 1)
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/* ADCCFG1 */
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#define ACDCDIG_ADCCFG1_FIR_COM_BPS_MASK BIT(0)
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#define ACDCDIG_ADCCFG1_FIR_COM_BPS_EN BIT(0)
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#define ACDCDIG_ADCCFG1_SIG_SCALE_MODE_MASK BIT(1)
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#define ACDCDIG_ADCCFG1_SIG_SCALE_MODE_HALF BIT(1)
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#define ACDCDIG_ADCCFG1_ADCSRT_MASK GENMASK(4, 2)
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#define ACDCDIG_ADCCFG1_ADCSRT(x) (((x) & 0x7) << 2)
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/* ADCVOLL0 */
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#define ACDCDIG_ADCVOLL0_ADCLV0_MASK GENMASK(7, 0)
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#define ACDCDIG_ADCVOLL0_ADCLV0(x) (x)
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/* ADCVOLL1 */
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#define ACDCDIG_ADCVOLL1_ADCLV1_MASK GENMASK(7, 0)
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#define ACDCDIG_ADCVOLL1_ADCLV1(x) (x)
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/* ADCVOLR0 */
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#define ACDCDIG_ADCVOLR0_ADCRV0_MASK GENMASK(7, 0)
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#define ACDCDIG_ADCVOLR0_ADCRV0(x) (x)
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/* ADCVOGP */
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#define ACDCDIG_ADCVOGP_VOLGPL0_MASK BIT(0)
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#define ACDCDIG_ADCVOGP_VOLGPL0_POS BIT(0)
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#define ACDCDIG_ADCVOGP_VOLGPL0_NEG 0
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#define ACDCDIG_ADCVOGP_VOLGPR0_MASK BIT(1)
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#define ACDCDIG_ADCVOGP_VOLGPR0_POS BIT(1)
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#define ACDCDIG_ADCVOGP_VOLGPR0_NEG 0
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#define ACDCDIG_ADCVOGP_VOLGPL1_MASK BIT(2)
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#define ACDCDIG_ADCVOGP_VOLGPL1_POS BIT(2)
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#define ACDCDIG_ADCVOGP_VOLGPL1_NEG 0
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/* ADCALC0 */
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#define ACDCDIG_ADCALC0_ALCL0_MASK BIT(0)
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#define ACDCDIG_ADCALC0_ALCL0_EN BIT(0)
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#define ACDCDIG_ADCALC0_ALCR0_MASK BIT(1)
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#define ACDCDIG_ADCALC0_ALCR0_EN BIT(1)
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#define ACDCDIG_ADCALC0_ALCL1_MASK BIT(2)
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#define ACDCDIG_ADCALC0_ALCL1_EN BIT(2)
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/* ADCALC1 */
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#define ACDCDIG_ADCALC1_ALCRRATE_MASK GENMASK(3, 0)
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#define ACDCDIG_ADCALC1_ALCRRATE(x) ((x) & 0xf)
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#define ACDCDIG_ADCALC1_ALCARATE_MASK GENMASK(7, 4)
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#define ACDCDIG_ADCALC1_ALCARATE(x) (((x) & 0xf) << 4)
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/* ADCALC2 */
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#define ACDCDIG_ADCALC2_ALCMIN_MASK GENMASK(2, 0)
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#define ACDCDIG_ADCALC2_ALCMIN(x) ((x) & 0x7)
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#define ACDCDIG_ADCALC2_ALCMAX_MASK GENMASK(6, 4)
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#define ACDCDIG_ADCALC2_ALCMAX(x) (((x) & 0x7) << 4)
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/* ADCHPFEN */
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#define ACDCDIG_ADCHPFEN_HPFEN_L0_MASK BIT(0)
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#define ACDCDIG_ADCHPFEN_HPFEN_L0_EN BIT(0)
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#define ACDCDIG_ADCHPFEN_HPFEN_R0_MASK BIT(1)
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#define ACDCDIG_ADCHPFEN_HPFEN_R0_EN BIT(1)
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#define ACDCDIG_ADCHPFEN_HPFEN_L1_MASK BIT(2)
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#define ACDCDIG_ADCHPFEN_HPFEN_L1_EN BIT(2)
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/* ADCHPFCF */
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#define ACDCDIG_ADCHPFCF_HPFCF_MASK GENMASK(1, 0)
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#define ACDCDIG_ADCHPFCF_HPFCF_493HZ 3
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#define ACDCDIG_ADCHPFCF_HPFCF_243HZ 2
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#define ACDCDIG_ADCHPFCF_HPFCF_60HZ 1
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#define ACDCDIG_ADCHPFCF_HPFCF_3P79HZ 0
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/* ADCPGL0 */
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#define ACDCDIG_ADCPGL0_PGA_L0_MASK GENMASK(3, 0)
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/* ADCPGL1 */
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#define ACDCDIG_ADCPGL1_PGA_L1_MASK GENMASK(3, 0)
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/* ADCPGR0 */
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#define ACDCDIG_ADCPGR0_PGA_R0_MASK GENMASK(3, 0)
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/* DACDIGEN */
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#define ACDCDIG_DACDIGEN_DACEN_L0R1_MASK BIT(0)
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#define ACDCDIG_DACDIGEN_DACEN_L0R1_EN BIT(0)
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#define ACDCDIG_DACDIGEN_DACEN_L0R1_DIS 0
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#define ACDCDIG_DACDIGEN_DAC_GLBEN_MASK BIT(4)
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#define ACDCDIG_DACDIGEN_DAC_GLBEN_EN BIT(4)
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#define ACDCDIG_DACDIGEN_DAC_GLBEN_DIS 0
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/* DACCLKCTRL */
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#define ACDCDIG_DACCLKCTRL_DAC_MODE_ATTENU_MASK BIT(0)
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#define ACDCDIG_DACCLKCTRL_DAC_MODE_ATTENU_EN BIT(0)
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#define ACDCDIG_DACCLKCTRL_DAC_MODE_ATTENU_DIS 0
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#define ACDCDIG_DACCLKCTRL_DAC_SYNC_STATUS_MASK BIT(1)
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#define ACDCDIG_DACCLKCTRL_DAC_SYNC_STATUS_DONE 0
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#define ACDCDIG_DACCLKCTRL_DAC_SYNC_ENA_MASK BIT(2)
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#define ACDCDIG_DACCLKCTRL_DAC_SYNC_ENA_EN BIT(2)
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#define ACDCDIG_DACCLKCTRL_DAC_SYNC_ENA_DIS 0
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#define ACDCDIG_DACCLKCTRL_CKE_BCLKRX_MASK BIT(3)
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#define ACDCDIG_DACCLKCTRL_CKE_BCLKRX_EN BIT(3)
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#define ACDCDIG_DACCLKCTRL_CKE_BCLKRX_DIS 0
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#define ACDCDIG_DACCLKCTRL_I2SRX_CKE_MASK BIT(4)
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#define ACDCDIG_DACCLKCTRL_I2SRX_CKE_EN BIT(4)
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#define ACDCDIG_DACCLKCTRL_I2SRX_CKE_DIS 0
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#define ACDCDIG_DACCLKCTRL_DAC_CKE_MASK BIT(5)
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#define ACDCDIG_DACCLKCTRL_DAC_CKE_EN BIT(5)
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#define ACDCDIG_DACCLKCTRL_DAC_CKE_DIS 0
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/* DACINT_DIV */
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#define ACDCDIG_DACINT_DIV_INT_DIV_CON_MASK GENMASK(7, 0)
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#define ACDCDIG_DACINT_DIV_INT_DIV_CON(x) ((x) - 1)
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/* DACSCLKRXINT_DIV */
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#define ACDCDIG_DACSCLKRXINT_DIV_SCKRXDIV_MASK GENMASK(7, 0)
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#define ACDCDIG_DACSCLKRXINT_DIV_SCKRXDIV(x) ((x) - 1)
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/* DACPWM_DIV */
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#define ACDCDIG_DACPWM_DIV_AUDIO_PWM_DIV_MASK GENMASK(7, 0)
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#define ACDCDIG_DACPWM_DIV_AUDIO_PWM_DIV(x) ((x) - 1)
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/* DACPWM_CTRL */
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#define ACDCDIG_DACPWM_CTRL_DITH_SEL_MASK GENMASK(2, 0)
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#define ACDCDIG_DACPWM_CTRL_DITH_SEL(x) (x)
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#define ACDCDIG_DACPWM_CTRL_PWM_EN_MASK BIT(3)
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#define ACDCDIG_DACPWM_CTRL_PWM_EN BIT(3)
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#define ACDCDIG_DACPWM_CTRL_PWM_DIS 0
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#define ACDCDIG_DACPWM_CTRL_PWM_MODE_MASK GENMASK(5, 4)
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#define ACDCDIG_DACPWM_CTRL_PWM_MODE_1 (0x2 << 4)
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#define ACDCDIG_DACPWM_CTRL_PWM_MODE_0 (0x1 << 4)
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#define ACDCDIG_DACPWM_CTRL_PWM_MODE_DAC (0x0 << 4)
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#define ACDCDIG_DACPWM_CTRL_PWM_MODE_CKE_MASK BIT(6)
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#define ACDCDIG_DACPWM_CTRL_PWM_MODE_CKE_EN BIT(6)
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#define ACDCDIG_DACPWM_CTRL_PWM_MODE_CKE_DIS 0
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/* DACCFG1 */
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#define ACDCDIG_DACCFG1_DACSRT_MASK GENMASK(4, 2)
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#define ACDCDIG_DACCFG1_DACSRT(x) ((x) << 2)
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/* DACMUTE */
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#define ACDCDIG_DACMUTE_DACMT_MASK BIT(0)
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#define ACDCDIG_DACMUTE_DACUNMT_MASK BIT(1)
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/* DACVOLL0 */
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#define ACDCDIG_DACVOLL0_DACLV0_MASK GENMASK(7, 0)
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#define ACDCDIG_DACVOLL0_DACLV0(x) (x)
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/* DACVOLR0 */
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#define ACDCDIG_DACVOLR0_DACRV0_MASK GENMASK(7, 0)
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#define ACDCDIG_DACVOLR0_DACRV0(x) (x)
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/* DACVOGP */
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#define ACDCDIG_DACVOGP_VOLGPL0_MASK BIT(0)
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#define ACDCDIG_DACVOGP_VOLGPL0_POS BIT(0)
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#define ACDCDIG_DACVOGP_VOLGPL0_NEG 0
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#define ACDCDIG_DACVOGP_VOLGPR0_MASK BIT(1)
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#define ACDCDIG_DACVOGP_VOLGPR0_POS BIT(1)
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#define ACDCDIG_DACVOGP_VOLGPR0_NEG 0
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/* DACMIXCTRLL */
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#define ACDCDIG_DACMIXCTRLL_MIXMODE_L0_MASK GENMASK(1, 0)
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#define ACDCDIG_DACMIXCTRLL_MIXMODE_L0_LR 2
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#define ACDCDIG_DACMIXCTRLL_MIXMODE_L0_R 1
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#define ACDCDIG_DACMIXCTRLL_MIXMODE_L0_L 0
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/* DACMIXCTRLR */
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#define ACDCDIG_DACMIXCTRLR_MIXMODE_R0_MASK GENMASK(1, 0)
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#define ACDCDIG_DACMIXCTRLR_MIXMODE_R0_LR 2
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#define ACDCDIG_DACMIXCTRLR_MIXMODE_R0_L 1
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#define ACDCDIG_DACMIXCTRLR_MIXMODE_R0_R 0
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/* DACHPF */
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#define ACDCDIG_DACHPF_HPFEN_L0R0_MASK BIT(0)
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#define ACDCDIG_DACHPF_HPFEN_L0R0_EN BIT(0)
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#define ACDCDIG_DACHPF_HPFCF_MASK GENMASK(5, 4)
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#define ACDCDIG_DACHPF_HPFCF_140HZ (0x3 << 4)
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#define ACDCDIG_DACHPF_HPFCF_120HZ (0x2 << 4)
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#define ACDCDIG_DACHPF_HPFCF_100HZ (0x1 << 4)
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#define ACDCDIG_DACHPF_HPFCF_80HZ (0x0 << 4)
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/* I2S_TXCR0 */
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#define ACDCDIG_I2S_TXCR0_VDW_MASK GENMASK(4, 0)
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#define ACDCDIG_I2S_TXCR0_VDW(x) ((x) - 1)
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/* I2S_TXCR1 */
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#define ACDCDIG_I2S_TXCR1_CEX_MASK BIT(4)
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#define ACDCDIG_I2S_TXCR1_CEX_EXCHANGE BIT(4)
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#define ACDCDIG_I2S_TXCR1_TCSR_MASK GENMASK(7, 6)
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#define ACDCDIG_I2S_TXCR1_TCSR_4CH (0x1 << 6)
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#define ACDCDIG_I2S_TXCR1_TCSR_2CH (0x0 << 6)
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/* I2S_RXCR0 */
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#define ACDCDIG_I2S_RXCR0_VDW_MASK GENMASK(4, 0)
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#define ACDCDIG_I2S_RXCR0_VDW(x) ((x) - 1)
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/* I2S_RXCR1 */
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#define ACDCDIG_I2S_RXCR1_CEX_MASK BIT(4)
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#define ACDCDIG_I2S_RXCR1_CEX_EXCHANGE BIT(4)
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#define ACDCDIG_I2S_RXCR1_RCSR_MASK GENMASK(7, 6)
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#define ACDCDIG_I2S_RXCR1_RCSR_2CH (0x0 << 6)
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/* I2S_CKR0 */
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#define ACDCDIG_I2S_CKR0_TSD_MASK GENMASK(1, 0)
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#define ACDCDIG_I2S_CKR0_TSD_64 (0 << 0)
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#define ACDCDIG_I2S_CKR0_TSD_128 (1 << 0)
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#define ACDCDIG_I2S_CKR0_TSD_256 (2 << 0)
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#define ACDCDIG_I2S_CKR0_RSD_MASK GENMASK(3, 2)
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#define ACDCDIG_I2S_CKR0_RSD_64 (0 << 2)
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#define ACDCDIG_I2S_CKR0_RSD_128 (1 << 2)
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#define ACDCDIG_I2S_CKR0_RSD_256 (2 << 2)
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/* I2S_CKR1 */
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#define ACDCDIG_I2S_CKR1_TLP_MASK BIT(0)
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#define ACDCDIG_I2S_CKR1_TLP_INVERTED BIT(0)
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#define ACDCDIG_I2S_CKR1_TLP_NORMAL 0
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#define ACDCDIG_I2S_CKR1_RLP_MASK BIT(1)
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#define ACDCDIG_I2S_CKR1_RLP_INVERTED BIT(1)
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#define ACDCDIG_I2S_CKR1_RLP_NORMAL 0
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#define ACDCDIG_I2S_CKR1_CKP_MASK BIT(2)
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#define ACDCDIG_I2S_CKR1_CKP_INVERTED BIT(2)
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#define ACDCDIG_I2S_CKR1_CKP_NORMAL 0
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#define ACDCDIG_I2S_CKR1_MSS_MASK BIT(3)
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#define ACDCDIG_I2S_CKR1_MSS_MASTER 0
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/* I2S_XFER */
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#define ACDCDIG_I2S_XFER_TXS_MASK BIT(0)
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#define ACDCDIG_I2S_XFER_TXS_START BIT(0)
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#define ACDCDIG_I2S_XFER_TXS_STOP 0
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#define ACDCDIG_I2S_XFER_RXS_MASK BIT(1)
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#define ACDCDIG_I2S_XFER_RXS_START BIT(1)
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#define ACDCDIG_I2S_XFER_RXS_STOP 0
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/* I2S_CLR */
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#define ACDCDIG_I2S_CLR_TXC_MASK BIT(0)
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#define ACDCDIG_I2S_CLR_TXC_CLR BIT(0)
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#define ACDCDIG_I2S_CLR_RXC_MASK BIT(1)
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#define ACDCDIG_I2S_CLR_RXC_CLR BIT(1)
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#endif
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