/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* @Descripttion: Header file of AW87XXX_PID_59_5X9_REG
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* @version: V1.33
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* @Author: zhaozhongbo
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* @Date: 2021-03-10
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* @LastEditors: Please set LastEditors
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* @LastEditTime: 2021-03-10
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*/
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#ifndef __AW87XXX_PID_59_5X9_REG_H__
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#define __AW87XXX_PID_59_5X9_REG_H__
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#define AW87XXX_PID_59_5X9_REG_CHIPID (0x00)
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#define AW87XXX_PID_59_5X9_REG_SYSCTRL (0x01)
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#define AW87XXX_PID_59_5X9_REG_BATSAFE (0x02)
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#define AW87XXX_PID_59_5X9_REG_BSTOVR (0x03)
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#define AW87XXX_PID_59_5X9_REG_BSTVPR (0x04)
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#define AW87XXX_PID_59_5X9_REG_PAGR (0x05)
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#define AW87XXX_PID_59_5X9_REG_PAGC3OPR (0x06)
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#define AW87XXX_PID_59_5X9_REG_PAGC3PR (0x07)
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#define AW87XXX_PID_59_5X9_REG_PAGC2OPR (0x08)
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#define AW87XXX_PID_59_5X9_REG_PAGC2PR (0x09)
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#define AW87XXX_PID_59_5X9_REG_PAGC1PR (0x0A)
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#define AW87XXX_PID_59_5X9_REG_SYSST (0x58)
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#define AW87XXX_PID_59_5X9_REG_SYSINT (0x59)
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#define AW87XXX_PID_59_5X9_REG_CPCR (0x60)
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#define AW87XXX_PID_59_5X9_REG_DFT1R (0x61)
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#define AW87XXX_PID_59_5X9_REG_DFT2R (0x62)
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#define AW87XXX_PID_59_5X9_REG_DFT3R (0x63)
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#define AW87XXX_PID_59_5X9_REG_DFT4R (0x64)
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#define AW87XXX_PID_59_5X9_REG_DFT5R (0x65)
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#define AW87XXX_PID_59_5X9_REG_DFT6R (0x66)
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#define AW87XXX_PID_59_5X9_REG_DFT7R (0x67)
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#define AW87XXX_PID_59_5X9_REG_DFT8R (0x68)
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#define AW87XXX_PID_59_5X9_REG_ENCR (0x69)
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#define AW87XXX_PID_59_5X9_ENCRY_DEFAULT (0x00)
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/********************************************
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* soft control info
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* If you need to update this file, add this information manually
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*******************************************/
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unsigned char aw87xxx_pid_59_5x9_softrst_access[2] = {0x00, 0xaa};
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/********************************************
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* Register Access
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*******************************************/
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#define AW87XXX_PID_59_5X9_REG_MAX (0x70)
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#define REG_NONE_ACCESS (0)
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#define REG_RD_ACCESS (1 << 0)
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#define REG_WR_ACCESS (1 << 1)
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const unsigned char aw87xxx_pid_59_5x9_reg_access[AW87XXX_PID_59_5X9_REG_MAX] = {
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[AW87XXX_PID_59_5X9_REG_CHIPID] = (REG_RD_ACCESS),
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[AW87XXX_PID_59_5X9_REG_SYSCTRL] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_5X9_REG_BATSAFE] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_5X9_REG_BSTOVR] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_5X9_REG_BSTVPR] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_5X9_REG_PAGR] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_5X9_REG_PAGC3OPR] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_5X9_REG_PAGC3PR] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_5X9_REG_PAGC2OPR] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_5X9_REG_PAGC2PR] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_5X9_REG_PAGC1PR] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_5X9_REG_SYSST] = (REG_RD_ACCESS),
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[AW87XXX_PID_59_5X9_REG_SYSINT] = (REG_RD_ACCESS),
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[AW87XXX_PID_59_5X9_REG_CPCR] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_5X9_REG_DFT1R] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_5X9_REG_DFT2R] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_5X9_REG_DFT3R] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_5X9_REG_DFT4R] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_5X9_REG_DFT5R] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_5X9_REG_DFT6R] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_5X9_REG_DFT7R] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_5X9_REG_DFT8R] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_5X9_REG_ENCR] = (REG_RD_ACCESS | REG_WR_ACCESS),
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};
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/* RCV_MODE bit 3 (SYSCTRL 0x01) */
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#define AW87XXX_PID_59_5X9_REC_MODE_START_BIT (3)
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#define AW87XXX_PID_59_5X9_REC_MODE_BITS_LEN (1)
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#define AW87XXX_PID_59_5X9_REC_MODE_MASK \
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(~(((1<<AW87XXX_PID_59_5X9_REC_MODE_BITS_LEN)-1) << AW87XXX_PID_59_5X9_REC_MODE_START_BIT))
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#define AW87XXX_PID_59_5X9_REC_MODE_DISABLE (0)
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#define AW87XXX_PID_59_5X9_REC_MODE_DISABLE_VALUE \
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(AW87XXX_PID_59_5X9_REC_MODE_DISABLE << AW87XXX_PID_59_5X9_REC_MODE_START_BIT)
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#define AW87XXX_PID_59_5X9_REC_MODE_ENABLE (1)
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#define AW87XXX_PID_59_5X9_REC_MODE_ENABLE_VALUE \
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(AW87XXX_PID_59_5X9_REC_MODE_ENABLE << AW87XXX_PID_59_5X9_REC_MODE_START_BIT)
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#endif
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