/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Rockchip Vehicle driver
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*
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* Copyright (C) 2022 Rockchip Electronics Co., Ltd.
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*/
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#ifndef _VEHICLE_CSI2_DPHY_COMMON_H_
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#define _VEHICLE_CSI2_DPHY_COMMON_H_
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#include <linux/kernel.h>
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#include <linux/rk-camera-module.h>
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#include <media/v4l2-subdev.h>
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#include "vehicle_samsung_dcphy_common.h"
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#include "../../../media/platform/rockchip/cif/mipi-csi2.h"
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/* RK3562 DPHY GRF REG OFFSET */
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#define RK3562_GRF_VI_CON0 (0x0520)
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#define RK3562_GRF_VI_CON1 (0x0524)
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/* GRF REG OFFSET */
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#define GRF_VI_CON0 (0x0340)
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#define GRF_VI_CON1 (0x0344)
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/*RK3588 DPHY GRF REG OFFSET */
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#define GRF_DPHY_CON0 (0x0)
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#define GRF_SOC_CON2 (0x0308)
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/*GRF REG BIT DEFINE */
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#define GRF_CSI2PHY_LANE_SEL_SPLIT (0x1)
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#define GRF_CSI2PHY_SEL_SPLIT_0_1 (0x0)
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#define GRF_CSI2PHY_SEL_SPLIT_2_3 BIT(0)
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/*RK3588 DCPHY GRF REG OFFSET */
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#define GRF_DCPHY_CON0 (0x0)
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/* PHY REG OFFSET */
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#define CSI2_DPHY_CTRL_INVALID_OFFSET (0xffff)
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#define CSI2_DPHY_CTRL_PWRCTL \
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CSI2_DPHY_CTRL_INVALID_OFFSET
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#define CSI2_DPHY_CTRL_LANE_ENABLE (0x00)
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#define CSI2_DPHY_CLK1_LANE_EN (0x2C)
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#define CSI2_DPHY_DUAL_CAL_EN (0x80)
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#define CSI2_DPHY_CLK_WR_THS_SETTLE (0x160)
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#define CSI2_DPHY_CLK_CALIB_EN (0x168)
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#define CSI2_DPHY_LANE0_WR_THS_SETTLE (0x1e0)
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#define CSI2_DPHY_LANE0_CALIB_EN (0x1e8)
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#define CSI2_DPHY_LANE1_WR_THS_SETTLE (0x260)
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#define CSI2_DPHY_LANE1_CALIB_EN (0x268)
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#define CSI2_DPHY_LANE2_WR_THS_SETTLE (0x2e0)
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#define CSI2_DPHY_LANE2_CALIB_EN (0x2e8)
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#define CSI2_DPHY_LANE3_WR_THS_SETTLE (0x360)
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#define CSI2_DPHY_LANE3_CALIB_EN (0x368)
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#define CSI2_DPHY_CLK1_WR_THS_SETTLE (0x3e0)
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#define CSI2_DPHY_CLK1_CALIB_EN (0x3e8)
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//DCPHY
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#define CSI2_DCPHY_CLK_WR_THS_SETTLE (0x030)
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#define CSI2_DCPHY_LANE0_WR_THS_SETTLE (0x130)
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#define CSI2_DCPHY_LANE0_WR_ERR_SOT_SYNC (0x134)
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#define CSI2_DCPHY_LANE1_WR_THS_SETTLE (0x230)
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#define CSI2_DCPHY_LANE1_WR_ERR_SOT_SYNC (0x234)
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#define CSI2_DCPHY_LANE2_WR_THS_SETTLE (0x330)
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#define CSI2_DCPHY_LANE2_WR_ERR_SOT_SYNC (0x334)
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#define CSI2_DCPHY_LANE3_WR_THS_SETTLE (0x430)
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#define CSI2_DCPHY_LANE3_WR_ERR_SOT_SYNC (0x434)
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#define CSI2_DCPHY_CLK_LANE_ENABLE (0x000)
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#define CSI2_DCPHY_DATA_LANE0_ENABLE (0x100)
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#define CSI2_DCPHY_DATA_LANE1_ENABLE (0x200)
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#define CSI2_DCPHY_DATA_LANE2_ENABLE (0x300)
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#define CSI2_DCPHY_DATA_LANE3_ENABLE (0x400)
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#define CSI2_DCPHY_S0C_GNR_CON1 (0x004)
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#define CSI2_DCPHY_S0C_ANA_CON1 (0x00c)
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#define CSI2_DCPHY_S0C_ANA_CON2 (0x010)
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#define CSI2_DCPHY_S0C_ANA_CON3 (0x014)
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#define CSI2_DCPHY_COMBO_S0D0_GNR_CON1 (0x104)
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#define CSI2_DCPHY_COMBO_S0D0_ANA_CON1 (0x10c)
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#define CSI2_DCPHY_COMBO_S0D0_ANA_CON2 (0x110)
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#define CSI2_DCPHY_COMBO_S0D0_ANA_CON3 (0x114)
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#define CSI2_DCPHY_COMBO_S0D0_ANA_CON6 (0x120)
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#define CSI2_DCPHY_COMBO_S0D0_ANA_CON7 (0x124)
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#define CSI2_DCPHY_COMBO_S0D0_DESKEW_CON0 (0x140)
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#define CSI2_DCPHY_COMBO_S0D0_DESKEW_CON2 (0x148)
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#define CSI2_DCPHY_COMBO_S0D0_DESKEW_CON4 (0x150)
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#define CSI2_DCPHY_COMBO_S0D0_CRC_CON1 (0x164)
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#define CSI2_DCPHY_COMBO_S0D0_CRC_CON2 (0x168)
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#define CSI2_DCPHY_COMBO_S0D1_GNR_CON1 (0x204)
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#define CSI2_DCPHY_COMBO_S0D1_ANA_CON1 (0x20c)
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#define CSI2_DCPHY_COMBO_S0D1_ANA_CON2 (0x210)
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#define CSI2_DCPHY_COMBO_S0D1_ANA_CON3 (0x214)
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#define CSI2_DCPHY_COMBO_S0D1_ANA_CON6 (0x220)
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#define CSI2_DCPHY_COMBO_S0D1_ANA_CON7 (0x224)
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#define CSI2_DCPHY_COMBO_S0D1_DESKEW_CON0 (0x240)
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#define CSI2_DCPHY_COMBO_S0D1_DESKEW_CON2 (0x248)
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#define CSI2_DCPHY_COMBO_S0D1_DESKEW_CON4 (0x250)
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#define CSI2_DCPHY_COMBO_S0D1_CRC_CON1 (0x264)
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#define CSI2_DCPHY_COMBO_S0D1_CRC_CON2 (0x268)
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#define CSI2_DCPHY_COMBO_S0D2_GNR_CON1 (0x304)
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#define CSI2_DCPHY_COMBO_S0D2_ANA_CON1 (0x30c)
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#define CSI2_DCPHY_COMBO_S0D2_ANA_CON2 (0x310)
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#define CSI2_DCPHY_COMBO_S0D2_ANA_CON3 (0x314)
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#define CSI2_DCPHY_COMBO_S0D2_ANA_CON6 (0x320)
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#define CSI2_DCPHY_COMBO_S0D2_ANA_CON7 (0x324)
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#define CSI2_DCPHY_COMBO_S0D2_DESKEW_CON0 (0x340)
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#define CSI2_DCPHY_COMBO_S0D2_DESKEW_CON2 (0x348)
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#define CSI2_DCPHY_COMBO_S0D2_DESKEW_CON4 (0x350)
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#define CSI2_DCPHY_COMBO_S0D2_CRC_CON1 (0x364)
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#define CSI2_DCPHY_COMBO_S0D2_CRC_CON2 (0x368)
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#define CSI2_DCPHY_S0D3_GNR_CON1 (0x404)
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#define CSI2_DCPHY_S0D3_ANA_CON1 (0x40c)
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#define CSI2_DCPHY_S0D3_ANA_CON2 (0x410)
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#define CSI2_DCPHY_S0D3_ANA_CON3 (0x414)
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#define CSI2_DCPHY_S0D3_DESKEW_CON0 (0x440)
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#define CSI2_DCPHY_S0D3_DESKEW_CON2 (0x448)
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#define CSI2_DCPHY_S0D3_DESKEW_CON4 (0x450)
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/* PHY REG BIT DEFINE */
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#define CSI2_DPHY_LANE_MODE_FULL (0x4)
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#define CSI2_DPHY_LANE_MODE_SPLIT (0x2)
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#define CSI2_DPHY_LANE_SPLIT_TOP (0x1)
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#define CSI2_DPHY_LANE_SPLIT_BOT (0x2)
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#define CSI2_DPHY_LANE_SPLIT_LANE0_1 (0x3 << 2)
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#define CSI2_DPHY_LANE_SPLIT_LANE2_3 (0x3 << 4)
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#define CSI2_DPHY_LANE_DUAL_MODE_EN BIT(6)
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#define CSI2_DPHY_LANE_PARA_ARR_NUM (0x2)
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#define CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT 2
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#define CSI2_DPHY_CTRL_DATALANE_SPLIT_LANE2_3_OFFSET_BIT 4
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#define CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT 6
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enum csi2_dphy_index {
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DPHY0 = 0x0,
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DPHY1,
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DPHY2,
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};
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enum csi2_dphy_lane {
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CSI2_DPHY_LANE_CLOCK = 0,
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CSI2_DPHY_LANE_CLOCK1,
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CSI2_DPHY_LANE_DATA0,
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CSI2_DPHY_LANE_DATA1,
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CSI2_DPHY_LANE_DATA2,
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CSI2_DPHY_LANE_DATA3
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};
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enum grf_reg_id {
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GRF_DPHY_RX0_TURNDISABLE = 0,
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GRF_DPHY_RX0_FORCERXMODE,
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GRF_DPHY_RX0_FORCETXSTOPMODE,
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GRF_DPHY_RX0_ENABLE,
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GRF_DPHY_RX0_TESTCLR,
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GRF_DPHY_RX0_TESTCLK,
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GRF_DPHY_RX0_TESTEN,
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GRF_DPHY_RX0_TESTDIN,
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GRF_DPHY_RX0_TURNREQUEST,
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GRF_DPHY_RX0_TESTDOUT,
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GRF_DPHY_TX0_TURNDISABLE,
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GRF_DPHY_TX0_FORCERXMODE,
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GRF_DPHY_TX0_FORCETXSTOPMODE,
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GRF_DPHY_TX0_TURNREQUEST,
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GRF_DPHY_TX1RX1_TURNDISABLE,
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GRF_DPHY_TX1RX1_FORCERXMODE,
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GRF_DPHY_TX1RX1_FORCETXSTOPMODE,
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GRF_DPHY_TX1RX1_ENABLE,
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GRF_DPHY_TX1RX1_MASTERSLAVEZ,
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GRF_DPHY_TX1RX1_BASEDIR,
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GRF_DPHY_TX1RX1_ENABLECLK,
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GRF_DPHY_TX1RX1_TURNREQUEST,
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GRF_DPHY_RX1_SRC_SEL,
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/* rk3288 only */
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GRF_CON_DISABLE_ISP,
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GRF_CON_ISP_DPHY_SEL,
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GRF_DSI_CSI_TESTBUS_SEL,
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GRF_DVP_V18SEL,
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/* rk1808 & rk3326 & rv1126 */
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GRF_DPHY_CSI2PHY_FORCERXMODE,
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GRF_DPHY_CSI2PHY_CLKLANE_EN,
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GRF_DPHY_CSI2PHY_DATALANE_EN,
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/* rv1126 only */
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GRF_DPHY_CLK_INV_SEL,
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GRF_DPHY_SEL,
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/* rk3368 only */
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GRF_ISP_MIPI_CSI_HOST_SEL,
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/* below is for rk3399 only */
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GRF_DPHY_RX0_CLK_INV_SEL,
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GRF_DPHY_RX1_CLK_INV_SEL,
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GRF_DPHY_TX1RX1_SRC_SEL,
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/* below is for rk3568 only */
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GRF_DPHY_CSI2PHY_CLKLANE1_EN,
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GRF_DPHY_CLK1_INV_SEL,
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GRF_DPHY_ISP_CSI2PHY_SEL,
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GRF_DPHY_CIF_CSI2PHY_SEL,
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GRF_DPHY_CSI2PHY_LANE_SEL,
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GRF_DPHY_CSI2PHY1_LANE_SEL,
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GRF_DPHY_CSI2PHY_DATALANE_EN0,
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GRF_DPHY_CSI2PHY_DATALANE_EN1,
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GRF_CPHY_MODE,
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GRF_DPHY_CSIHOST2_SEL,
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GRF_DPHY_CSIHOST3_SEL,
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GRF_DPHY_CSIHOST4_SEL,
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GRF_DPHY_CSIHOST5_SEL,
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/* below is for rv1106 only */
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GRF_MIPI_HOST0_SEL,
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GRF_LVDS_HOST0_SEL,
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/* below is for rk3562 */
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GRF_DPHY1_CLK_INV_SEL,
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GRF_DPHY1_CLK1_INV_SEL,
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GRF_DPHY1_CSI2PHY_CLKLANE1_EN,
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GRF_DPHY1_CSI2PHY_FORCERXMODE,
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GRF_DPHY1_CSI2PHY_CLKLANE_EN,
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GRF_DPHY1_CSI2PHY_DATALANE_EN,
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GRF_DPHY1_CSI2PHY_DATALANE_EN0,
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GRF_DPHY1_CSI2PHY_DATALANE_EN1,
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};
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enum csi2dphy_reg_id {
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CSI2PHY_REG_CTRL_LANE_ENABLE = 0,
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CSI2PHY_CTRL_PWRCTL,
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CSI2PHY_CTRL_DIG_RST,
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CSI2PHY_CLK_THS_SETTLE,
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CSI2PHY_LANE0_THS_SETTLE,
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CSI2PHY_LANE1_THS_SETTLE,
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CSI2PHY_LANE2_THS_SETTLE,
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CSI2PHY_LANE3_THS_SETTLE,
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CSI2PHY_CLK_CALIB_ENABLE,
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CSI2PHY_LANE0_CALIB_ENABLE,
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CSI2PHY_LANE1_CALIB_ENABLE,
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CSI2PHY_LANE2_CALIB_ENABLE,
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CSI2PHY_LANE3_CALIB_ENABLE,
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//rv1126 only
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CSI2PHY_MIPI_LVDS_MODEL,
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CSI2PHY_LVDS_MODE,
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//rk3568 only
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CSI2PHY_DUAL_CLK_EN,
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CSI2PHY_CLK1_THS_SETTLE,
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CSI2PHY_CLK1_CALIB_ENABLE,
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//rk3588
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CSI2PHY_CLK_LANE_ENABLE,
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CSI2PHY_CLK1_LANE_ENABLE,
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CSI2PHY_DATA_LANE0_ENABLE,
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CSI2PHY_DATA_LANE1_ENABLE,
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CSI2PHY_DATA_LANE2_ENABLE,
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CSI2PHY_DATA_LANE3_ENABLE,
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CSI2PHY_LANE0_ERR_SOT_SYNC,
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CSI2PHY_LANE1_ERR_SOT_SYNC,
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CSI2PHY_LANE2_ERR_SOT_SYNC,
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CSI2PHY_LANE3_ERR_SOT_SYNC,
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CSI2PHY_S0C_GNR_CON1,
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CSI2PHY_S0C_ANA_CON1,
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CSI2PHY_S0C_ANA_CON2,
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CSI2PHY_S0C_ANA_CON3,
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CSI2PHY_COMBO_S0D0_GNR_CON1,
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CSI2PHY_COMBO_S0D0_ANA_CON1,
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CSI2PHY_COMBO_S0D0_ANA_CON2,
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CSI2PHY_COMBO_S0D0_ANA_CON3,
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CSI2PHY_COMBO_S0D0_ANA_CON6,
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CSI2PHY_COMBO_S0D0_ANA_CON7,
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CSI2PHY_COMBO_S0D0_DESKEW_CON0,
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CSI2PHY_COMBO_S0D0_DESKEW_CON2,
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CSI2PHY_COMBO_S0D0_DESKEW_CON4,
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CSI2PHY_COMBO_S0D0_CRC_CON1,
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CSI2PHY_COMBO_S0D0_CRC_CON2,
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CSI2PHY_COMBO_S0D1_GNR_CON1,
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CSI2PHY_COMBO_S0D1_ANA_CON1,
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CSI2PHY_COMBO_S0D1_ANA_CON2,
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CSI2PHY_COMBO_S0D1_ANA_CON3,
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CSI2PHY_COMBO_S0D1_ANA_CON6,
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CSI2PHY_COMBO_S0D1_ANA_CON7,
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CSI2PHY_COMBO_S0D1_DESKEW_CON0,
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CSI2PHY_COMBO_S0D1_DESKEW_CON2,
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CSI2PHY_COMBO_S0D1_DESKEW_CON4,
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CSI2PHY_COMBO_S0D1_CRC_CON1,
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CSI2PHY_COMBO_S0D1_CRC_CON2,
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CSI2PHY_COMBO_S0D2_GNR_CON1,
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CSI2PHY_COMBO_S0D2_ANA_CON1,
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CSI2PHY_COMBO_S0D2_ANA_CON2,
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CSI2PHY_COMBO_S0D2_ANA_CON3,
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CSI2PHY_COMBO_S0D2_ANA_CON6,
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CSI2PHY_COMBO_S0D2_ANA_CON7,
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CSI2PHY_COMBO_S0D2_DESKEW_CON0,
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CSI2PHY_COMBO_S0D2_DESKEW_CON2,
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CSI2PHY_COMBO_S0D2_DESKEW_CON4,
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CSI2PHY_COMBO_S0D2_CRC_CON1,
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CSI2PHY_COMBO_S0D2_CRC_CON2,
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CSI2PHY_S0D3_GNR_CON1,
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CSI2PHY_S0D3_ANA_CON1,
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CSI2PHY_S0D3_ANA_CON2,
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CSI2PHY_S0D3_ANA_CON3,
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CSI2PHY_S0D3_DESKEW_CON0,
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CSI2PHY_S0D3_DESKEW_CON2,
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CSI2PHY_S0D3_DESKEW_CON4,
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};
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#define HIWORD_UPDATE(val, mask, shift) \
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((val) << (shift) | (mask) << ((shift) + 16))
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#define GRF_REG(_offset, _width, _shift) \
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{ .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
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#define CSI2PHY_REG(_offset) \
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{ .offset = _offset, }
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/* add new chip id in tail by time order */
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enum csi2_dphy_chip_id {
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CHIP_ID_RK3568 = 0x0,
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CHIP_ID_RK3588 = 0x1,
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CHIP_ID_RK3588_DCPHY = 0x2,
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CHIP_ID_RV1106 = 0x3,
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CHIP_ID_RK3562 = 0x4,
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};
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enum csi2_dphy_rx_pads {
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CSI2_DPHY_RX_PAD_SINK = 0,
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CSI2_DPHY_RX_PAD_SOURCE,
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CSI2_DPHY_RX_PADS_NUM,
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};
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enum csi2_dphy_lane_mode {
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LANE_MODE_UNDEF = 0x0,
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LANE_MODE_FULL,
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LANE_MODE_SPLIT,
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};
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struct grf_reg {
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u32 offset;
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u32 mask;
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u32 shift;
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};
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struct csi2dphy_reg {
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u32 offset;
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};
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struct hsfreq_range {
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u32 range_h;
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u16 cfg_bit;
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};
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#define MAX_DPHY_SENSORS (2)
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#define MAX_NUM_CSI2_DPHY (0x2)
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#define RKCSI2_MAX_RESET 8
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#define RKDPHY_MAX_RESET 8
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/* csi2 head */
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struct csi2_dphy_hw {
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struct clk_bulk_data *dphy_clks;
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int num_dphy_clks;
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struct clk_bulk_data *csi2_clks;
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int num_csi2_clks;
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const char * const *csi2_rsts;
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struct reset_control *csi2_rst[RKCSI2_MAX_RESET];
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int num_csi2_rsts;
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const char * const *dphy_rsts;
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struct reset_control *dphy_rst[RKDPHY_MAX_RESET];
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int num_dphy_rsts;
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// struct reset_control *rsts_bulk;
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/* spinlock_t lock; */
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bool on;
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const struct hsfreq_range *hsfreq_ranges;
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int num_hsfreq_ranges;
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const struct grf_reg *grf_regs;
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const struct txrx_reg *txrx_regs;
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const struct csi2dphy_reg *csi2dphy_regs;
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enum csi2_dphy_chip_id chip_id;
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struct device *dev;
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struct regmap *regmap_grf;
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struct regmap *regmap_sys_grf;
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void __iomem *csi2_dphy_base; /*csi2_dphy base addr*/
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void __iomem *csi2_base; /*csi2 base addr*/
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struct mutex mutex; /* lock for updating protection */
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atomic_t stream_cnt;
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struct csi2_err_stats err_list[RK_CSI2_ERR_MAX];
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u64 data_rate_mbps;
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struct rkmodule_csi_dphy_param *dphy_param;
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struct samsung_mipi_dcphy *samsung_phy;
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int phy_index;
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};
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#endif
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