// SPDX-License-Identifier: GPL-2.0-only
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/* ffb.c: Creator/Elite3D frame buffer driver
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*
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* Copyright (C) 2003, 2006 David S. Miller (davem@davemloft.net)
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* Copyright (C) 1997,1998,1999 Jakub Jelinek (jj@ultra.linux.cz)
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*
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* Driver layout based loosely on tgafb.c, see that file for credits.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/fb.h>
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#include <linux/mm.h>
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#include <linux/timer.h>
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#include <linux/of_device.h>
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#include <asm/io.h>
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#include <asm/upa.h>
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#include <asm/fbio.h>
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#include "sbuslib.h"
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/*
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* Local functions.
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*/
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static int ffb_setcolreg(unsigned, unsigned, unsigned, unsigned,
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unsigned, struct fb_info *);
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static int ffb_blank(int, struct fb_info *);
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static void ffb_imageblit(struct fb_info *, const struct fb_image *);
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static void ffb_fillrect(struct fb_info *, const struct fb_fillrect *);
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static void ffb_copyarea(struct fb_info *, const struct fb_copyarea *);
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static int ffb_sync(struct fb_info *);
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static int ffb_mmap(struct fb_info *, struct vm_area_struct *);
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static int ffb_ioctl(struct fb_info *, unsigned int, unsigned long);
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static int ffb_pan_display(struct fb_var_screeninfo *, struct fb_info *);
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/*
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* Frame buffer operations
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*/
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static const struct fb_ops ffb_ops = {
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.owner = THIS_MODULE,
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.fb_setcolreg = ffb_setcolreg,
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.fb_blank = ffb_blank,
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.fb_pan_display = ffb_pan_display,
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.fb_fillrect = ffb_fillrect,
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.fb_copyarea = ffb_copyarea,
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.fb_imageblit = ffb_imageblit,
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.fb_sync = ffb_sync,
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.fb_mmap = ffb_mmap,
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.fb_ioctl = ffb_ioctl,
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#ifdef CONFIG_COMPAT
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.fb_compat_ioctl = sbusfb_compat_ioctl,
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#endif
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};
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/* Register layout and definitions */
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#define FFB_SFB8R_VOFF 0x00000000
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#define FFB_SFB8G_VOFF 0x00400000
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#define FFB_SFB8B_VOFF 0x00800000
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#define FFB_SFB8X_VOFF 0x00c00000
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#define FFB_SFB32_VOFF 0x01000000
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#define FFB_SFB64_VOFF 0x02000000
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#define FFB_FBC_REGS_VOFF 0x04000000
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#define FFB_BM_FBC_REGS_VOFF 0x04002000
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#define FFB_DFB8R_VOFF 0x04004000
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#define FFB_DFB8G_VOFF 0x04404000
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#define FFB_DFB8B_VOFF 0x04804000
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#define FFB_DFB8X_VOFF 0x04c04000
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#define FFB_DFB24_VOFF 0x05004000
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#define FFB_DFB32_VOFF 0x06004000
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#define FFB_DFB422A_VOFF 0x07004000 /* DFB 422 mode write to A */
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#define FFB_DFB422AD_VOFF 0x07804000 /* DFB 422 mode with line doubling */
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#define FFB_DFB24B_VOFF 0x08004000 /* DFB 24bit mode write to B */
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#define FFB_DFB422B_VOFF 0x09004000 /* DFB 422 mode write to B */
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#define FFB_DFB422BD_VOFF 0x09804000 /* DFB 422 mode with line doubling */
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#define FFB_SFB16Z_VOFF 0x0a004000 /* 16bit mode Z planes */
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#define FFB_SFB8Z_VOFF 0x0a404000 /* 8bit mode Z planes */
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#define FFB_SFB422_VOFF 0x0ac04000 /* SFB 422 mode write to A/B */
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#define FFB_SFB422D_VOFF 0x0b404000 /* SFB 422 mode with line doubling */
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#define FFB_FBC_KREGS_VOFF 0x0bc04000
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#define FFB_DAC_VOFF 0x0bc06000
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#define FFB_PROM_VOFF 0x0bc08000
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#define FFB_EXP_VOFF 0x0bc18000
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#define FFB_SFB8R_POFF 0x04000000UL
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#define FFB_SFB8G_POFF 0x04400000UL
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#define FFB_SFB8B_POFF 0x04800000UL
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#define FFB_SFB8X_POFF 0x04c00000UL
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#define FFB_SFB32_POFF 0x05000000UL
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#define FFB_SFB64_POFF 0x06000000UL
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#define FFB_FBC_REGS_POFF 0x00600000UL
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#define FFB_BM_FBC_REGS_POFF 0x00600000UL
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#define FFB_DFB8R_POFF 0x01000000UL
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#define FFB_DFB8G_POFF 0x01400000UL
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#define FFB_DFB8B_POFF 0x01800000UL
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#define FFB_DFB8X_POFF 0x01c00000UL
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#define FFB_DFB24_POFF 0x02000000UL
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#define FFB_DFB32_POFF 0x03000000UL
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#define FFB_FBC_KREGS_POFF 0x00610000UL
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#define FFB_DAC_POFF 0x00400000UL
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#define FFB_PROM_POFF 0x00000000UL
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#define FFB_EXP_POFF 0x00200000UL
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#define FFB_DFB422A_POFF 0x09000000UL
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#define FFB_DFB422AD_POFF 0x09800000UL
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#define FFB_DFB24B_POFF 0x0a000000UL
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#define FFB_DFB422B_POFF 0x0b000000UL
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#define FFB_DFB422BD_POFF 0x0b800000UL
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#define FFB_SFB16Z_POFF 0x0c800000UL
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#define FFB_SFB8Z_POFF 0x0c000000UL
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#define FFB_SFB422_POFF 0x0d000000UL
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#define FFB_SFB422D_POFF 0x0d800000UL
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/* Draw operations */
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#define FFB_DRAWOP_DOT 0x00
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#define FFB_DRAWOP_AADOT 0x01
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#define FFB_DRAWOP_BRLINECAP 0x02
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#define FFB_DRAWOP_BRLINEOPEN 0x03
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#define FFB_DRAWOP_DDLINE 0x04
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#define FFB_DRAWOP_AALINE 0x05
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#define FFB_DRAWOP_TRIANGLE 0x06
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#define FFB_DRAWOP_POLYGON 0x07
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#define FFB_DRAWOP_RECTANGLE 0x08
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#define FFB_DRAWOP_FASTFILL 0x09
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#define FFB_DRAWOP_BCOPY 0x0a
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#define FFB_DRAWOP_VSCROLL 0x0b
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/* Pixel processor control */
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/* Force WID */
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#define FFB_PPC_FW_DISABLE 0x800000
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#define FFB_PPC_FW_ENABLE 0xc00000
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/* Auxiliary clip */
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#define FFB_PPC_ACE_DISABLE 0x040000
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#define FFB_PPC_ACE_AUX_SUB 0x080000
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#define FFB_PPC_ACE_AUX_ADD 0x0c0000
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/* Depth cue */
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#define FFB_PPC_DCE_DISABLE 0x020000
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#define FFB_PPC_DCE_ENABLE 0x030000
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/* Alpha blend */
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#define FFB_PPC_ABE_DISABLE 0x008000
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#define FFB_PPC_ABE_ENABLE 0x00c000
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/* View clip */
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#define FFB_PPC_VCE_DISABLE 0x001000
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#define FFB_PPC_VCE_2D 0x002000
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#define FFB_PPC_VCE_3D 0x003000
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/* Area pattern */
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#define FFB_PPC_APE_DISABLE 0x000800
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#define FFB_PPC_APE_ENABLE 0x000c00
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/* Transparent background */
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#define FFB_PPC_TBE_OPAQUE 0x000200
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#define FFB_PPC_TBE_TRANSPARENT 0x000300
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/* Z source */
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#define FFB_PPC_ZS_VAR 0x000080
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#define FFB_PPC_ZS_CONST 0x0000c0
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/* Y source */
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#define FFB_PPC_YS_VAR 0x000020
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#define FFB_PPC_YS_CONST 0x000030
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/* X source */
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#define FFB_PPC_XS_WID 0x000004
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#define FFB_PPC_XS_VAR 0x000008
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#define FFB_PPC_XS_CONST 0x00000c
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/* Color (BGR) source */
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#define FFB_PPC_CS_VAR 0x000002
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#define FFB_PPC_CS_CONST 0x000003
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#define FFB_ROP_NEW 0x83
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#define FFB_ROP_OLD 0x85
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#define FFB_ROP_NEW_XOR_OLD 0x86
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#define FFB_UCSR_FIFO_MASK 0x00000fff
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#define FFB_UCSR_FB_BUSY 0x01000000
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#define FFB_UCSR_RP_BUSY 0x02000000
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#define FFB_UCSR_ALL_BUSY (FFB_UCSR_RP_BUSY|FFB_UCSR_FB_BUSY)
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#define FFB_UCSR_READ_ERR 0x40000000
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#define FFB_UCSR_FIFO_OVFL 0x80000000
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#define FFB_UCSR_ALL_ERRORS (FFB_UCSR_READ_ERR|FFB_UCSR_FIFO_OVFL)
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struct ffb_fbc {
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/* Next vertex registers */
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u32 xxx1[3];
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u32 alpha;
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u32 red;
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u32 green;
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u32 blue;
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u32 depth;
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u32 y;
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u32 x;
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u32 xxx2[2];
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u32 ryf;
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u32 rxf;
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u32 xxx3[2];
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u32 dmyf;
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u32 dmxf;
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u32 xxx4[2];
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u32 ebyi;
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u32 ebxi;
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u32 xxx5[2];
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u32 by;
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u32 bx;
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u32 dy;
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u32 dx;
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u32 bh;
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u32 bw;
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u32 xxx6[2];
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u32 xxx7[32];
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/* Setup unit vertex state register */
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u32 suvtx;
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u32 xxx8[63];
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/* Control registers */
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u32 ppc;
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u32 wid;
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u32 fg;
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u32 bg;
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u32 consty;
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u32 constz;
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u32 xclip;
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u32 dcss;
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u32 vclipmin;
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u32 vclipmax;
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u32 vclipzmin;
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u32 vclipzmax;
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u32 dcsf;
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u32 dcsb;
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u32 dczf;
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u32 dczb;
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u32 xxx9;
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u32 blendc;
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u32 blendc1;
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u32 blendc2;
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u32 fbramitc;
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u32 fbc;
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u32 rop;
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u32 cmp;
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u32 matchab;
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u32 matchc;
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u32 magnab;
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u32 magnc;
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u32 fbcfg0;
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u32 fbcfg1;
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u32 fbcfg2;
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u32 fbcfg3;
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u32 ppcfg;
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u32 pick;
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u32 fillmode;
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u32 fbramwac;
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u32 pmask;
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u32 xpmask;
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u32 ypmask;
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u32 zpmask;
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u32 clip0min;
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u32 clip0max;
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u32 clip1min;
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u32 clip1max;
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u32 clip2min;
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u32 clip2max;
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u32 clip3min;
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u32 clip3max;
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/* New 3dRAM III support regs */
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u32 rawblend2;
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u32 rawpreblend;
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u32 rawstencil;
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u32 rawstencilctl;
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u32 threedram1;
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u32 threedram2;
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u32 passin;
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u32 rawclrdepth;
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u32 rawpmask;
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u32 rawcsrc;
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u32 rawmatch;
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u32 rawmagn;
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u32 rawropblend;
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u32 rawcmp;
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u32 rawwac;
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u32 fbramid;
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u32 drawop;
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u32 xxx10[2];
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u32 fontlpat;
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u32 xxx11;
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u32 fontxy;
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u32 fontw;
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u32 fontinc;
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u32 font;
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u32 xxx12[3];
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u32 blend2;
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u32 preblend;
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u32 stencil;
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u32 stencilctl;
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u32 xxx13[4];
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u32 dcss1;
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u32 dcss2;
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u32 dcss3;
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u32 widpmask;
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u32 dcs2;
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u32 dcs3;
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u32 dcs4;
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u32 xxx14;
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u32 dcd2;
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u32 dcd3;
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u32 dcd4;
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u32 xxx15;
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u32 pattern[32];
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u32 xxx16[256];
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u32 devid;
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u32 xxx17[63];
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u32 ucsr;
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u32 xxx18[31];
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u32 mer;
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};
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struct ffb_dac {
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u32 type;
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u32 value;
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u32 type2;
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u32 value2;
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};
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#define FFB_DAC_UCTRL 0x1001 /* User Control */
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#define FFB_DAC_UCTRL_MANREV 0x00000f00 /* 4-bit Manufacturing Revision */
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#define FFB_DAC_UCTRL_MANREV_SHIFT 8
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#define FFB_DAC_TGEN 0x6000 /* Timing Generator */
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#define FFB_DAC_TGEN_VIDE 0x00000001 /* Video Enable */
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#define FFB_DAC_DID 0x8000 /* Device Identification */
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#define FFB_DAC_DID_PNUM 0x0ffff000 /* Device Part Number */
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#define FFB_DAC_DID_PNUM_SHIFT 12
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#define FFB_DAC_DID_REV 0xf0000000 /* Device Revision */
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#define FFB_DAC_DID_REV_SHIFT 28
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#define FFB_DAC_CUR_CTRL 0x100
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#define FFB_DAC_CUR_CTRL_P0 0x00000001
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#define FFB_DAC_CUR_CTRL_P1 0x00000002
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struct ffb_par {
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spinlock_t lock;
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struct ffb_fbc __iomem *fbc;
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struct ffb_dac __iomem *dac;
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u32 flags;
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#define FFB_FLAG_AFB 0x00000001 /* AFB m3 or m6 */
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#define FFB_FLAG_BLANKED 0x00000002 /* screen is blanked */
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#define FFB_FLAG_INVCURSOR 0x00000004 /* DAC has inverted cursor logic */
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u32 fg_cache __attribute__((aligned (8)));
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u32 bg_cache;
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u32 rop_cache;
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int fifo_cache;
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unsigned long physbase;
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unsigned long fbsize;
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int board_type;
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u32 pseudo_palette[16];
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};
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static void FFBFifo(struct ffb_par *par, int n)
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{
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struct ffb_fbc __iomem *fbc;
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int cache = par->fifo_cache;
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if (cache - n < 0) {
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fbc = par->fbc;
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do {
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cache = (upa_readl(&fbc->ucsr) & FFB_UCSR_FIFO_MASK);
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cache -= 8;
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} while (cache - n < 0);
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}
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par->fifo_cache = cache - n;
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}
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static void FFBWait(struct ffb_par *par)
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{
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struct ffb_fbc __iomem *fbc;
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int limit = 10000;
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fbc = par->fbc;
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do {
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if ((upa_readl(&fbc->ucsr) & FFB_UCSR_ALL_BUSY) == 0)
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break;
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if ((upa_readl(&fbc->ucsr) & FFB_UCSR_ALL_ERRORS) != 0) {
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upa_writel(FFB_UCSR_ALL_ERRORS, &fbc->ucsr);
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}
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udelay(10);
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} while (--limit > 0);
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}
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static int ffb_sync(struct fb_info *p)
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{
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struct ffb_par *par = (struct ffb_par *)p->par;
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FFBWait(par);
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return 0;
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}
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static __inline__ void ffb_rop(struct ffb_par *par, u32 rop)
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{
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if (par->rop_cache != rop) {
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FFBFifo(par, 1);
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upa_writel(rop, &par->fbc->rop);
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par->rop_cache = rop;
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}
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}
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static void ffb_switch_from_graph(struct ffb_par *par)
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{
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struct ffb_fbc __iomem *fbc = par->fbc;
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struct ffb_dac __iomem *dac = par->dac;
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unsigned long flags;
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spin_lock_irqsave(&par->lock, flags);
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FFBWait(par);
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par->fifo_cache = 0;
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FFBFifo(par, 7);
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upa_writel(FFB_PPC_VCE_DISABLE | FFB_PPC_TBE_OPAQUE |
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FFB_PPC_APE_DISABLE | FFB_PPC_CS_CONST,
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&fbc->ppc);
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upa_writel(0x2000707f, &fbc->fbc);
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upa_writel(par->rop_cache, &fbc->rop);
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upa_writel(0xffffffff, &fbc->pmask);
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upa_writel((1 << 16) | (0 << 0), &fbc->fontinc);
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upa_writel(par->fg_cache, &fbc->fg);
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upa_writel(par->bg_cache, &fbc->bg);
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FFBWait(par);
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/* Disable cursor. */
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upa_writel(FFB_DAC_CUR_CTRL, &dac->type2);
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if (par->flags & FFB_FLAG_INVCURSOR)
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upa_writel(0, &dac->value2);
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else
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upa_writel((FFB_DAC_CUR_CTRL_P0 |
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FFB_DAC_CUR_CTRL_P1), &dac->value2);
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spin_unlock_irqrestore(&par->lock, flags);
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}
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static int ffb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
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{
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struct ffb_par *par = (struct ffb_par *)info->par;
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/* We just use this to catch switches out of
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* graphics mode.
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*/
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ffb_switch_from_graph(par);
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if (var->xoffset || var->yoffset || var->vmode)
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return -EINVAL;
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return 0;
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}
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/**
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* ffb_fillrect - Draws a rectangle on the screen.
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*
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* @info: frame buffer structure that represents a single frame buffer
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* @rect: structure defining the rectagle and operation.
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*/
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static void ffb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
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{
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struct ffb_par *par = (struct ffb_par *)info->par;
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struct ffb_fbc __iomem *fbc = par->fbc;
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unsigned long flags;
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u32 fg;
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BUG_ON(rect->rop != ROP_COPY && rect->rop != ROP_XOR);
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fg = ((u32 *)info->pseudo_palette)[rect->color];
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spin_lock_irqsave(&par->lock, flags);
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if (fg != par->fg_cache) {
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FFBFifo(par, 1);
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upa_writel(fg, &fbc->fg);
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par->fg_cache = fg;
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}
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ffb_rop(par, rect->rop == ROP_COPY ?
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FFB_ROP_NEW :
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FFB_ROP_NEW_XOR_OLD);
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FFBFifo(par, 5);
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upa_writel(FFB_DRAWOP_RECTANGLE, &fbc->drawop);
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upa_writel(rect->dy, &fbc->by);
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upa_writel(rect->dx, &fbc->bx);
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upa_writel(rect->height, &fbc->bh);
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upa_writel(rect->width, &fbc->bw);
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spin_unlock_irqrestore(&par->lock, flags);
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}
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/**
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* ffb_copyarea - Copies on area of the screen to another area.
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*
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* @info: frame buffer structure that represents a single frame buffer
|
* @area: structure defining the source and destination.
|
*/
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static void ffb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
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{
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struct ffb_par *par = (struct ffb_par *)info->par;
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struct ffb_fbc __iomem *fbc = par->fbc;
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unsigned long flags;
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if (area->dx != area->sx ||
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area->dy == area->sy) {
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cfb_copyarea(info, area);
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return;
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}
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spin_lock_irqsave(&par->lock, flags);
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ffb_rop(par, FFB_ROP_OLD);
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FFBFifo(par, 7);
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upa_writel(FFB_DRAWOP_VSCROLL, &fbc->drawop);
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upa_writel(area->sy, &fbc->by);
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upa_writel(area->sx, &fbc->bx);
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upa_writel(area->dy, &fbc->dy);
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upa_writel(area->dx, &fbc->dx);
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upa_writel(area->height, &fbc->bh);
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upa_writel(area->width, &fbc->bw);
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spin_unlock_irqrestore(&par->lock, flags);
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}
|
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/**
|
* ffb_imageblit - Copies a image from system memory to the screen.
|
*
|
* @info: frame buffer structure that represents a single frame buffer
|
* @image: structure defining the image.
|
*/
|
static void ffb_imageblit(struct fb_info *info, const struct fb_image *image)
|
{
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struct ffb_par *par = (struct ffb_par *)info->par;
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struct ffb_fbc __iomem *fbc = par->fbc;
|
const u8 *data = image->data;
|
unsigned long flags;
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u32 fg, bg, xy;
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u64 fgbg;
|
int i, width, stride;
|
|
if (image->depth > 1) {
|
cfb_imageblit(info, image);
|
return;
|
}
|
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fg = ((u32 *)info->pseudo_palette)[image->fg_color];
|
bg = ((u32 *)info->pseudo_palette)[image->bg_color];
|
fgbg = ((u64) fg << 32) | (u64) bg;
|
xy = (image->dy << 16) | image->dx;
|
width = image->width;
|
stride = ((width + 7) >> 3);
|
|
spin_lock_irqsave(&par->lock, flags);
|
|
if (fgbg != *(u64 *)&par->fg_cache) {
|
FFBFifo(par, 2);
|
upa_writeq(fgbg, &fbc->fg);
|
*(u64 *)&par->fg_cache = fgbg;
|
}
|
|
if (width >= 32) {
|
FFBFifo(par, 1);
|
upa_writel(32, &fbc->fontw);
|
}
|
|
while (width >= 32) {
|
const u8 *next_data = data + 4;
|
|
FFBFifo(par, 1);
|
upa_writel(xy, &fbc->fontxy);
|
xy += (32 << 0);
|
|
for (i = 0; i < image->height; i++) {
|
u32 val = (((u32)data[0] << 24) |
|
((u32)data[1] << 16) |
|
((u32)data[2] << 8) |
|
((u32)data[3] << 0));
|
FFBFifo(par, 1);
|
upa_writel(val, &fbc->font);
|
|
data += stride;
|
}
|
|
data = next_data;
|
width -= 32;
|
}
|
|
if (width) {
|
FFBFifo(par, 2);
|
upa_writel(width, &fbc->fontw);
|
upa_writel(xy, &fbc->fontxy);
|
|
for (i = 0; i < image->height; i++) {
|
u32 val = (((u32)data[0] << 24) |
|
((u32)data[1] << 16) |
|
((u32)data[2] << 8) |
|
((u32)data[3] << 0));
|
FFBFifo(par, 1);
|
upa_writel(val, &fbc->font);
|
|
data += stride;
|
}
|
}
|
|
spin_unlock_irqrestore(&par->lock, flags);
|
}
|
|
static void ffb_fixup_var_rgb(struct fb_var_screeninfo *var)
|
{
|
var->red.offset = 0;
|
var->red.length = 8;
|
var->green.offset = 8;
|
var->green.length = 8;
|
var->blue.offset = 16;
|
var->blue.length = 8;
|
var->transp.offset = 0;
|
var->transp.length = 0;
|
}
|
|
/**
|
* ffb_setcolreg - Sets a color register.
|
*
|
* @regno: boolean, 0 copy local, 1 get_user() function
|
* @red: frame buffer colormap structure
|
* @green: The green value which can be up to 16 bits wide
|
* @blue: The blue value which can be up to 16 bits wide.
|
* @transp: If supported the alpha value which can be up to 16 bits wide.
|
* @info: frame buffer info structure
|
*/
|
static int ffb_setcolreg(unsigned regno,
|
unsigned red, unsigned green, unsigned blue,
|
unsigned transp, struct fb_info *info)
|
{
|
u32 value;
|
|
if (regno >= 16)
|
return 1;
|
|
red >>= 8;
|
green >>= 8;
|
blue >>= 8;
|
|
value = (blue << 16) | (green << 8) | red;
|
((u32 *)info->pseudo_palette)[regno] = value;
|
|
return 0;
|
}
|
|
/**
|
* ffb_blank - Optional function. Blanks the display.
|
* @blank_mode: the blank mode we want.
|
* @info: frame buffer structure that represents a single frame buffer
|
*/
|
static int ffb_blank(int blank, struct fb_info *info)
|
{
|
struct ffb_par *par = (struct ffb_par *)info->par;
|
struct ffb_dac __iomem *dac = par->dac;
|
unsigned long flags;
|
u32 val;
|
int i;
|
|
spin_lock_irqsave(&par->lock, flags);
|
|
FFBWait(par);
|
|
upa_writel(FFB_DAC_TGEN, &dac->type);
|
val = upa_readl(&dac->value);
|
switch (blank) {
|
case FB_BLANK_UNBLANK: /* Unblanking */
|
val |= FFB_DAC_TGEN_VIDE;
|
par->flags &= ~FFB_FLAG_BLANKED;
|
break;
|
|
case FB_BLANK_NORMAL: /* Normal blanking */
|
case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
|
case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
|
case FB_BLANK_POWERDOWN: /* Poweroff */
|
val &= ~FFB_DAC_TGEN_VIDE;
|
par->flags |= FFB_FLAG_BLANKED;
|
break;
|
}
|
upa_writel(FFB_DAC_TGEN, &dac->type);
|
upa_writel(val, &dac->value);
|
for (i = 0; i < 10; i++) {
|
upa_writel(FFB_DAC_TGEN, &dac->type);
|
upa_readl(&dac->value);
|
}
|
|
spin_unlock_irqrestore(&par->lock, flags);
|
|
return 0;
|
}
|
|
static struct sbus_mmap_map ffb_mmap_map[] = {
|
{
|
.voff = FFB_SFB8R_VOFF,
|
.poff = FFB_SFB8R_POFF,
|
.size = 0x0400000
|
},
|
{
|
.voff = FFB_SFB8G_VOFF,
|
.poff = FFB_SFB8G_POFF,
|
.size = 0x0400000
|
},
|
{
|
.voff = FFB_SFB8B_VOFF,
|
.poff = FFB_SFB8B_POFF,
|
.size = 0x0400000
|
},
|
{
|
.voff = FFB_SFB8X_VOFF,
|
.poff = FFB_SFB8X_POFF,
|
.size = 0x0400000
|
},
|
{
|
.voff = FFB_SFB32_VOFF,
|
.poff = FFB_SFB32_POFF,
|
.size = 0x1000000
|
},
|
{
|
.voff = FFB_SFB64_VOFF,
|
.poff = FFB_SFB64_POFF,
|
.size = 0x2000000
|
},
|
{
|
.voff = FFB_FBC_REGS_VOFF,
|
.poff = FFB_FBC_REGS_POFF,
|
.size = 0x0002000
|
},
|
{
|
.voff = FFB_BM_FBC_REGS_VOFF,
|
.poff = FFB_BM_FBC_REGS_POFF,
|
.size = 0x0002000
|
},
|
{
|
.voff = FFB_DFB8R_VOFF,
|
.poff = FFB_DFB8R_POFF,
|
.size = 0x0400000
|
},
|
{
|
.voff = FFB_DFB8G_VOFF,
|
.poff = FFB_DFB8G_POFF,
|
.size = 0x0400000
|
},
|
{
|
.voff = FFB_DFB8B_VOFF,
|
.poff = FFB_DFB8B_POFF,
|
.size = 0x0400000
|
},
|
{
|
.voff = FFB_DFB8X_VOFF,
|
.poff = FFB_DFB8X_POFF,
|
.size = 0x0400000
|
},
|
{
|
.voff = FFB_DFB24_VOFF,
|
.poff = FFB_DFB24_POFF,
|
.size = 0x1000000
|
},
|
{
|
.voff = FFB_DFB32_VOFF,
|
.poff = FFB_DFB32_POFF,
|
.size = 0x1000000
|
},
|
{
|
.voff = FFB_FBC_KREGS_VOFF,
|
.poff = FFB_FBC_KREGS_POFF,
|
.size = 0x0002000
|
},
|
{
|
.voff = FFB_DAC_VOFF,
|
.poff = FFB_DAC_POFF,
|
.size = 0x0002000
|
},
|
{
|
.voff = FFB_PROM_VOFF,
|
.poff = FFB_PROM_POFF,
|
.size = 0x0010000
|
},
|
{
|
.voff = FFB_EXP_VOFF,
|
.poff = FFB_EXP_POFF,
|
.size = 0x0002000
|
},
|
{
|
.voff = FFB_DFB422A_VOFF,
|
.poff = FFB_DFB422A_POFF,
|
.size = 0x0800000
|
},
|
{
|
.voff = FFB_DFB422AD_VOFF,
|
.poff = FFB_DFB422AD_POFF,
|
.size = 0x0800000
|
},
|
{
|
.voff = FFB_DFB24B_VOFF,
|
.poff = FFB_DFB24B_POFF,
|
.size = 0x1000000
|
},
|
{
|
.voff = FFB_DFB422B_VOFF,
|
.poff = FFB_DFB422B_POFF,
|
.size = 0x0800000
|
},
|
{
|
.voff = FFB_DFB422BD_VOFF,
|
.poff = FFB_DFB422BD_POFF,
|
.size = 0x0800000
|
},
|
{
|
.voff = FFB_SFB16Z_VOFF,
|
.poff = FFB_SFB16Z_POFF,
|
.size = 0x0800000
|
},
|
{
|
.voff = FFB_SFB8Z_VOFF,
|
.poff = FFB_SFB8Z_POFF,
|
.size = 0x0800000
|
},
|
{
|
.voff = FFB_SFB422_VOFF,
|
.poff = FFB_SFB422_POFF,
|
.size = 0x0800000
|
},
|
{
|
.voff = FFB_SFB422D_VOFF,
|
.poff = FFB_SFB422D_POFF,
|
.size = 0x0800000
|
},
|
{ .size = 0 }
|
};
|
|
static int ffb_mmap(struct fb_info *info, struct vm_area_struct *vma)
|
{
|
struct ffb_par *par = (struct ffb_par *)info->par;
|
|
return sbusfb_mmap_helper(ffb_mmap_map,
|
par->physbase, par->fbsize,
|
0, vma);
|
}
|
|
static int ffb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
|
{
|
struct ffb_par *par = (struct ffb_par *)info->par;
|
|
return sbusfb_ioctl_helper(cmd, arg, info,
|
FBTYPE_CREATOR, 24, par->fbsize);
|
}
|
|
/*
|
* Initialisation
|
*/
|
|
static void ffb_init_fix(struct fb_info *info)
|
{
|
struct ffb_par *par = (struct ffb_par *)info->par;
|
const char *ffb_type_name;
|
|
if (!(par->flags & FFB_FLAG_AFB)) {
|
if ((par->board_type & 0x7) == 0x3)
|
ffb_type_name = "Creator 3D";
|
else
|
ffb_type_name = "Creator";
|
} else
|
ffb_type_name = "Elite 3D";
|
|
strlcpy(info->fix.id, ffb_type_name, sizeof(info->fix.id));
|
|
info->fix.type = FB_TYPE_PACKED_PIXELS;
|
info->fix.visual = FB_VISUAL_TRUECOLOR;
|
|
/* Framebuffer length is the same regardless of resolution. */
|
info->fix.line_length = 8192;
|
|
info->fix.accel = FB_ACCEL_SUN_CREATOR;
|
}
|
|
static int ffb_probe(struct platform_device *op)
|
{
|
struct device_node *dp = op->dev.of_node;
|
struct ffb_fbc __iomem *fbc;
|
struct ffb_dac __iomem *dac;
|
struct fb_info *info;
|
struct ffb_par *par;
|
u32 dac_pnum, dac_rev, dac_mrev;
|
int err;
|
|
info = framebuffer_alloc(sizeof(struct ffb_par), &op->dev);
|
|
err = -ENOMEM;
|
if (!info)
|
goto out_err;
|
|
par = info->par;
|
|
spin_lock_init(&par->lock);
|
par->fbc = of_ioremap(&op->resource[2], 0,
|
sizeof(struct ffb_fbc), "ffb fbc");
|
if (!par->fbc)
|
goto out_release_fb;
|
|
par->dac = of_ioremap(&op->resource[1], 0,
|
sizeof(struct ffb_dac), "ffb dac");
|
if (!par->dac)
|
goto out_unmap_fbc;
|
|
par->rop_cache = FFB_ROP_NEW;
|
par->physbase = op->resource[0].start;
|
|
/* Don't mention copyarea, so SCROLL_REDRAW is always
|
* used. It is the fastest on this chip.
|
*/
|
info->flags = (FBINFO_DEFAULT |
|
/* FBINFO_HWACCEL_COPYAREA | */
|
FBINFO_HWACCEL_FILLRECT |
|
FBINFO_HWACCEL_IMAGEBLIT);
|
|
info->fbops = &ffb_ops;
|
|
info->screen_base = (char *) par->physbase + FFB_DFB24_POFF;
|
info->pseudo_palette = par->pseudo_palette;
|
|
sbusfb_fill_var(&info->var, dp, 32);
|
par->fbsize = PAGE_ALIGN(info->var.xres * info->var.yres * 4);
|
ffb_fixup_var_rgb(&info->var);
|
|
info->var.accel_flags = FB_ACCELF_TEXT;
|
|
if (of_node_name_eq(dp, "SUNW,afb"))
|
par->flags |= FFB_FLAG_AFB;
|
|
par->board_type = of_getintprop_default(dp, "board_type", 0);
|
|
fbc = par->fbc;
|
if ((upa_readl(&fbc->ucsr) & FFB_UCSR_ALL_ERRORS) != 0)
|
upa_writel(FFB_UCSR_ALL_ERRORS, &fbc->ucsr);
|
|
dac = par->dac;
|
upa_writel(FFB_DAC_DID, &dac->type);
|
dac_pnum = upa_readl(&dac->value);
|
dac_rev = (dac_pnum & FFB_DAC_DID_REV) >> FFB_DAC_DID_REV_SHIFT;
|
dac_pnum = (dac_pnum & FFB_DAC_DID_PNUM) >> FFB_DAC_DID_PNUM_SHIFT;
|
|
upa_writel(FFB_DAC_UCTRL, &dac->type);
|
dac_mrev = upa_readl(&dac->value);
|
dac_mrev = (dac_mrev & FFB_DAC_UCTRL_MANREV) >>
|
FFB_DAC_UCTRL_MANREV_SHIFT;
|
|
/* Elite3D has different DAC revision numbering, and no DAC revisions
|
* have the reversed meaning of cursor enable. Otherwise, Pacifica 1
|
* ramdacs with manufacturing revision less than 3 have inverted
|
* cursor logic. We identify Pacifica 1 as not Pacifica 2, the
|
* latter having a part number value of 0x236e.
|
*/
|
if ((par->flags & FFB_FLAG_AFB) || dac_pnum == 0x236e) {
|
par->flags &= ~FFB_FLAG_INVCURSOR;
|
} else {
|
if (dac_mrev < 3)
|
par->flags |= FFB_FLAG_INVCURSOR;
|
}
|
|
ffb_switch_from_graph(par);
|
|
/* Unblank it just to be sure. When there are multiple
|
* FFB/AFB cards in the system, or it is not the OBP
|
* chosen console, it will have video outputs off in
|
* the DAC.
|
*/
|
ffb_blank(FB_BLANK_UNBLANK, info);
|
|
if (fb_alloc_cmap(&info->cmap, 256, 0))
|
goto out_unmap_dac;
|
|
ffb_init_fix(info);
|
|
err = register_framebuffer(info);
|
if (err < 0)
|
goto out_dealloc_cmap;
|
|
dev_set_drvdata(&op->dev, info);
|
|
printk(KERN_INFO "%pOF: %s at %016lx, type %d, "
|
"DAC pnum[%x] rev[%d] manuf_rev[%d]\n",
|
dp,
|
((par->flags & FFB_FLAG_AFB) ? "AFB" : "FFB"),
|
par->physbase, par->board_type,
|
dac_pnum, dac_rev, dac_mrev);
|
|
return 0;
|
|
out_dealloc_cmap:
|
fb_dealloc_cmap(&info->cmap);
|
|
out_unmap_dac:
|
of_iounmap(&op->resource[1], par->dac, sizeof(struct ffb_dac));
|
|
out_unmap_fbc:
|
of_iounmap(&op->resource[2], par->fbc, sizeof(struct ffb_fbc));
|
|
out_release_fb:
|
framebuffer_release(info);
|
|
out_err:
|
return err;
|
}
|
|
static int ffb_remove(struct platform_device *op)
|
{
|
struct fb_info *info = dev_get_drvdata(&op->dev);
|
struct ffb_par *par = info->par;
|
|
unregister_framebuffer(info);
|
fb_dealloc_cmap(&info->cmap);
|
|
of_iounmap(&op->resource[2], par->fbc, sizeof(struct ffb_fbc));
|
of_iounmap(&op->resource[1], par->dac, sizeof(struct ffb_dac));
|
|
framebuffer_release(info);
|
|
return 0;
|
}
|
|
static const struct of_device_id ffb_match[] = {
|
{
|
.name = "SUNW,ffb",
|
},
|
{
|
.name = "SUNW,afb",
|
},
|
{},
|
};
|
MODULE_DEVICE_TABLE(of, ffb_match);
|
|
static struct platform_driver ffb_driver = {
|
.driver = {
|
.name = "ffb",
|
.of_match_table = ffb_match,
|
},
|
.probe = ffb_probe,
|
.remove = ffb_remove,
|
};
|
|
static int __init ffb_init(void)
|
{
|
if (fb_get_options("ffb", NULL))
|
return -ENODEV;
|
|
return platform_driver_register(&ffb_driver);
|
}
|
|
static void __exit ffb_exit(void)
|
{
|
platform_driver_unregister(&ffb_driver);
|
}
|
|
module_init(ffb_init);
|
module_exit(ffb_exit);
|
|
MODULE_DESCRIPTION("framebuffer driver for Creator/Elite3D chipsets");
|
MODULE_AUTHOR("David S. Miller <davem@davemloft.net>");
|
MODULE_VERSION("2.0");
|
MODULE_LICENSE("GPL");
|
