/* SPDX-License-Identifier: GPL-2.0+ */
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/* Copyright (C) 2005-2010,2012 Freescale Semiconductor, Inc.
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* Copyright (c) 2005 MontaVista Software
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*/
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#ifndef _EHCI_FSL_H
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#define _EHCI_FSL_H
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/* offsets for the non-ehci registers in the FSL SOC USB controller */
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#define FSL_SOC_USB_SBUSCFG 0x90
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#define SBUSCFG_INCR8 0x02 /* INCR8, specified */
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#define FSL_SOC_USB_ULPIVP 0x170
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#define FSL_SOC_USB_PORTSC1 0x184
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#define PORT_PTS_MSK (3<<30)
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#define PORT_PTS_UTMI (0<<30)
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#define PORT_PTS_ULPI (2<<30)
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#define PORT_PTS_SERIAL (3<<30)
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#define PORT_PTS_PTW (1<<28)
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#define FSL_SOC_USB_PORTSC2 0x188
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#define FSL_SOC_USB_USBMODE 0x1a8
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#define USBMODE_CM_MASK (3 << 0) /* controller mode mask */
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#define USBMODE_CM_HOST (3 << 0) /* controller mode: host */
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#define USBMODE_ES (1 << 2) /* (Big) Endian Select */
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#define FSL_SOC_USB_USBGENCTRL 0x200
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#define USBGENCTRL_PPP (1 << 3)
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#define USBGENCTRL_PFP (1 << 2)
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#define FSL_SOC_USB_ISIPHYCTRL 0x204
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#define ISIPHYCTRL_PXE (1)
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#define ISIPHYCTRL_PHYE (1 << 4)
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#define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */
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#define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */
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#define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */
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#define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */
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#define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */
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#define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */
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#define CTRL_UTMI_PHY_EN (1<<9)
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#define CTRL_PHY_CLK_VALID (1 << 17)
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#define SNOOP_SIZE_2GB 0x1e
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/* control Register Bit Masks */
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#define CONTROL_REGISTER_W1C_MASK 0x00020000 /* W1C: PHY_CLK_VALID */
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#define ULPI_INT_EN (1<<0)
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#define WU_INT_EN (1<<1)
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#define USB_CTRL_USB_EN (1<<2)
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#define LINE_STATE_FILTER__EN (1<<3)
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#define KEEP_OTG_ON (1<<4)
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#define OTG_PORT (1<<5)
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#define PLL_RESET (1<<8)
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#define UTMI_PHY_EN (1<<9)
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#define ULPI_PHY_CLK_SEL (1<<10)
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#define PHY_CLK_VALID (1<<17)
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/* Retry count for checking UTMI PHY CLK validity */
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#define UTMI_PHY_CLK_VALID_CHK_RETRY 5
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#endif /* _EHCI_FSL_H */
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