// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Rockchip SPI Slave Controller Driver
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*
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* Copyright (c) 2023, Rockchip Inc.
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* Author: Jon Lin <Jon.lin@rock-chips.com>
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*/
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#include <linux/acpi.h>
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#include <linux/clk.h>
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#include <linux/dmaengine.h>
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#include <linux/gpio.h>
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#include <linux/interrupt.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <linux/pm_runtime.h>
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#include <linux/dma-mapping.h>
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#define DRIVER_NAME "rockchip-spi-slave"
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/* SPI register offsets */
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#define ROCKCHIP_SPI_CTRLR0 0x0000
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#define ROCKCHIP_SPI_CTRLR1 0x0004
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#define ROCKCHIP_SPI_SSIENR 0x0008
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#define ROCKCHIP_SPI_SER 0x000c
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#define ROCKCHIP_SPI_BAUDR 0x0010
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#define ROCKCHIP_SPI_TXFTLR 0x0014
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#define ROCKCHIP_SPI_RXFTLR 0x0018
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#define ROCKCHIP_SPI_TXFLR 0x001c
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#define ROCKCHIP_SPI_RXFLR 0x0020
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#define ROCKCHIP_SPI_SR 0x0024
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#define ROCKCHIP_SPI_IPR 0x0028
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#define ROCKCHIP_SPI_IMR 0x002c
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#define ROCKCHIP_SPI_ISR 0x0030
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#define ROCKCHIP_SPI_RISR 0x0034
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#define ROCKCHIP_SPI_ICR 0x0038
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#define ROCKCHIP_SPI_DMACR 0x003c
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#define ROCKCHIP_SPI_DMATDLR 0x0040
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#define ROCKCHIP_SPI_DMARDLR 0x0044
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#define ROCKCHIP_SPI_VERSION 0x0048
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#define ROCKCHIP_SPI_TIMEOUT 0x004c
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#define ROCKCHIP_SPI_BYPASS 0x0050
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#define ROCKCHIP_SPI_BYPASS_ENR 0x0054
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#define ROCKCHIP_SPI_TXDR 0x0400
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#define ROCKCHIP_SPI_RXDR 0x0800
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/* Bit fields in CTRLR0 */
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#define CR0_DFS_OFFSET 0
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#define CR0_DFS_4BIT 0x0
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#define CR0_DFS_8BIT 0x1
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#define CR0_DFS_16BIT 0x2
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#define CR0_SCPH_OFFSET 6
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#define CR0_EM_OFFSET 11
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#define CR0_EM_LITTLE 0x0
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#define CR0_EM_BIG 0x1
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#define CR0_FBM_OFFSET 12
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#define CR0_FBM_MSB 0x0
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#define CR0_FBM_LSB 0x1
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#define CR0_BHT_OFFSET 13
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#define CR0_BHT_16BIT 0x0
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#define CR0_BHT_8BIT 0x1
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#define CR0_FRF_OFFSET 16
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#define CR0_FRF_SPI 0x0
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#define CR0_FRF_SSP 0x1
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#define CR0_FRF_MICROWIRE 0x2
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#define CR0_XFM_OFFSET 18
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#define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET)
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#define CR0_XFM_TR 0x0
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#define CR0_XFM_TO 0x1
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#define CR0_XFM_RO 0x2
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#define CR0_OPM_OFFSET 20
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#define CR0_OPM_MASTER 0x0
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#define CR0_OPM_SLAVE 0x1
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#define CR0_SOI_OFFSET 23
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/* Bit fields in SR, 6bit */
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#define SR_MASK 0x3f
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#define SR_BUSY (1 << 0)
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#define SR_TF_FULL (1 << 1)
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#define SR_TF_EMPTY (1 << 2)
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#define SR_RF_EMPTY (1 << 3)
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#define SR_RF_FULL (1 << 4)
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#define SR_SLAVE_TX_BUSY (1 << 5)
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#define SR_SS_IN_N (1 << 6)
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/* Bit fields in ISR, IMR, ISR, RISR, 5bit */
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#define INT_MASK 0x1f
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#define INT_TF_EMPTY (1 << 0)
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#define INT_TF_OVERFLOW (1 << 1)
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#define INT_RF_UNDERFLOW (1 << 2)
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#define INT_RF_OVERFLOW (1 << 3)
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#define INT_RF_FULL (1 << 4)
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#define INT_CS_INACTIVE (1 << 6)
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/* Bit fields in ICR, 4bit */
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#define ICR_MASK 0x0f
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#define ICR_ALL (1 << 0)
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#define ICR_RF_UNDERFLOW (1 << 1)
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#define ICR_RF_OVERFLOW (1 << 2)
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#define ICR_TF_OVERFLOW (1 << 3)
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/* Bit fields in DMACR */
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#define RF_DMA_EN (1 << 0)
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#define TF_DMA_EN (1 << 1)
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/* Bit fields in TIMEOUT */
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#define TIMEOUT_THRESHOLD_OFFSET 0x0
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#define TIMEOUT_COUNTER_EN (1 << 16)
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#define TIMEOUT_SINGLE_REQUEST_EN (1 << 18)
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/* Bit fields in BYPASS */
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#define BYPASS_EN (1 << 0)
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#define BYPASS_INT_TF_EN (1 << 1)
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#define CLOCK_GATING_NONE (0x0 << 2)
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#define CLOCK_GATING_SPICLK_INNER (0x1 << 2)
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#define CLOCK_GATING_SPICLK_EXT (0x2 << 2)
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#define CLOCK_GATING_ALL_IN_IDLE (0x3 << 2)
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/* Driver state flags */
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#define RXDMA (1 << 0)
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#define TXDMA (1 << 1)
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/*
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* SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However,
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* the controller seems to hang when given 0x10000, so stick with this for now.
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*/
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#define ROCKCHIP_SPI_MAX_TRANLEN 0xffff
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#define ROCKCHIP_SPI_VER2_TYPE1 0x05EC0002
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#define ROCKCHIP_SPI_VER2_TYPE2 0x00110002
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#define ROCKCHIP_SPI_VER3 0x03110003
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/*
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* The callback function may not be timely, and even cs has been released, so
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* some redundancy needs to be done for this.
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*/
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#define ROCKCHIP_SPI_DMA_CB_REDUNDANCY_US 10000
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/*
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* Tclk-invalid-to-cs-deassert
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*/
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#define ROCKCHIP_SPI_CLK_TO_CS_DEASSERT_US 10000
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enum rockchip_spi_slave_xfer_mode {
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ROCKCHIP_SPI_DMA,
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ROCKCHIP_SPI_IRQ,
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};
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struct rockchip_spi {
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struct device *dev;
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struct clk_bulk_data *clks;
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unsigned int clk_cnt;
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void __iomem *regs;
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dma_addr_t dma_addr_rx;
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dma_addr_t dma_addr_tx;
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u32 *dma_buf;
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dma_addr_t dma_phys;
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const void *tx;
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void *rx;
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unsigned int tx_left;
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unsigned int rx_left;
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atomic_t state;
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struct completion xfer_done;
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u32 version;
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/*depth of the FIFO buffer */
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u32 fifo_len;
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int max_transfer_size;
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u32 fixed_burst_size;
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u8 tx_idle_type; /* 0-SR_TF_EMPTY 1-SR_SLAVE_TX_BUSY */
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u32 dma_timeout;
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u8 n_bytes;
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bool slave_aborted;
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bool cs_inactive; /* spi slave tansmition stop when cs inactive */
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struct gpio_desc *ready; /* spi slave transmission ready */
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struct spi_transfer *xfer; /* Store xfer temporarily */
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enum rockchip_spi_slave_xfer_mode xfer_mode;
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bool ext_spi_clk;
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bool verbose;
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ktime_t dbg_time;
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};
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static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable)
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{
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if (rs->ext_spi_clk)
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writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_BYPASS_ENR);
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writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR);
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}
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static inline void wait_for_tx_idle(struct rockchip_spi *rs)
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{
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unsigned long timeout = jiffies + msecs_to_jiffies(5);
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u32 bit_filed = SR_TF_EMPTY;
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u32 idle_val = 1;
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/* When using external clock, tx clk can function normally without waiting for idle */
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if (rs->ext_spi_clk)
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return;
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if (rs->tx_idle_type == 1) {
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bit_filed = SR_SLAVE_TX_BUSY;
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idle_val = 0;
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}
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do {
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if ((readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & bit_filed) == idle_val) {
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if (bit_filed == SR_TF_EMPTY)
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udelay(1);
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return;
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}
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} while (!time_after(jiffies, timeout));
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dev_warn(rs->dev, "spi controller is in busy state!\n");
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}
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static void rockchip_spi_slave_pio_writer(struct rockchip_spi *rs)
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{
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u32 tx_free = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
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u32 words = min(rs->tx_left, tx_free);
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rs->tx_left -= words;
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for (; words; words--) {
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u32 txw;
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if (rs->n_bytes == 1)
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txw = *(u8 *)rs->tx;
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else
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txw = *(u16 *)rs->tx;
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writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
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rs->tx += rs->n_bytes;
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}
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}
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static void rockchip_spi_slave_pio_reader(struct rockchip_spi *rs)
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{
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u32 rx_valid = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
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u32 words = min(rs->rx_left, rx_valid);
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rs->rx_left -= words;
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for (; words; words--) {
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u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
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if (!rs->rx)
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continue;
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if (rs->n_bytes == 1)
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*(u8 *)rs->rx = (u8)rxw;
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else
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*(u16 *)rs->rx = (u16)rxw;
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rs->rx += rs->n_bytes;
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}
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}
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static int rockchop_spi_rx_fifo_flush(struct spi_controller *ctlr)
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{
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struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
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u32 rx_fifo_left;
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/* Flush rx fifo */
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rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
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for (; rx_fifo_left; rx_fifo_left--)
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readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
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return 0;
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}
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static void rockchip_spi_slave_handle_err(struct spi_controller *ctlr)
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{
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struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
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dev_err(rs->dev, "state=%x\n", atomic_read(&rs->state));
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dev_err(rs->dev, "tx_left=%x\n", rs->tx_left);
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dev_err(rs->dev, "rx_left=%x\n", rs->rx_left);
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print_hex_dump(KERN_ERR, "regs ", DUMP_PREFIX_OFFSET, 4, 4, rs->regs, 0x58, 0);
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rockchop_spi_rx_fifo_flush(ctlr);
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if (atomic_read(&rs->state) & TXDMA)
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dmaengine_terminate_async(ctlr->dma_tx);
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if (atomic_read(&rs->state) & RXDMA)
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dmaengine_terminate_async(ctlr->dma_rx);
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atomic_set(&rs->state, 0);
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}
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static irqreturn_t rockchip_spi_slave_isr(int irq, void *dev_id)
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{
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struct spi_controller *ctlr = dev_id;
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struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
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if (rs->xfer_mode == ROCKCHIP_SPI_IRQ) {
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if (rs->tx_left)
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rockchip_spi_slave_pio_writer(rs);
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rockchip_spi_slave_pio_reader(rs);
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if (!rs->rx_left) {
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writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
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writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
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complete(&rs->xfer_done);
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return IRQ_HANDLED;
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}
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}
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/* When int_cs_inactive comes, spi slave abort */
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if (rs->cs_inactive && readl_relaxed(rs->regs + ROCKCHIP_SPI_ISR) & INT_CS_INACTIVE) {
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rs->slave_aborted = true;
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writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
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writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
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complete(&rs->xfer_done);
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}
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return IRQ_HANDLED;
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}
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static int rockchip_spi_slave_prepare_irq(struct rockchip_spi *rs,
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struct spi_controller *ctlr,
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struct spi_transfer *xfer)
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{
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rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0;
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rs->rx_left = xfer->len / rs->n_bytes;
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writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
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spi_enable_chip(rs, true);
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if (rs->tx_left)
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rockchip_spi_slave_pio_writer(rs);
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if (rs->cs_inactive)
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writel_relaxed(INT_RF_FULL | INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR);
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else
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writel_relaxed(INT_RF_FULL, rs->regs + ROCKCHIP_SPI_IMR);
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/* 1 means the transfer is in progress */
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return 1;
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}
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static void rockchip_spi_slave_dma_rxcb(void *data)
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{
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struct spi_controller *ctlr = data;
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struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
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int state = atomic_fetch_andnot(RXDMA, &rs->state);
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if (state & TXDMA)
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return;
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complete(&rs->xfer_done);
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}
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static void rockchip_spi_slave_dma_txcb(void *data)
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{
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struct spi_controller *ctlr = data;
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struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
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int state = atomic_fetch_andnot(TXDMA, &rs->state);
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if (state & RXDMA)
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return;
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complete(&rs->xfer_done);
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}
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static u32 rockchip_spi_slave_calc_burst_size(struct rockchip_spi *rs, u32 data_len)
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{
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u32 i;
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if (rs->dma_timeout)
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return rs->fixed_burst_size;
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/* burst size: 1, 2, 4, 8, 16 */
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for (i = 1; i < 16; i <<= 1) {
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if (data_len & i)
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break;
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}
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return i;
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}
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static int rockchip_spi_slave_prepare_dma(struct rockchip_spi *rs,
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struct spi_controller *ctlr, struct spi_transfer *xfer)
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{
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struct dma_async_tx_descriptor *rxdesc = NULL, *txdesc = NULL;
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atomic_set(&rs->state, 0);
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if (xfer->rx_buf) {
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struct dma_slave_config rxconf = {
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.direction = DMA_DEV_TO_MEM,
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.src_addr = rs->dma_addr_rx,
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.src_addr_width = rs->n_bytes,
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.src_maxburst = rockchip_spi_slave_calc_burst_size(rs, xfer->len / rs->n_bytes),
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};
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dmaengine_slave_config(ctlr->dma_rx, &rxconf);
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rxdesc = dmaengine_prep_slave_single(ctlr->dma_rx, rs->dma_phys, xfer->len,
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DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
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if (!rxdesc)
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return -EINVAL;
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rxdesc->callback = rockchip_spi_slave_dma_rxcb;
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rxdesc->callback_param = ctlr;
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}
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if (xfer->tx_buf) {
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struct dma_slave_config txconf = {
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.direction = DMA_MEM_TO_DEV,
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.dst_addr = rs->dma_addr_tx,
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.dst_addr_width = rs->n_bytes,
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.dst_maxburst = 8,
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};
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dmaengine_slave_config(ctlr->dma_tx, &txconf);
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memcpy(rs->dma_buf, xfer->tx_buf, xfer->len);
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txdesc = dmaengine_prep_slave_single(ctlr->dma_tx, rs->dma_phys, xfer->len,
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DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
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if (!txdesc) {
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if (rxdesc)
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dmaengine_terminate_sync(ctlr->dma_rx);
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return -EINVAL;
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}
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txdesc->callback = rockchip_spi_slave_dma_txcb;
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txdesc->callback_param = ctlr;
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}
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/* rx must be started before tx due to spi instinct */
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if (rxdesc) {
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atomic_or(RXDMA, &rs->state);
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ctlr->dma_rx->cookie = dmaengine_submit(rxdesc);
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dma_async_issue_pending(ctlr->dma_rx);
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}
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if (rs->cs_inactive)
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writel_relaxed(INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR);
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spi_enable_chip(rs, true);
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if (txdesc) {
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atomic_or(TXDMA, &rs->state);
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dmaengine_submit(txdesc);
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dma_async_issue_pending(ctlr->dma_tx);
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}
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/* 1 means the transfer is in progress */
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return 1;
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}
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static int rockchip_spi_slave_config(struct rockchip_spi *rs,
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struct spi_device *spi, struct spi_transfer *xfer)
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{
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u32 cr0 = CR0_FRF_SPI << CR0_FRF_OFFSET
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| CR0_BHT_8BIT << CR0_BHT_OFFSET
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| CR0_EM_BIG << CR0_EM_OFFSET
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| CR0_OPM_SLAVE << CR0_OPM_OFFSET;
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u32 cr1;
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u32 dmacr = 0;
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u32 val = 0;
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rs->slave_aborted = false;
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cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET;
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if (spi->mode & SPI_LSB_FIRST)
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cr0 |= CR0_FBM_LSB << CR0_FBM_OFFSET;
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if (xfer->rx_buf && xfer->tx_buf) {
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cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET;
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} else if (xfer->rx_buf) {
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cr0 |= CR0_XFM_RO << CR0_XFM_OFFSET;
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} else if (xfer->tx_buf) {
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/*
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* Use the water line of rx fifo in full duplex mode to trigger
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* the interruption of tx irq transmission completion.
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* For the new version of SPI witch support ext_spi_clk, TX under
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* IRQ transmission can only be developed using TR.
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*/
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if (rs->xfer_mode == ROCKCHIP_SPI_IRQ)
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cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET;
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else
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cr0 |= CR0_XFM_TO << CR0_XFM_OFFSET;
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} else {
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dev_err(rs->dev, "no transmission buffer\n");
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return -EINVAL;
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}
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switch (xfer->bits_per_word) {
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case 4:
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cr0 |= CR0_DFS_4BIT << CR0_DFS_OFFSET;
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cr1 = xfer->len - 1;
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break;
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case 8:
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cr0 |= CR0_DFS_8BIT << CR0_DFS_OFFSET;
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cr1 = xfer->len - 1;
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break;
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case 16:
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cr0 |= CR0_DFS_16BIT << CR0_DFS_OFFSET;
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cr1 = xfer->len / 2 - 1;
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if (xfer->len & 0x1) {
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dev_err(rs->dev, "xfer->len is not aligned with 16bits\n");
|
return -EINVAL;
|
}
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break;
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default:
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/* we only whitelist 4, 8 and 16 bit words in
|
* ctlr->bits_per_word_mask, so this shouldn't
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* happen
|
*/
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dev_err(rs->dev, "unknown bits per word: %d\n",
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xfer->bits_per_word);
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return -EINVAL;
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}
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if (rs->xfer_mode == ROCKCHIP_SPI_DMA) {
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if (xfer->tx_buf)
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dmacr |= TF_DMA_EN;
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if (xfer->rx_buf)
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dmacr |= RF_DMA_EN;
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}
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writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
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writel_relaxed(cr1, rs->regs + ROCKCHIP_SPI_CTRLR1);
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if (rs->ext_spi_clk) {
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val = BYPASS_EN | BYPASS_INT_TF_EN | CLOCK_GATING_NONE;
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writel_relaxed(val, rs->regs + ROCKCHIP_SPI_BYPASS);
|
}
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if (rs->dma_timeout) {
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val = TIMEOUT_SINGLE_REQUEST_EN | TIMEOUT_COUNTER_EN |
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16 << TIMEOUT_THRESHOLD_OFFSET;
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writel_relaxed(val, rs->regs + ROCKCHIP_SPI_TIMEOUT);
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}
|
|
/* unfortunately setting the fifo threshold level to generate an
|
* interrupt exactly when the fifo is full doesn't seem to work,
|
* so we need the strict inequality here
|
*/
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if ((xfer->len / rs->n_bytes) < rs->fifo_len)
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writel_relaxed(xfer->len / rs->n_bytes - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
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else
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writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
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writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_DMATDLR);
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writel_relaxed(rockchip_spi_slave_calc_burst_size(rs, xfer->len / rs->n_bytes) - 1,
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rs->regs + ROCKCHIP_SPI_DMARDLR);
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writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
|
|
return 0;
|
}
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|
static size_t rockchip_spi_slave_max_transfer_size(struct spi_device *spi)
|
{
|
struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller);
|
|
return rs->max_transfer_size;
|
}
|
|
static int rockchip_spi_slave_transfer_wait(struct spi_controller *ctlr)
|
{
|
struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
|
int state;
|
int ret = 0;
|
|
if (wait_for_completion_interruptible(&rs->xfer_done)) {
|
dev_dbg(rs->dev, "RK SPI transfer interrupted\n");
|
ret = -EINTR;
|
goto out;
|
}
|
|
if (rs->slave_aborted) {
|
if (rs->xfer_mode == ROCKCHIP_SPI_DMA) {
|
state = atomic_read(&rs->state);
|
reinit_completion(&rs->xfer_done);
|
|
if (state && state == atomic_read(&rs->state) &&
|
wait_for_completion_interruptible_timeout(&rs->xfer_done,
|
ROCKCHIP_SPI_DMA_CB_REDUNDANCY_US) <= 0) {
|
dev_err(rs->dev, "RK SPI transfer slave abort\n");
|
ret = -EIO;
|
goto out;
|
} else {
|
dev_dbg(rs->dev, "RK SPI transfer slave dma cb lately\n");
|
}
|
} else {
|
dev_err(rs->dev, "RK SPI transfer slave abort\n");
|
ret = -EIO;
|
goto out;
|
}
|
|
}
|
|
if (rs->xfer->tx_buf)
|
wait_for_tx_idle(rs);
|
out:
|
if (ret)
|
rockchip_spi_slave_handle_err(ctlr);
|
|
return 0;
|
}
|
|
static int rockchip_spi_slave_stop(struct spi_controller *ctlr)
|
{
|
struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
|
|
spi_enable_chip(rs, false);
|
|
return 0;
|
}
|
|
static int rockchip_spi_slave_do_one_msg(struct spi_controller *ctlr, struct spi_message *m)
|
{
|
struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
|
struct spi_device *spi = m->spi;
|
struct spi_transfer *xfer;
|
int ret = -EINVAL;
|
bool use_dma;
|
u32 status;
|
|
WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) &&
|
(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
|
|
if (rs->cs_inactive) {
|
ret = readl_poll_timeout(rs->regs + ROCKCHIP_SPI_SR, status,
|
status & SR_SS_IN_N, 20,
|
ROCKCHIP_SPI_CLK_TO_CS_DEASSERT_US);
|
if (ret) {
|
dev_err(rs->dev, "The cs of spi master is still asserted\n");
|
ret = -EIO;
|
goto out;
|
}
|
}
|
|
list_for_each_entry(xfer, &m->transfers, transfer_list) {
|
if (!xfer->len || (!xfer->tx_buf && !xfer->rx_buf)) {
|
dev_err(rs->dev, "No buffer for transfer\n");
|
ret = -EINVAL;
|
goto out;
|
}
|
|
if (xfer->len > rs->max_transfer_size) {
|
dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len);
|
ret = -EINVAL;
|
goto out;
|
}
|
|
rs->n_bytes = xfer->bits_per_word <= 8 ? 1 : 2;
|
rs->xfer = xfer;
|
|
use_dma = ctlr->can_dma(ctlr, spi, xfer);
|
if (use_dma)
|
rs->xfer_mode = ROCKCHIP_SPI_DMA;
|
else
|
rs->xfer_mode = ROCKCHIP_SPI_IRQ;
|
|
ret = rockchip_spi_slave_config(rs, spi, xfer);
|
if (ret)
|
goto out;
|
|
rs->tx = xfer->tx_buf;
|
rs->rx = xfer->rx_buf;
|
|
reinit_completion(&rs->xfer_done);
|
|
switch (rs->xfer_mode) {
|
case ROCKCHIP_SPI_DMA:
|
ret = rockchip_spi_slave_prepare_dma(rs, ctlr, xfer);
|
break;
|
default:
|
ret = rockchip_spi_slave_prepare_irq(rs, ctlr, xfer);
|
}
|
|
if (rs->ready) {
|
gpiod_set_value(rs->ready, 0);
|
gpiod_set_value(rs->ready, 1);
|
}
|
|
if (rs->verbose)
|
dev_info(rs->dev, "cur_gap=%lldus\n",
|
ktime_to_us(ktime_sub(ktime_get(), rs->dbg_time)));
|
if (ret > 0)
|
ret = rockchip_spi_slave_transfer_wait(ctlr);
|
if (rs->verbose)
|
rs->dbg_time = ktime_get();
|
|
rockchip_spi_slave_stop(ctlr);
|
|
if (xfer->rx_buf && rs->xfer_mode == ROCKCHIP_SPI_DMA)
|
memcpy(xfer->rx_buf, rs->dma_buf, xfer->len);
|
|
m->actual_length += xfer->len;
|
|
if (xfer->delay_usecs)
|
udelay(xfer->delay_usecs);
|
}
|
|
out:
|
m->status = ret;
|
|
spi_finalize_current_message(ctlr);
|
return 0;
|
}
|
|
static bool rockchip_spi_slave_can_dma(struct spi_controller *ctlr,
|
struct spi_device *spi,
|
struct spi_transfer *xfer)
|
{
|
struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
|
unsigned int bytes_per_word = xfer->bits_per_word <= 8 ? 1 : 2;
|
|
/* if the numbor of spi words to transfer is less than the fifo
|
* length we can just fill the fifo and wait for a single irq,
|
* so don't bother setting up dma
|
*/
|
return xfer->len / bytes_per_word >= rs->fifo_len;
|
}
|
|
static int rockchip_spi_slave_setup(struct spi_device *spi)
|
{
|
struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller);
|
u32 cr0;
|
|
pm_runtime_get_sync(rs->dev);
|
|
cr0 = readl_relaxed(rs->regs + ROCKCHIP_SPI_CTRLR0);
|
cr0 |= ((spi->mode & 0x3) << CR0_SCPH_OFFSET) | CR0_OPM_SLAVE << CR0_OPM_OFFSET;
|
writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
|
|
pm_runtime_put(rs->dev);
|
|
return 0;
|
}
|
|
static int rockchip_spi_slave_probe(struct platform_device *pdev)
|
{
|
int ret = 0;
|
struct rockchip_spi *rs;
|
struct spi_controller *ctlr;
|
struct resource *mem;
|
struct device_node *sram_np;
|
struct resource sram_res;
|
u32 val;
|
|
ctlr = spi_alloc_slave(&pdev->dev, sizeof(struct rockchip_spi));
|
if (!ctlr)
|
return -ENOMEM;
|
|
ctlr->rt = true;
|
platform_set_drvdata(pdev, ctlr);
|
|
rs = spi_controller_get_devdata(ctlr);
|
|
/* Get basic io resource and map it */
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
rs->regs = devm_ioremap_resource(&pdev->dev, mem);
|
if (IS_ERR(rs->regs)) {
|
ret = PTR_ERR(rs->regs);
|
goto err_put_ctlr;
|
}
|
|
if (!has_acpi_companion(&pdev->dev))
|
ret = devm_clk_bulk_get_all(&pdev->dev, &rs->clks);
|
if (ret < 0) {
|
dev_err(&pdev->dev, "Failed to get clks\n");
|
goto err_put_ctlr;
|
}
|
rs->clk_cnt = ret;
|
|
if (!has_acpi_companion(&pdev->dev))
|
ret = clk_bulk_prepare_enable(rs->clk_cnt, rs->clks);
|
if (ret) {
|
dev_err(&pdev->dev, "Failed to enable clks\n");
|
goto err_put_ctlr;
|
}
|
|
ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
|
if (ret) {
|
dev_err(&pdev->dev, "Failed to set dma mask\n");
|
goto err_put_ctlr;
|
}
|
|
sram_np = of_parse_phandle(pdev->dev.of_node, "rockchip,sram", 0);
|
if (sram_np) {
|
/* get sram start and size */
|
ret = of_address_to_resource(sram_np, 0, &sram_res);
|
if (ret) {
|
dev_err(&pdev->dev, "find sram res error\n");
|
goto err_put_ctlr;
|
}
|
|
rs->max_transfer_size = resource_size(&sram_res);
|
rs->dma_phys = sram_res.start;
|
rs->dma_buf = devm_ioremap_resource(&pdev->dev, &sram_res);
|
if (IS_ERR(rs->dma_buf)) {
|
ret = PTR_ERR(rs->dma_buf);
|
goto err_put_ctlr;
|
}
|
dev_err(&pdev->dev, "set sram_buf\n");
|
} else {
|
rs->max_transfer_size = ROCKCHIP_SPI_MAX_TRANLEN;
|
rs->dma_buf = dma_alloc_coherent(&pdev->dev, rs->max_transfer_size + 1,
|
&rs->dma_phys, GFP_KERNEL);
|
if (!rs->dma_buf) {
|
ret = -ENOMEM;
|
goto err_put_ctlr;
|
}
|
}
|
|
spi_enable_chip(rs, false);
|
|
ret = platform_get_irq(pdev, 0);
|
if (ret < 0)
|
goto err_disable_spiclk;
|
|
ret = devm_request_irq(&pdev->dev, ret, rockchip_spi_slave_isr, 0, dev_name(&pdev->dev), ctlr);
|
if (ret)
|
goto err_disable_spiclk;
|
|
rs->dev = &pdev->dev;
|
|
rs->version = readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION);
|
rs->verbose = 0;
|
|
device_property_read_u32(&pdev->dev, "rockchip,autosuspend-delay-ms", &val);
|
if (val <= 0)
|
val = (ROCKCHIP_SPI_CLK_TO_CS_DEASSERT_US + 999) / 1000;
|
pm_runtime_set_autosuspend_delay(&pdev->dev, val);
|
pm_runtime_use_autosuspend(&pdev->dev);
|
pm_runtime_set_active(&pdev->dev);
|
pm_runtime_enable(&pdev->dev);
|
ctlr->auto_runtime_pm = true;
|
|
ctlr->bus_num = pdev->id;
|
ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
|
ctlr->dev.of_node = pdev->dev.of_node;
|
ctlr->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8) | SPI_BPW_MASK(4);
|
|
ctlr->setup = rockchip_spi_slave_setup;
|
ctlr->transfer_one_message = rockchip_spi_slave_do_one_msg;
|
ctlr->max_transfer_size = rockchip_spi_slave_max_transfer_size;
|
|
ctlr->dma_tx = dma_request_chan(rs->dev, "tx");
|
if (IS_ERR(ctlr->dma_tx)) {
|
/* Check tx to see if we need defer probing driver */
|
if (PTR_ERR(ctlr->dma_tx) == -EPROBE_DEFER) {
|
ret = -EPROBE_DEFER;
|
goto err_disable_pm_runtime;
|
}
|
dev_warn(rs->dev, "Failed to request TX DMA channel\n");
|
ret = -EINVAL;
|
goto err_disable_spiclk;
|
}
|
ctlr->dma_rx = dma_request_chan(rs->dev, "rx");
|
if (IS_ERR(ctlr->dma_rx)) {
|
if (PTR_ERR(ctlr->dma_rx) == -EPROBE_DEFER) {
|
ret = -EPROBE_DEFER;
|
goto err_free_dma_tx;
|
}
|
dev_warn(rs->dev, "Failed to request RX DMA channel\n");
|
ret = -EINVAL;
|
goto err_free_dma_tx;
|
}
|
rs->dma_addr_tx = mem->start + ROCKCHIP_SPI_TXDR;
|
rs->dma_addr_rx = mem->start + ROCKCHIP_SPI_RXDR;
|
ctlr->can_dma = rockchip_spi_slave_can_dma;
|
|
init_completion(&rs->xfer_done);
|
switch (rs->version) {
|
case ROCKCHIP_SPI_VER3:
|
rs->ext_spi_clk = true;
|
rs->dma_timeout = 16;
|
rs->fixed_burst_size = 16;
|
rs->tx_idle_type = 1;
|
rs->cs_inactive = true;
|
rs->fifo_len = 64;
|
break;
|
case ROCKCHIP_SPI_VER2_TYPE2:
|
rs->tx_idle_type = 1;
|
rs->cs_inactive = true;
|
rs->fifo_len = 64;
|
break;
|
case ROCKCHIP_SPI_VER2_TYPE1:
|
rs->tx_idle_type = 0;
|
rs->cs_inactive = true;
|
rs->fifo_len = 64;
|
break;
|
default:
|
rs->ext_spi_clk = false;
|
rs->dma_timeout = 0;
|
rs->fixed_burst_size = 0;
|
rs->tx_idle_type = 0;
|
rs->cs_inactive = false;
|
rs->fifo_len = 32;
|
}
|
|
if (device_property_read_bool(&pdev->dev, "rockchip,cs-inactive-disable"))
|
rs->cs_inactive = false;
|
|
if (!device_property_read_bool(&pdev->dev, "rockchip,dma-support-req-mix"))
|
rs->dma_timeout = 0;
|
|
rs->ready = devm_gpiod_get_optional(&pdev->dev, "ready", GPIOD_OUT_HIGH);
|
if (IS_ERR(rs->ready)) {
|
ret = PTR_ERR(rs->ready);
|
dev_err(&pdev->dev, "invalid ready-gpios property in node\n");
|
goto err_free_dma_rx;
|
}
|
|
ret = devm_spi_register_controller(&pdev->dev, ctlr);
|
if (ret < 0) {
|
dev_err(&pdev->dev, "Failed to register controller\n");
|
goto err_free_dma_rx;
|
}
|
|
dev_info(rs->dev, "slave probed, cs-inactive=%d, ready=%d, ext=%d, dam_buf=%x\n",
|
rs->cs_inactive, rs->ready ? 1 : 0, rs->ext_spi_clk, (u32)rs->dma_phys);
|
|
return 0;
|
|
err_free_dma_rx:
|
dma_release_channel(ctlr->dma_rx);
|
err_free_dma_tx:
|
dma_release_channel(ctlr->dma_tx);
|
err_disable_pm_runtime:
|
pm_runtime_disable(&pdev->dev);
|
err_disable_spiclk:
|
clk_bulk_disable_unprepare(rs->clk_cnt, rs->clks);
|
err_put_ctlr:
|
spi_controller_put(ctlr);
|
|
return ret;
|
}
|
|
static int rockchip_spi_slave_remove(struct platform_device *pdev)
|
{
|
struct spi_controller *ctlr = spi_controller_get(platform_get_drvdata(pdev));
|
struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
|
|
pm_runtime_get_sync(&pdev->dev);
|
|
clk_bulk_disable_unprepare(rs->clk_cnt, rs->clks);
|
|
pm_runtime_put_noidle(&pdev->dev);
|
pm_runtime_disable(&pdev->dev);
|
pm_runtime_set_suspended(&pdev->dev);
|
|
if (ctlr->dma_tx)
|
dma_release_channel(ctlr->dma_tx);
|
if (ctlr->dma_rx)
|
dma_release_channel(ctlr->dma_rx);
|
|
spi_controller_put(ctlr);
|
|
return 0;
|
}
|
|
#ifdef CONFIG_PM
|
static int rockchip_spi_slave_runtime_suspend(struct device *dev)
|
{
|
struct spi_controller *ctlr = dev_get_drvdata(dev);
|
struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
|
|
clk_bulk_disable_unprepare(rs->clk_cnt, rs->clks);
|
|
return 0;
|
}
|
|
static int rockchip_spi_slave_runtime_resume(struct device *dev)
|
{
|
struct spi_controller *ctlr = dev_get_drvdata(dev);
|
struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
|
|
return clk_bulk_prepare_enable(rs->clk_cnt, rs->clks);
|
}
|
#endif /* CONFIG_PM */
|
|
#ifdef CONFIG_PM_SLEEP
|
static int rockchip_spi_slave_suspend(struct device *dev)
|
{
|
int ret;
|
struct spi_controller *ctlr = dev_get_drvdata(dev);
|
|
ret = spi_controller_suspend(ctlr);
|
if (ret < 0)
|
return ret;
|
|
/* Avoid redundant clock disable */
|
if (!pm_runtime_status_suspended(dev))
|
rockchip_spi_slave_runtime_suspend(dev);
|
|
pinctrl_pm_select_sleep_state(dev);
|
|
return 0;
|
}
|
|
static int rockchip_spi_slave_resume(struct device *dev)
|
{
|
int ret;
|
struct spi_controller *ctlr = dev_get_drvdata(dev);
|
|
pinctrl_pm_select_default_state(dev);
|
|
if (!pm_runtime_status_suspended(dev)) {
|
ret = rockchip_spi_slave_runtime_resume(dev);
|
if (ret < 0)
|
return ret;
|
}
|
|
ret = spi_controller_resume(ctlr);
|
if (ret < 0)
|
rockchip_spi_slave_runtime_suspend(dev);
|
|
return 0;
|
}
|
#endif /* CONFIG_PM_SLEEP */
|
|
static const struct dev_pm_ops rockchip_spi_slave_pm = {
|
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rockchip_spi_slave_suspend, rockchip_spi_slave_resume)
|
SET_RUNTIME_PM_OPS(rockchip_spi_slave_runtime_suspend,
|
rockchip_spi_slave_runtime_resume, NULL)
|
};
|
|
static const struct of_device_id rockchip_spi_slave_dt_match[] = {
|
{ .compatible = "rockchip,spi-slave", },
|
{ },
|
};
|
MODULE_DEVICE_TABLE(of, rockchip_spi_slave_dt_match);
|
|
static struct platform_driver rockchip_spi_slave_driver = {
|
.driver = {
|
.name = DRIVER_NAME,
|
.pm = &rockchip_spi_slave_pm,
|
.of_match_table = of_match_ptr(rockchip_spi_slave_dt_match),
|
},
|
.probe = rockchip_spi_slave_probe,
|
.remove = rockchip_spi_slave_remove,
|
};
|
|
module_platform_driver(rockchip_spi_slave_driver);
|
|
MODULE_AUTHOR("Jon Lin <jon.lin@rock-chips.com>");
|
MODULE_DESCRIPTION("ROCKCHIP SPI Slave Controller Driver");
|
MODULE_LICENSE("GPL");
|
