// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2021 Rockchip Electronics Co., Ltd.
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*/
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#include <asm/cacheflush.h>
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/dma-mapping.h>
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#include <linux/initramfs.h>
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#include <linux/interrupt.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/kthread.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/soc/rockchip/rockchip_decompress.h>
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#define SHA256_PROBE_TIMEOUT 1000
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#define SHA256_COMPARE_TIMEOUT 2000
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#define SHA256_HASH_SIZE 32
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#define _SBF(s, v) ((v) << (s))
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#define CRYPTO_WRITE_MASK_SHIFT (16)
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#define CRYPTO_WRITE_MASK_ALL ((0xffffu << CRYPTO_WRITE_MASK_SHIFT))
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/* Crypto DMA control registers*/
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#define CRYPTO_DMA_INT_EN 0x0008
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#define CRYPTO_ZERO_ERR_INT_EN BIT(6)
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#define CRYPTO_LIST_ERR_INT_EN BIT(5)
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#define CRYPTO_SRC_ERR_INT_EN BIT(4)
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#define CRYPTO_DST_ERR_INT_EN BIT(3)
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#define CRYPTO_SRC_ITEM_INT_EN BIT(2)
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#define CRYPTO_DST_ITEM_DONE_INT_EN BIT(1)
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#define CRYPTO_LIST_DONE_INT_EN BIT(0)
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#define CRYPTO_DMA_INT_ST 0x000C
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#define CRYPTO_ZERO_LEN_INT_ST BIT(6)
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#define CRYPTO_LIST_ERR_INT_ST BIT(5)
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#define CRYPTO_SRC_ERR_INT_ST BIT(4)
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#define CRYPTO_DST_ERR_INT_ST BIT(3)
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#define CRYPTO_SRC_ITEM_DONE_INT_ST BIT(2)
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#define CRYPTO_DST_ITEM_DONE_INT_ST BIT(1)
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#define CRYPTO_LIST_DONE_INT_ST BIT(0)
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#define CRYPTO_DMA_CTL 0x0010
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#define CRYPTO_DMA_RESTART BIT(1)
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#define CRYPTO_DMA_START BIT(0)
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/* DMA LIST Start Address Register */
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#define CRYPTO_DMA_LLI_ADDR 0x0014
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#define CRYPTO_FIFO_CTL 0x0040
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#define CRYPTO_DOUT_BYTESWAP BIT(1)
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#define CRYPTO_DOIN_BYTESWAP BIT(0)
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/* Hash Control Register */
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#define CRYPTO_HASH_CTL 0x0048
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#define CRYPTO_SHA1 _SBF(4, 0x00)
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#define CRYPTO_MD5 _SBF(4, 0x01)
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#define CRYPTO_SHA256 _SBF(4, 0x02)
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#define CRYPTO_SHA224 _SBF(4, 0x03)
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#define CRYPTO_SM3 _SBF(4, 0x06)
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#define CRYPTO_SHA512 _SBF(4, 0x08)
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#define CRYPTO_SHA384 _SBF(4, 0x09)
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#define CRYPTO_SHA512_224 _SBF(4, 0x0A)
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#define CRYPTO_SHA512_256 _SBF(4, 0x0B)
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#define CRYPTO_HMAC_ENABLE BIT(3)
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#define CRYPTO_HW_PAD_ENABLE BIT(2)
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#define CRYPTO_HASH_SRC_SEL BIT(1)
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#define CRYPTO_HASH_ENABLE BIT(0)
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#define CRYPTO_HASH_DOUT_0 0x03a0
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#define CRYPTO_HASH_DOUT_1 0x03a4
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#define CRYPTO_HASH_DOUT_2 0x03a8
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#define CRYPTO_HASH_DOUT_3 0x03ac
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#define CRYPTO_HASH_DOUT_4 0x03b0
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#define CRYPTO_HASH_DOUT_5 0x03b4
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#define CRYPTO_HASH_DOUT_6 0x03b8
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#define CRYPTO_HASH_DOUT_7 0x03bc
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#define CRYPTO_HASH_DOUT_8 0x03c0
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#define CRYPTO_HASH_DOUT_9 0x03c4
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#define CRYPTO_HASH_DOUT_10 0x03c8
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#define CRYPTO_HASH_DOUT_11 0x03cc
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#define CRYPTO_HASH_DOUT_12 0x03d0
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#define CRYPTO_HASH_DOUT_13 0x03d4
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#define CRYPTO_HASH_DOUT_14 0x03d8
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#define CRYPTO_HASH_DOUT_15 0x03dc
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#define CRYPTO_HASH_VALID 0x03e4
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#define CRYPTO_HASH_IS_VALID BIT(0)
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#define LLI_DMA_CTRL_LAST BIT(0)
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#define LLI_DMA_CTRL_PAUSE BIT(1)
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#define LLI_DMA_CTRL_LIST_DONE BIT(8)
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#define LLI_DMA_CTRL_DST_DONE BIT(9)
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#define LLI_DMA_CTRL_SRC_DONE BIT(10)
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#define LLI_USER_CPIHER_START BIT(0)
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#define LLI_USER_STRING_START BIT(1)
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#define LLI_USER_STRING_LAST BIT(2)
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#define LLI_USER_STRING_ADA BIT(3)
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#define LLI_USER_PRIVACY_KEY BIT(7)
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#define LLI_USER_ROOT_KEY BIT(8)
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#define CRYPTO_READ(dev, offset) \
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readl_relaxed(((dev)->reg + (offset)))
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#define CRYPTO_WRITE(dev, offset, val) \
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writel_relaxed((val), ((dev)->reg + (offset)))
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#ifdef DEBUG
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#define CRYPTO_TRACE(format, ...) pr_err("[%s, %05d]-trace: " format "\n", \
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__func__, __LINE__, ##__VA_ARGS__)
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#define CRYPTO_MSG(format, ...) pr_err("[%s, %05d]-msg:" format "\n", \
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__func__, __LINE__, ##__VA_ARGS__)
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#define CRYPTO_DUMPHEX(var_name, data, len) \
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print_hex_dump(KERN_CONT, (var_name), \
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DUMP_PREFIX_OFFSET, \
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16, 1, (data), (len), false)
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#else
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#define CRYPTO_TRACE(format, ...)
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#define CRYPTO_MSG(format, ...)
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#define CRYPTO_DUMPHEX(var_name, data, len)
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#endif
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struct crypto_lli_desc {
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u32 src_addr;
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u32 src_len;
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u32 dst_addr;
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u32 dst_len;
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u32 user_define;
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u32 reserve;
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u32 dma_ctrl;
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u32 next_addr;
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};
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struct crypto_data {
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struct device *dev;
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void __iomem *reg;
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int irq;
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int clks_num;
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struct clk_bulk_data *clk_bulks;
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struct crypto_lli_desc *desc;
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dma_addr_t desc_dma;
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int calc_ret;
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void (*done_cb)(void *user_data,
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int hash_ret,
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u8 *hash_val);
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void *cb_data;
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u8 *hash;
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};
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enum endian_mode {
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BIG_ENDIAN = 0,
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LITTLE_ENDIAN
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};
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static struct crypto_data *g_crypto_info;
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static DECLARE_COMPLETION(sha256_probe_complete);
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static DECLARE_WAIT_QUEUE_HEAD(crypto_sha256_compare_done);
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static bool compare_done;
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int __init rk_tb_crypto_sha256_wait_compare_done(void)
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{
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if (wait_event_timeout(crypto_sha256_compare_done, compare_done,
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SHA256_COMPARE_TIMEOUT))
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return 0;
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return -ETIMEDOUT;
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}
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static void word2byte(u32 word, u8 *ch, u32 endian)
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{
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/* 0: Big-Endian 1: Little-Endian */
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if (endian == BIG_ENDIAN) {
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ch[0] = (word >> 24) & 0xff;
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ch[1] = (word >> 16) & 0xff;
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ch[2] = (word >> 8) & 0xff;
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ch[3] = (word >> 0) & 0xff;
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} else if (endian == LITTLE_ENDIAN) {
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ch[0] = (word >> 0) & 0xff;
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ch[1] = (word >> 8) & 0xff;
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ch[2] = (word >> 16) & 0xff;
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ch[3] = (word >> 24) & 0xff;
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} else {
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ch[0] = 0;
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ch[1] = 0;
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ch[2] = 0;
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ch[3] = 0;
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}
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}
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static void sha256_done_cb(void *user_data, int hash_ret, u8 *hash_val)
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{
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CRYPTO_TRACE();
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if (!memcmp(user_data, hash_val, 32)) {
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compare_done = true;
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wake_up(&crypto_sha256_compare_done);
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}
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}
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static inline void clear_hash_out_reg(struct crypto_data *dev)
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{
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int i;
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/*clear out register*/
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for (i = 0; i < 16; i++)
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CRYPTO_WRITE(dev, CRYPTO_HASH_DOUT_0 + 4 * i, 0);
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}
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static int get_hash_value(struct crypto_data *dev, u8 *data, u32 data_len)
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{
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int ret = 0;
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u32 i, offset;
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offset = CRYPTO_HASH_DOUT_0;
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for (i = 0; i < data_len / 4; i++, offset += 4)
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word2byte(CRYPTO_READ(dev, offset), data + i * 4, BIG_ENDIAN);
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if (data_len % 4) {
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uint8_t tmp_buf[4];
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word2byte(CRYPTO_READ(dev, offset), tmp_buf, BIG_ENDIAN);
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memcpy(data + i * 4, tmp_buf, data_len % 4);
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}
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CRYPTO_WRITE(dev, CRYPTO_HASH_VALID, CRYPTO_HASH_IS_VALID);
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return ret;
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}
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static void rk_tb_crypto_disable_clk(struct crypto_data *dev)
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{
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dev_dbg(dev->dev, "clk_bulk_disable_unprepare.\n");
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clk_bulk_disable_unprepare(dev->clks_num, dev->clk_bulks);
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}
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static irqreturn_t rk_tb_crypto_irq_handle(int irq, void *dev_id)
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{
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struct crypto_data *crypto_info = platform_get_drvdata(dev_id);
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CRYPTO_TRACE("xxxxxxxxxx irq xxxxxxxxxx");
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if (crypto_info) {
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u32 interrupt_status;
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get_hash_value(crypto_info, crypto_info->hash, SHA256_HASH_SIZE);
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CRYPTO_WRITE(crypto_info, CRYPTO_HASH_CTL, CRYPTO_WRITE_MASK_ALL | 0);
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interrupt_status = CRYPTO_READ(crypto_info, CRYPTO_DMA_INT_ST);
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CRYPTO_WRITE(crypto_info, CRYPTO_DMA_INT_ST, interrupt_status);
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if (interrupt_status == CRYPTO_LIST_DONE_INT_ST)
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crypto_info->calc_ret = 0;
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CRYPTO_TRACE("interrupt_status = %08x", interrupt_status);
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if (crypto_info->done_cb)
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crypto_info->done_cb(crypto_info->cb_data,
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crypto_info->calc_ret,
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crypto_info->hash);
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rk_tb_crypto_disable_clk(crypto_info);
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}
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return IRQ_HANDLED;
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}
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int rk_tb_sha256(dma_addr_t data, size_t data_len, void *user_data)
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{
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u32 reg_ctrl = 0;
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struct crypto_data *crypto_info;
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wait_for_completion_interruptible_timeout(&sha256_probe_complete,
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SHA256_PROBE_TIMEOUT);
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crypto_info = g_crypto_info;
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if (!crypto_info)
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return -ENODEV;
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if (data % 4)
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return -EINVAL;
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clear_hash_out_reg(crypto_info);
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reg_ctrl = CRYPTO_SHA256 | CRYPTO_HW_PAD_ENABLE;
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CRYPTO_WRITE(crypto_info, CRYPTO_HASH_CTL,
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reg_ctrl | CRYPTO_WRITE_MASK_ALL);
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reg_ctrl = CRYPTO_ZERO_ERR_INT_EN |
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CRYPTO_LIST_ERR_INT_EN |
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CRYPTO_SRC_ERR_INT_EN |
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CRYPTO_DST_ERR_INT_EN |
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CRYPTO_LIST_DONE_INT_EN;
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CRYPTO_WRITE(crypto_info, CRYPTO_FIFO_CTL, 0x00030003);
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CRYPTO_WRITE(crypto_info, CRYPTO_DMA_INT_EN, reg_ctrl);
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memset(crypto_info->desc, 0x00, sizeof(*crypto_info->desc));
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crypto_info->desc->src_addr = (u32)data;
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crypto_info->desc->src_len = data_len;
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crypto_info->desc->next_addr = 0;
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crypto_info->desc->dma_ctrl = LLI_DMA_CTRL_LIST_DONE |
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LLI_DMA_CTRL_LAST;
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crypto_info->desc->user_define = LLI_USER_CPIHER_START |
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LLI_USER_STRING_START |
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LLI_USER_STRING_LAST;
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#ifdef CONFIG_ARM64
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__flush_dcache_area((void *)crypto_info->desc,
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sizeof(struct crypto_data));
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#else
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__cpuc_flush_dcache_area((void *)crypto_info->desc,
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sizeof(struct crypto_data));
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#endif
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CRYPTO_WRITE(crypto_info, CRYPTO_DMA_LLI_ADDR, crypto_info->desc_dma);
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CRYPTO_WRITE(crypto_info, CRYPTO_HASH_CTL,
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(CRYPTO_HASH_ENABLE <<
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CRYPTO_WRITE_MASK_SHIFT) |
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CRYPTO_HASH_ENABLE);
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CRYPTO_WRITE(crypto_info, CRYPTO_DMA_CTL, 0x00010001); /* start */
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crypto_info->calc_ret = -1;
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crypto_info->done_cb = sha256_done_cb;
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crypto_info->cb_data = user_data;
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crypto_info->hash = devm_kzalloc(crypto_info->dev, 32, GFP_KERNEL);
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if (!crypto_info->hash)
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return -ENOMEM;
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return 0;
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}
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EXPORT_SYMBOL_GPL(rk_tb_sha256);
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static int __init rk_tb_crypto_probe(struct platform_device *pdev)
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{
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struct crypto_data *crypto_info;
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struct resource *res;
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int ret = 0;
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CRYPTO_TRACE();
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crypto_info = devm_kzalloc(&pdev->dev, sizeof(*crypto_info),
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GFP_KERNEL);
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if (!crypto_info)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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crypto_info->reg = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(crypto_info->reg)) {
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dev_err(crypto_info->dev,
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"devm_ioremap_resource crypto reg error.\n");
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ret = PTR_ERR(crypto_info->reg);
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goto exit;
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}
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crypto_info->dev = &pdev->dev;
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crypto_info->clks_num =
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devm_clk_bulk_get_all(&pdev->dev, &crypto_info->clk_bulks);
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if (crypto_info->clks_num < 0) {
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dev_err(&pdev->dev, "failed to get clks property\n");
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ret = -ENODEV;
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goto exit;
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}
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ret = clk_bulk_prepare_enable(crypto_info->clks_num, crypto_info->clk_bulks);
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if (ret) {
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dev_err(&pdev->dev, "failed to enable clks\n");
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goto exit;
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}
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crypto_info->irq = platform_get_irq(pdev, 0);
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if (crypto_info->irq < 0) {
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dev_err(crypto_info->dev,
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"control Interrupt is not available.\n");
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ret = crypto_info->irq;
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goto exit;
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}
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ret = devm_request_irq(&pdev->dev, crypto_info->irq,
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rk_tb_crypto_irq_handle, IRQF_SHARED,
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"rk-tb-crypto", pdev);
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if (ret) {
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dev_err(crypto_info->dev, "irq request failed.\n");
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goto exit;
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}
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crypto_info->desc = devm_kzalloc(&pdev->dev, sizeof(struct crypto_data),
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GFP_KERNEL | GFP_DMA);
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crypto_info->desc_dma = (dma_addr_t)virt_to_phys(crypto_info->desc);
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if (!crypto_info->desc) {
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dev_err(crypto_info->dev, "desc alloc failed.\n");
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ret = -ENOMEM;
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goto exit;
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}
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g_crypto_info = crypto_info;
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platform_set_drvdata(pdev, crypto_info);
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complete(&sha256_probe_complete);
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exit:
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return ret;
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}
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#ifdef CONFIG_OF
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static const struct of_device_id rk_tb_crypto_dt_match[] = {
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{ .compatible = "rockchip,rv1126-crypto" },
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{},
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};
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#endif
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static struct platform_driver rk_tb_crypto_driver = {
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.driver = {
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.name = "rockchip_thunder_boot_crypto",
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.of_match_table = rk_tb_crypto_dt_match,
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},
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};
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static int __init rk_tb_crypto_init(void)
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{
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struct device_node *node;
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CRYPTO_TRACE();
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node = of_find_matching_node(NULL, rk_tb_crypto_dt_match);
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if (node) {
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of_platform_device_create(node, NULL, NULL);
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of_node_put(node);
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return platform_driver_probe(&rk_tb_crypto_driver,
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rk_tb_crypto_probe);
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}
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CRYPTO_TRACE();
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return 0;
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}
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pure_initcall(rk_tb_crypto_init);
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