// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2022 Rockchip Electronics Co., Ltd.
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*/
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#include <linux/kernel.h>
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#include <linux/proc_fs.h>
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#include <linux/seq_file.h>
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#include <soc/rockchip/rockchip_performance.h>
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#include <../../kernel/sched/sched.h>
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static int perf_level = CONFIG_ROCKCHIP_PERFORMANCE_LEVEL;
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static cpumask_var_t cpul_mask, cpub_mask;
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static bool perf_init_done;
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static DEFINE_MUTEX(update_mutex);
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#ifdef CONFIG_UCLAMP_TASK
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static inline void set_uclamp_util_min_rt(unsigned int util)
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{
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sysctl_sched_uclamp_util_min_rt_default = util;
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static_branch_enable(&sched_uclamp_used);
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rockchip_perf_uclamp_sync_util_min_rt_default();
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}
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#else
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static inline void set_uclamp_util_min_rt(unsigned int util) { };
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#endif
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static void update_perf_level_locked(int level)
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{
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struct em_perf_domain *em;
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unsigned long target_cost, target_freq, max_freq;
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unsigned long scale_cpu0 = arch_scale_cpu_capacity(0);
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unsigned int uclamp_util_min_rt = scale_cpu0 * 2 / 3;
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int i;
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if (perf_init_done && perf_level == level)
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return;
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perf_level = level;
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if (level == 0) {
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set_uclamp_util_min_rt(0);
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return;
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}
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if ((level == 1) || (level == 2)) {
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set_uclamp_util_min_rt(SCHED_CAPACITY_SCALE);
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return;
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}
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/* find a better efficient frequency and consider performance */
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em = em_cpu_get(0);
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if (em) {
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target_cost = em->table[0].cost + (em->table[0].cost >> 2);
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for (i = 1; i < em->nr_perf_states; i++) {
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if (em->table[i].cost >= target_cost)
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break;
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}
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target_freq = em->table[i-1].frequency;
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max_freq = em->table[em->nr_perf_states-1].frequency;
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uclamp_util_min_rt = scale_cpu0 * target_freq / max_freq;
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}
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/* schedutil will reserve 20% util, and we need more 5% for debounce */
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uclamp_util_min_rt = uclamp_util_min_rt * 3 / 4;
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set_uclamp_util_min_rt(uclamp_util_min_rt);
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}
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static void update_perf_level(int level)
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{
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mutex_lock(&update_mutex);
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update_perf_level_locked(level);
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mutex_unlock(&update_mutex);
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}
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static int param_set_level(const char *buf, const struct kernel_param *kp)
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{
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int ret, level;
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ret = kstrtoint(buf, 10, &level);
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if (ret || (level < 0) || (level > 2))
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return -EINVAL;
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if (!perf_init_done)
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return 0;
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update_perf_level(level);
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return 0;
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}
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static const struct kernel_param_ops level_param_ops = {
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.set = param_set_level,
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.get = param_get_int,
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};
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module_param_cb(level, &level_param_ops, &perf_level, 0644);
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static __init int rockchip_perf_init(void)
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{
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int cpu;
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int cpub_min_cap = SCHED_CAPACITY_SCALE - (SCHED_CAPACITY_SCALE >> 3);
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if (!zalloc_cpumask_var(&cpul_mask, GFP_KERNEL))
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return -ENOMEM;
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if (!zalloc_cpumask_var(&cpub_mask, GFP_KERNEL))
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return -ENOMEM;
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for_each_possible_cpu(cpu) {
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if (arch_scale_cpu_capacity(cpu) > cpub_min_cap)
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cpumask_set_cpu(cpu, cpub_mask);
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else
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cpumask_set_cpu(cpu, cpul_mask);
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}
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update_perf_level(perf_level);
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perf_init_done = true;
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return 0;
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}
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late_initcall_sync(rockchip_perf_init);
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int rockchip_perf_get_level(void)
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{
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return perf_level;
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}
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struct cpumask *rockchip_perf_get_cpul_mask(void)
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{
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if (static_branch_unlikely(&sched_asym_cpucapacity))
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return cpul_mask;
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return NULL;
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}
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struct cpumask *rockchip_perf_get_cpub_mask(void)
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{
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if (static_branch_unlikely(&sched_asym_cpucapacity))
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return cpub_mask;
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return NULL;
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}
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#ifdef CONFIG_SMP
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int rockchip_perf_select_rt_cpu(int prev_cpu, struct cpumask *lowest_mask)
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{
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struct cpumask target_mask;
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int cpu = nr_cpu_ids;
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if (!perf_init_done)
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return prev_cpu;
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if (static_branch_unlikely(&sched_asym_cpucapacity)) {
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if (perf_level == 0)
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cpumask_and(&target_mask, lowest_mask, cpul_mask);
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if (perf_level == 2)
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cpumask_and(&target_mask, lowest_mask, cpub_mask);
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if (cpumask_test_cpu(prev_cpu, &target_mask))
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return prev_cpu;
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cpu = cpumask_first(&target_mask);
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if (cpu < nr_cpu_ids)
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return cpu;
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}
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return prev_cpu;
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}
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bool rockchip_perf_misfit_rt(int cpu)
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{
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if (!perf_init_done)
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return false;
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if (static_branch_unlikely(&sched_asym_cpucapacity)) {
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if ((perf_level == 0) && cpumask_test_cpu(cpu, cpub_mask))
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return true;
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if ((perf_level == 2) && cpumask_test_cpu(cpu, cpul_mask))
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return true;
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}
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return false;
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}
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#endif /* CONFIG_SMP */
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