/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright © 2014-2017 Broadcom
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include "pm.h"
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.text
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.align 3
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#define AON_CTRL_REG r10
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#define DDR_PHY_STATUS_REG r11
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/*
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* r0: AON_CTRL base address
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* r1: DDRY PHY PLL status register address
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*/
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ENTRY(brcmstb_pm_do_s2)
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stmfd sp!, {r4-r11, lr}
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mov AON_CTRL_REG, r0
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mov DDR_PHY_STATUS_REG, r1
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/* Flush memory transactions */
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dsb
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/* Cache DDR_PHY_STATUS_REG translation */
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ldr r0, [DDR_PHY_STATUS_REG]
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/* power down request */
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ldr r0, =PM_S2_COMMAND
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ldr r1, =0
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str r1, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
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ldr r1, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
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str r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
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ldr r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
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/* Wait for interrupt */
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wfi
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nop
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/* Bring MEMC back up */
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1: ldr r0, [DDR_PHY_STATUS_REG]
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ands r0, #1
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beq 1b
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/* Power-up handshake */
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ldr r0, =1
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str r0, [AON_CTRL_REG, #AON_CTRL_HOST_MISC_CMDS]
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ldr r0, [AON_CTRL_REG, #AON_CTRL_HOST_MISC_CMDS]
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ldr r0, =0
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str r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
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ldr r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
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/* Return to caller */
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ldr r0, =0
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ldmfd sp!, {r4-r11, pc}
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ENDPROC(brcmstb_pm_do_s2)
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/* Place literal pool here */
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.ltorg
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ENTRY(brcmstb_pm_do_s2_sz)
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.word . - brcmstb_pm_do_s2
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