/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Definitions for Broadcom STB power management / Always ON (AON) block
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*
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* Copyright © 2016-2017 Broadcom
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*/
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#ifndef __BRCMSTB_PM_H__
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#define __BRCMSTB_PM_H__
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#define AON_CTRL_RESET_CTRL 0x00
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#define AON_CTRL_PM_CTRL 0x04
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#define AON_CTRL_PM_STATUS 0x08
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#define AON_CTRL_PM_CPU_WAIT_COUNT 0x10
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#define AON_CTRL_PM_INITIATE 0x88
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#define AON_CTRL_HOST_MISC_CMDS 0x8c
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#define AON_CTRL_SYSTEM_DATA_RAM_OFS 0x200
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/* MIPS PM constants */
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/* MEMC0 offsets */
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#define DDR40_PHY_CONTROL_REGS_0_PLL_STATUS 0x10
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#define DDR40_PHY_CONTROL_REGS_0_STANDBY_CTRL 0xa4
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/* TIMER offsets */
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#define TIMER_TIMER1_CTRL 0x0c
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#define TIMER_TIMER1_STAT 0x1c
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/* TIMER defines */
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#define RESET_TIMER 0x0
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#define START_TIMER 0xbfffffff
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#define TIMER_MASK 0x3fffffff
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/* PM_CTRL bitfield (Method #0) */
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#define PM_FAST_PWRDOWN (1 << 6)
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#define PM_WARM_BOOT (1 << 5)
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#define PM_DEEP_STANDBY (1 << 4)
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#define PM_CPU_PWR (1 << 3)
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#define PM_USE_CPU_RDY (1 << 2)
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#define PM_PLL_PWRDOWN (1 << 1)
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#define PM_PWR_DOWN (1 << 0)
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/* PM_CTRL bitfield (Method #1) */
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#define PM_DPHY_STANDBY_CLEAR (1 << 20)
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#define PM_MIN_S3_WIDTH_TIMER_BYPASS (1 << 7)
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#define PM_S2_COMMAND (PM_PLL_PWRDOWN | PM_USE_CPU_RDY | PM_PWR_DOWN)
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/* Method 0 bitmasks */
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#define PM_COLD_CONFIG (PM_PLL_PWRDOWN | PM_DEEP_STANDBY)
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#define PM_WARM_CONFIG (PM_COLD_CONFIG | PM_USE_CPU_RDY | PM_WARM_BOOT)
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/* Method 1 bitmask */
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#define M1_PM_WARM_CONFIG (PM_DPHY_STANDBY_CLEAR | \
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PM_MIN_S3_WIDTH_TIMER_BYPASS | \
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PM_WARM_BOOT | PM_DEEP_STANDBY | \
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PM_PLL_PWRDOWN | PM_PWR_DOWN)
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#define M1_PM_COLD_CONFIG (PM_DPHY_STANDBY_CLEAR | \
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PM_MIN_S3_WIDTH_TIMER_BYPASS | \
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PM_DEEP_STANDBY | \
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PM_PLL_PWRDOWN | PM_PWR_DOWN)
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#ifndef __ASSEMBLY__
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#ifndef CONFIG_MIPS
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extern const unsigned long brcmstb_pm_do_s2_sz;
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extern asmlinkage int brcmstb_pm_do_s2(void __iomem *aon_ctrl_base,
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void __iomem *ddr_phy_pll_status);
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#else
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/* s2 asm */
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extern asmlinkage int brcm_pm_do_s2(u32 *s2_params);
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/* s3 asm */
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extern asmlinkage int brcm_pm_do_s3(void __iomem *aon_ctrl_base,
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int dcache_linesz);
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extern int s3_reentry;
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#endif /* CONFIG_MIPS */
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#endif
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#endif /* __BRCMSTB_PM_H__ */
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