/*
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* Copyright 2014 Cisco Systems, Inc. All rights reserved.
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*
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* This program is free software; you may redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef _SNIC_IO_H
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#define _SNIC_IO_H
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#define SNIC_DFLT_SG_DESC_CNT 32 /* Default descriptors for sgl */
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#define SNIC_MAX_SG_DESC_CNT 60 /* Max descriptor for sgl */
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#define SNIC_SG_DESC_ALIGN 16 /* Descriptor address alignment */
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/* SG descriptor for snic */
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struct snic_sg_desc {
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__le64 addr;
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__le32 len;
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u32 _resvd;
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};
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struct snic_dflt_sgl {
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struct snic_sg_desc sg_desc[SNIC_DFLT_SG_DESC_CNT];
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};
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struct snic_max_sgl {
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struct snic_sg_desc sg_desc[SNIC_MAX_SG_DESC_CNT];
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};
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enum snic_req_cache_type {
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SNIC_REQ_CACHE_DFLT_SGL = 0, /* cache with default size sgl */
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SNIC_REQ_CACHE_MAX_SGL, /* cache with max size sgl */
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SNIC_REQ_TM_CACHE, /* cache for task mgmt reqs contains
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snic_host_req objects only*/
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SNIC_REQ_MAX_CACHES /* number of sgl caches */
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};
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/* Per IO internal state */
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struct snic_internal_io_state {
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char *rqi;
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u64 flags;
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u32 state;
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u32 abts_status; /* Abort completion status */
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u32 lr_status; /* device reset completion status */
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};
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/* IO state machine */
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enum snic_ioreq_state {
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SNIC_IOREQ_NOT_INITED = 0,
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SNIC_IOREQ_PENDING,
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SNIC_IOREQ_ABTS_PENDING,
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SNIC_IOREQ_ABTS_COMPLETE,
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SNIC_IOREQ_LR_PENDING,
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SNIC_IOREQ_LR_COMPLETE,
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SNIC_IOREQ_COMPLETE,
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};
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struct snic;
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struct snic_host_req;
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/*
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* snic_req_info : Contains info about IO, one per scsi command.
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* Notes: Make sure that the structure is aligned to 16 B
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* this helps in easy access to snic_req_info from snic_host_req
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*/
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struct snic_req_info {
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struct list_head list;
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struct snic_host_req *req;
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u64 start_time; /* start time in jiffies */
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u16 rq_pool_type; /* noticion of request pool type */
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u16 req_len; /* buf len passing to fw (req + sgl)*/
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u32 tgt_id;
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u32 tm_tag;
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u8 io_cmpl:1; /* sets to 1 when fw completes IO */
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u8 resvd[3];
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struct scsi_cmnd *sc; /* Associated scsi cmd */
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struct snic *snic; /* Associated snic */
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ulong sge_va; /* Pointer to Resp Buffer */
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u64 snsbuf_va;
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struct snic_host_req *abort_req;
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struct completion *abts_done;
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struct snic_host_req *dr_req;
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struct completion *dr_done;
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};
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#define rqi_to_req(rqi) \
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((struct snic_host_req *) (((struct snic_req_info *)rqi)->req))
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#define req_to_rqi(req) \
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((struct snic_req_info *) (((struct snic_host_req *)req)->hdr.init_ctx))
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#define req_to_sgl(req) \
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((struct snic_sg_desc *) (((struct snic_host_req *)req)+1))
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struct snic_req_info *
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snic_req_init(struct snic *, int sg_cnt);
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void snic_req_free(struct snic *, struct snic_req_info *);
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void snic_calc_io_process_time(struct snic *, struct snic_req_info *);
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void snic_pci_unmap_rsp_buf(struct snic *, struct snic_req_info *);
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struct snic_host_req *
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snic_abort_req_init(struct snic *, struct snic_req_info *);
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struct snic_host_req *
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snic_dr_req_init(struct snic *, struct snic_req_info *);
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#endif /* _SNIC_IO_H */
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