/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* mac53c94.h: definitions for the driver for the 53c94 SCSI bus adaptor
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* found on Power Macintosh computers, controlling the external SCSI chain.
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*
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* Copyright (C) 1996 Paul Mackerras.
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*/
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#ifndef _MAC53C94_H
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#define _MAC53C94_H
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/*
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* Registers in the 53C94 controller.
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*/
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struct mac53c94_regs {
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unsigned char count_lo;
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char pad0[15];
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unsigned char count_mid;
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char pad1[15];
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unsigned char fifo;
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char pad2[15];
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unsigned char command;
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char pad3[15];
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unsigned char status;
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char pad4[15];
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unsigned char interrupt;
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char pad5[15];
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unsigned char seqstep;
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char pad6[15];
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unsigned char flags;
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char pad7[15];
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unsigned char config1;
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char pad8[15];
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unsigned char clk_factor;
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char pad9[15];
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unsigned char test;
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char pad10[15];
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unsigned char config2;
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char pad11[15];
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unsigned char config3;
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char pad12[15];
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unsigned char config4;
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char pad13[15];
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unsigned char count_hi;
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char pad14[15];
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unsigned char fifo_res;
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char pad15[15];
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};
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/*
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* Alternate functions for some registers.
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*/
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#define dest_id status
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#define sel_timeout interrupt
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#define sync_period seqstep
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#define sync_offset flags
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/*
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* Bits in command register.
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*/
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#define CMD_DMA_MODE 0x80
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#define CMD_MODE_MASK 0x70
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#define CMD_MODE_INIT 0x10
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#define CMD_MODE_TARG 0x20
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#define CMD_MODE_DISC 0x40
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#define CMD_NOP 0
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#define CMD_FLUSH 1
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#define CMD_RESET 2
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#define CMD_SCSI_RESET 3
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#define CMD_XFER_DATA 0x10
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#define CMD_I_COMPLETE 0x11
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#define CMD_ACCEPT_MSG 0x12
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#define CMD_XFER_PAD 0x18
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#define CMD_SET_ATN 0x1a
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#define CMD_CLR_ATN 0x1b
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#define CMD_SEND_MSG 0x20
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#define CMD_SEND_STATUS 0x21
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#define CMD_SEND_DATA 0x22
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#define CMD_DISC_SEQ 0x23
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#define CMD_TERMINATE 0x24
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#define CMD_T_COMPLETE 0x25
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#define CMD_DISCONNECT 0x27
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#define CMD_RECV_MSG 0x28
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#define CMD_RECV_CDB 0x29
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#define CMD_RECV_DATA 0x2a
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#define CMD_RECV_CMD 0x2b
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#define CMD_ABORT_DMA 0x04
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#define CMD_RESELECT 0x40
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#define CMD_SELECT 0x41
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#define CMD_SELECT_ATN 0x42
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#define CMD_SELATN_STOP 0x43
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#define CMD_ENABLE_SEL 0x44
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#define CMD_DISABLE_SEL 0x45
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#define CMD_SEL_ATN3 0x46
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#define CMD_RESEL_ATN3 0x47
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/*
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* Bits in status register.
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*/
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#define STAT_IRQ 0x80
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#define STAT_ERROR 0x40
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#define STAT_PARITY 0x20
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#define STAT_TC_ZERO 0x10
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#define STAT_DONE 0x08
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#define STAT_PHASE 0x07
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#define STAT_MSG 0x04
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#define STAT_CD 0x02
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#define STAT_IO 0x01
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/*
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* Bits in interrupt register.
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*/
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#define INTR_RESET 0x80 /* SCSI bus was reset */
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#define INTR_ILL_CMD 0x40 /* illegal command */
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#define INTR_DISCONNECT 0x20 /* we got disconnected */
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#define INTR_BUS_SERV 0x10 /* bus service requested */
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#define INTR_DONE 0x08 /* function completed */
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#define INTR_RESELECTED 0x04 /* we were reselected */
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#define INTR_SEL_ATN 0x02 /* we were selected, ATN asserted */
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#define INTR_SELECT 0x01 /* we were selected, ATN negated */
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/*
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* Encoding for the select timeout.
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*/
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#define TIMO_VAL(x) ((x) * 5000 / 7682)
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/*
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* Bits in sequence step register.
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*/
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#define SS_MASK 7
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#define SS_ARB_SEL 0 /* Selection & arbitration complete */
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#define SS_MSG_SENT 1 /* One message byte sent */
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#define SS_NOT_CMD 2 /* Not in command phase */
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#define SS_PHASE_CHG 3 /* Early phase change, cmd bytes lost */
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#define SS_DONE 4 /* Command was sent OK */
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/*
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* Encoding for sync transfer period.
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*/
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#define SYNCP_MASK 0x1f
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#define SYNCP_MIN 4
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#define SYNCP_MAX 31
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/*
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* Bits in flags register.
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*/
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#define FLAGS_FIFO_LEV 0x1f
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#define FLAGS_SEQ_STEP 0xe0
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/*
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* Encoding for sync offset.
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*/
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#define SYNCO_MASK 0x0f
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#define SYNCO_ASS_CTRL 0x30 /* REQ/ACK assertion control */
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#define SYNCO_NEG_CTRL 0xc0 /* REQ/ACK negation control */
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/*
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* Bits in config1 register.
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*/
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#define CF1_SLOW_CABLE 0x80 /* Slow cable mode */
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#define CF1_NO_RES_REP 0x40 /* Disable SCSI reset reports */
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#define CF1_PAR_TEST 0x20 /* Parity test mode enable */
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#define CF1_PAR_ENABLE 0x10 /* Enable parity checks */
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#define CF1_TEST 0x08 /* Chip tests */
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#define CF1_MY_ID 0x07 /* Controller's address on bus */
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/*
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* Encoding for clk_factor register.
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*/
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#define CLKF_MASK 7
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#define CLKF_VAL(freq) ((((freq) + 4999999) / 5000000) & CLKF_MASK)
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/*
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* Bits in test mode register.
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*/
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#define TEST_TARGET 1 /* target test mode */
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#define TEST_INITIATOR 2 /* initiator test mode */
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#define TEST_TRISTATE 4 /* tristate (hi-z) test mode */
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/*
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* Bits in config2 register.
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*/
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#define CF2_RFB 0x80
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#define CF2_FEATURE_EN 0x40 /* enable features / phase latch */
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#define CF2_BYTECTRL 0x20
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#define CF2_DREQ_HIZ 0x10
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#define CF2_SCSI2 0x08
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#define CF2_PAR_ABORT 0x04 /* bad parity target abort */
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#define CF2_REG_PARERR 0x02 /* register parity error */
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#define CF2_DMA_PARERR 0x01 /* DMA parity error */
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/*
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* Bits in the config3 register.
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*/
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#define CF3_ID_MSG_CHK 0x80
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#define CF3_3B_MSGS 0x40
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#define CF3_CDB10 0x20
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#define CF3_FASTSCSI 0x10 /* enable fast SCSI support */
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#define CF3_FASTCLOCK 0x08
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#define CF3_SAVERESID 0x04
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#define CF3_ALT_DMA 0x02
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#define CF3_THRESH_8 0x01
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/*
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* Bits in the config4 register.
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*/
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#define CF4_EAN 0x04
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#define CF4_TEST 0x02
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#define CF4_BBTE 0x01
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#endif /* _MAC53C94_H */
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