/*
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* Au1xxx counter0 (aka Time-Of-Year counter) RTC interface driver.
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*
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* Copyright (C) 2008 Manuel Lauss <mano@roarinelk.homelinux.net>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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/* All current Au1xxx SoCs have 2 counters fed by an external 32.768 kHz
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* crystal. Counter 0, which keeps counting during sleep/powerdown, is
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* used to count seconds since the beginning of the unix epoch.
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*
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* The counters must be configured and enabled by bootloader/board code;
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* no checks as to whether they really get a proper 32.768kHz clock are
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* made as this would take far too long.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/rtc.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <asm/mach-au1x00/au1000.h>
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/* 32kHz clock enabled and detected */
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#define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S)
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static int au1xtoy_rtc_read_time(struct device *dev, struct rtc_time *tm)
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{
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unsigned long t;
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t = alchemy_rdsys(AU1000_SYS_TOYREAD);
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rtc_time64_to_tm(t, tm);
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return 0;
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}
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static int au1xtoy_rtc_set_time(struct device *dev, struct rtc_time *tm)
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{
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unsigned long t;
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t = rtc_tm_to_time64(tm);
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alchemy_wrsys(t, AU1000_SYS_TOYWRITE);
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/* wait for the pending register write to succeed. This can
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* take up to 6 seconds...
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*/
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while (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C0S)
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msleep(1);
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return 0;
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}
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static const struct rtc_class_ops au1xtoy_rtc_ops = {
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.read_time = au1xtoy_rtc_read_time,
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.set_time = au1xtoy_rtc_set_time,
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};
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static int au1xtoy_rtc_probe(struct platform_device *pdev)
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{
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struct rtc_device *rtcdev;
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unsigned long t;
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t = alchemy_rdsys(AU1000_SYS_CNTRCTRL);
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if (!(t & CNTR_OK)) {
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dev_err(&pdev->dev, "counters not working; aborting.\n");
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return -ENODEV;
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}
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/* set counter0 tickrate to 1Hz if necessary */
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if (alchemy_rdsys(AU1000_SYS_TOYTRIM) != 32767) {
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/* wait until hardware gives access to TRIM register */
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t = 0x00100000;
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while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_T0S) && --t)
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msleep(1);
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if (!t) {
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/* timed out waiting for register access; assume
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* counters are unusable.
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*/
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dev_err(&pdev->dev, "timeout waiting for access\n");
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return -ETIMEDOUT;
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}
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/* set 1Hz TOY tick rate */
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alchemy_wrsys(32767, AU1000_SYS_TOYTRIM);
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}
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/* wait until the hardware allows writes to the counter reg */
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while (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C0S)
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msleep(1);
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rtcdev = devm_rtc_allocate_device(&pdev->dev);
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if (IS_ERR(rtcdev))
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return PTR_ERR(rtcdev);
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rtcdev->ops = &au1xtoy_rtc_ops;
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rtcdev->range_max = U32_MAX;
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platform_set_drvdata(pdev, rtcdev);
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return rtc_register_device(rtcdev);
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}
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static struct platform_driver au1xrtc_driver = {
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.driver = {
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.name = "rtc-au1xxx",
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},
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};
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module_platform_driver_probe(au1xrtc_driver, au1xtoy_rtc_probe);
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MODULE_DESCRIPTION("Au1xxx TOY-counter-based RTC driver");
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MODULE_AUTHOR("Manuel Lauss <manuel.lauss@gmail.com>");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:rtc-au1xxx");
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