/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019, Mellanox Technologies. All rights reserved.
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*/
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#ifndef __MLXBF_TMFIFO_REGS_H__
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#define __MLXBF_TMFIFO_REGS_H__
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#include <linux/types.h>
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#include <linux/bits.h>
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#define MLXBF_TMFIFO_TX_DATA 0x00
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#define MLXBF_TMFIFO_TX_STS 0x08
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#define MLXBF_TMFIFO_TX_STS__LENGTH 0x0001
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#define MLXBF_TMFIFO_TX_STS__COUNT_SHIFT 0
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#define MLXBF_TMFIFO_TX_STS__COUNT_WIDTH 9
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#define MLXBF_TMFIFO_TX_STS__COUNT_RESET_VAL 0
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#define MLXBF_TMFIFO_TX_STS__COUNT_RMASK GENMASK_ULL(8, 0)
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#define MLXBF_TMFIFO_TX_STS__COUNT_MASK GENMASK_ULL(8, 0)
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#define MLXBF_TMFIFO_TX_CTL 0x10
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#define MLXBF_TMFIFO_TX_CTL__LENGTH 0x0001
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#define MLXBF_TMFIFO_TX_CTL__LWM_SHIFT 0
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#define MLXBF_TMFIFO_TX_CTL__LWM_WIDTH 8
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#define MLXBF_TMFIFO_TX_CTL__LWM_RESET_VAL 128
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#define MLXBF_TMFIFO_TX_CTL__LWM_RMASK GENMASK_ULL(7, 0)
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#define MLXBF_TMFIFO_TX_CTL__LWM_MASK GENMASK_ULL(7, 0)
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#define MLXBF_TMFIFO_TX_CTL__HWM_SHIFT 8
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#define MLXBF_TMFIFO_TX_CTL__HWM_WIDTH 8
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#define MLXBF_TMFIFO_TX_CTL__HWM_RESET_VAL 128
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#define MLXBF_TMFIFO_TX_CTL__HWM_RMASK GENMASK_ULL(7, 0)
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#define MLXBF_TMFIFO_TX_CTL__HWM_MASK GENMASK_ULL(15, 8)
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#define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_SHIFT 32
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#define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_WIDTH 9
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#define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_RESET_VAL 256
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#define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_RMASK GENMASK_ULL(8, 0)
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#define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_MASK GENMASK_ULL(40, 32)
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#define MLXBF_TMFIFO_RX_DATA 0x00
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#define MLXBF_TMFIFO_RX_STS 0x08
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#define MLXBF_TMFIFO_RX_STS__LENGTH 0x0001
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#define MLXBF_TMFIFO_RX_STS__COUNT_SHIFT 0
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#define MLXBF_TMFIFO_RX_STS__COUNT_WIDTH 9
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#define MLXBF_TMFIFO_RX_STS__COUNT_RESET_VAL 0
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#define MLXBF_TMFIFO_RX_STS__COUNT_RMASK GENMASK_ULL(8, 0)
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#define MLXBF_TMFIFO_RX_STS__COUNT_MASK GENMASK_ULL(8, 0)
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#define MLXBF_TMFIFO_RX_CTL 0x10
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#define MLXBF_TMFIFO_RX_CTL__LENGTH 0x0001
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#define MLXBF_TMFIFO_RX_CTL__LWM_SHIFT 0
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#define MLXBF_TMFIFO_RX_CTL__LWM_WIDTH 8
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#define MLXBF_TMFIFO_RX_CTL__LWM_RESET_VAL 128
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#define MLXBF_TMFIFO_RX_CTL__LWM_RMASK GENMASK_ULL(7, 0)
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#define MLXBF_TMFIFO_RX_CTL__LWM_MASK GENMASK_ULL(7, 0)
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#define MLXBF_TMFIFO_RX_CTL__HWM_SHIFT 8
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#define MLXBF_TMFIFO_RX_CTL__HWM_WIDTH 8
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#define MLXBF_TMFIFO_RX_CTL__HWM_RESET_VAL 128
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#define MLXBF_TMFIFO_RX_CTL__HWM_RMASK GENMASK_ULL(7, 0)
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#define MLXBF_TMFIFO_RX_CTL__HWM_MASK GENMASK_ULL(15, 8)
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#define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_SHIFT 32
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#define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_WIDTH 9
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#define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_RESET_VAL 256
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#define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_RMASK GENMASK_ULL(8, 0)
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#define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_MASK GENMASK_ULL(40, 32)
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#endif /* !defined(__MLXBF_TMFIFO_REGS_H__) */
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