// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
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*
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* Author: Wyon Bi <bivvy.bi@rock-chips.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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#include <linux/phy/phy.h>
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#define EDP_PHY_GRF_CON0 0x0000
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#define EDP_PHY_TX_IDLE GENMASK(11, 8)
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#define EDP_PHY_TX_PD GENMASK(7, 4)
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#define EDP_PHY_IDDQ_EN BIT(1)
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#define EDP_PHY_PD_PLL BIT(0)
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#define EDP_PHY_GRF_CON1 0x0004
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#define EDP_PHY_PLL_DIV GENMASK(14, 0)
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#define EDP_PHY_GRF_CON2 0x0008
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#define EDP_PHY_TX_RTERM GENMASK(10, 8)
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#define EDP_PHY_RATE GENMASK(5, 4)
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#define EDP_PHY_REF_DIV GENMASK(3, 0)
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#define EDP_PHY_GRF_CON3 0x000c
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#define EDP_PHY_TX3_EMP GENMASK(15, 12)
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#define EDP_PHY_TX2_EMP GENMASK(11, 8)
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#define EDP_PHY_TX1_EMP GENMASK(7, 4)
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#define EDP_PHY_TX0_EMP GENMASK(3, 0)
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#define EDP_PHY_GRF_CON4 0x0010
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#define EDP_PHY_TX3_AMP GENMASK(14, 12)
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#define EDP_PHY_TX2_AMP GENMASK(10, 8)
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#define EDP_PHY_TX1_AMP GENMASK(6, 4)
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#define EDP_PHY_TX0_AMP GENMASK(2, 0)
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#define EDP_PHY_GRF_CON5 0x0014
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#define EDP_PHY_TX_MODE GENMASK(9, 8)
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#define EDP_PHY_TX3_AMP_SCALE GENMASK(7, 6)
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#define EDP_PHY_TX2_AMP_SCALE GENMASK(5, 4)
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#define EDP_PHY_TX1_AMP_SCALE GENMASK(3, 2)
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#define EDP_PHY_TX0_AMP_SCALE GENMASK(1, 0)
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#define EDP_PHY_GRF_CON6 0x0018
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#define EDP_PHY_SSC_DEPTH GENMASK(15, 12)
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#define EDP_PHY_SSC_EN BIT(11)
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#define EDP_PHY_SSC_CNT GENMASK(9, 0)
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#define EDP_PHY_GRF_CON7 0x001c
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#define EDP_PHY_GRF_CON8 0x0020
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#define EDP_PHY_PLL_CTL_H GENMASK(15, 0)
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#define EDP_PHY_GRF_CON9 0x0024
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#define EDP_PHY_TX_CTL GENMASK(15, 0)
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#define EDP_PHY_GRF_CON10 0x0028
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#define EDP_PHY_AUX_RCV_PD_SEL BIT(5)
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#define EDP_PHY_AUX_DRV_PD_SEL BIT(4)
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#define EDP_PHY_AUX_IDLE BIT(2)
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#define EDP_PHY_AUX_RCV_PD BIT(1)
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#define EDP_PHY_AUX_DRV_PD BIT(0)
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#define EDP_PHY_GRF_CON11 0x002c
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#define EDP_PHY_AUX_RCV_VCM GENMASK(14, 12)
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#define EDP_PHY_AUX_MODE GENMASK(11, 10)
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#define EDP_PHY_AUX_AMP_SCALE GENMASK(9, 8)
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#define EDP_PHY_AUX_AMP GENMASK(6, 4)
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#define EDP_PHY_AUX_RTERM GENMASK(2, 0)
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#define EDP_PHY_GRF_STATUS0 0x0030
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#define PLL_RDY BIT(0)
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#define EDP_PHY_GRF_STATUS1 0x0034
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struct rockchip_edp_phy {
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struct regmap *grf;
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struct device *dev;
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struct clk *refclk;
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};
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static inline int rockchip_grf_write(struct regmap *grf, unsigned int reg,
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unsigned int mask, unsigned int val)
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{
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return regmap_write(grf, reg, (mask << 16) | (val & mask));
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}
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static struct {
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int amp;
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int amp_scale;
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int emp;
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} vp[4][4] = {
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{ {0x1, 0x1, 0x0}, {0x2, 0x1, 0x4}, {0x3, 0x1, 0x8}, {0x4, 0x1, 0xd} },
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{ {0x3, 0x1, 0x0}, {0x5, 0x1, 0x7}, {0x6, 0x1, 0x6}, { -1, -1, -1} },
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{ {0x5, 0x1, 0x0}, {0x7, 0x1, 0x4}, { -1, -1, -1}, { -1, -1, -1} },
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{ {0x7, 0x1, 0x0}, { -1, -1, -1}, { -1, -1, -1}, { -1, -1, -1} },
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};
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static void rockchip_edp_phy_set_voltage(struct rockchip_edp_phy *edpphy,
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struct phy_configure_opts_dp *dp,
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u8 lane)
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{
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u32 amp, amp_scale, emp;
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amp = vp[dp->voltage[lane]][dp->pre[lane]].amp;
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amp_scale = vp[dp->voltage[lane]][dp->pre[lane]].amp_scale;
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emp = vp[dp->voltage[lane]][dp->pre[lane]].emp;
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switch (lane) {
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case 0:
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON3,
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EDP_PHY_TX0_EMP,
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FIELD_PREP(EDP_PHY_TX0_EMP, emp));
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON4,
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EDP_PHY_TX0_AMP,
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FIELD_PREP(EDP_PHY_TX0_AMP, amp));
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5,
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EDP_PHY_TX0_AMP_SCALE,
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FIELD_PREP(EDP_PHY_TX0_AMP_SCALE, amp_scale));
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break;
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case 1:
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON3,
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EDP_PHY_TX1_EMP,
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FIELD_PREP(EDP_PHY_TX1_EMP, emp));
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON4,
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EDP_PHY_TX1_AMP,
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FIELD_PREP(EDP_PHY_TX1_AMP, amp));
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5,
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EDP_PHY_TX1_AMP_SCALE,
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FIELD_PREP(EDP_PHY_TX1_AMP_SCALE, amp_scale));
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break;
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case 2:
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON3,
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EDP_PHY_TX2_EMP,
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FIELD_PREP(EDP_PHY_TX2_EMP, emp));
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON4,
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EDP_PHY_TX2_AMP,
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FIELD_PREP(EDP_PHY_TX2_AMP, amp));
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5,
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EDP_PHY_TX2_AMP_SCALE,
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FIELD_PREP(EDP_PHY_TX2_AMP_SCALE, amp_scale));
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break;
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case 3:
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON3,
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EDP_PHY_TX3_EMP,
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FIELD_PREP(EDP_PHY_TX3_EMP, emp));
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON4,
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EDP_PHY_TX3_AMP,
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FIELD_PREP(EDP_PHY_TX3_AMP, amp));
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5,
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EDP_PHY_TX3_AMP_SCALE,
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FIELD_PREP(EDP_PHY_TX3_AMP_SCALE, amp_scale));
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break;
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}
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}
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static int rockchip_edp_phy_set_voltages(struct rockchip_edp_phy *edpphy,
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struct phy_configure_opts_dp *dp)
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{
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u8 lane;
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for (lane = 0; lane < dp->lanes; lane++)
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rockchip_edp_phy_set_voltage(edpphy, dp, lane);
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return 0;
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}
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static int rockchip_edp_phy_set_rate(struct rockchip_edp_phy *edpphy,
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struct phy_configure_opts_dp *dp)
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{
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u32 value;
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int ret;
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0,
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EDP_PHY_TX_IDLE | EDP_PHY_TX_PD,
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FIELD_PREP(EDP_PHY_TX_IDLE, 0xf) |
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FIELD_PREP(EDP_PHY_TX_PD, 0xf));
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usleep_range(100, 101);
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5, EDP_PHY_TX_MODE,
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FIELD_PREP(EDP_PHY_TX_MODE, 0x3));
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0, EDP_PHY_PD_PLL,
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FIELD_PREP(EDP_PHY_PD_PLL, 0x1));
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switch (dp->link_rate) {
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case 1620:
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON1,
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EDP_PHY_PLL_DIV,
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FIELD_PREP(EDP_PHY_PLL_DIV, 0x4380));
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON2,
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EDP_PHY_TX_RTERM | EDP_PHY_RATE | EDP_PHY_REF_DIV,
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FIELD_PREP(EDP_PHY_TX_RTERM, 0x1) |
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FIELD_PREP(EDP_PHY_RATE, 0x1) |
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FIELD_PREP(EDP_PHY_REF_DIV, 0x0));
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON8,
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EDP_PHY_PLL_CTL_H,
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FIELD_PREP(EDP_PHY_PLL_CTL_H, 0x0800));
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON9,
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EDP_PHY_TX_CTL,
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FIELD_PREP(EDP_PHY_TX_CTL, 0x0000));
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break;
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case 2700:
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON1,
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EDP_PHY_PLL_DIV,
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FIELD_PREP(EDP_PHY_PLL_DIV, 0x3840));
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON2,
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EDP_PHY_TX_RTERM | EDP_PHY_RATE | EDP_PHY_REF_DIV,
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FIELD_PREP(EDP_PHY_TX_RTERM, 0x1) |
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FIELD_PREP(EDP_PHY_RATE, 0x0) |
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FIELD_PREP(EDP_PHY_REF_DIV, 0x0));
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON8,
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EDP_PHY_PLL_CTL_H,
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FIELD_PREP(EDP_PHY_PLL_CTL_H, 0x0800));
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON9,
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EDP_PHY_TX_CTL,
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FIELD_PREP(EDP_PHY_TX_CTL, 0x0000));
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break;
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}
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if (dp->ssc)
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON6,
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EDP_PHY_SSC_DEPTH | EDP_PHY_SSC_EN | EDP_PHY_SSC_CNT,
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FIELD_PREP(EDP_PHY_SSC_DEPTH, 0x9) |
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FIELD_PREP(EDP_PHY_SSC_EN, 0x1) |
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FIELD_PREP(EDP_PHY_SSC_CNT, 0x17d));
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else
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON6,
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EDP_PHY_SSC_EN,
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FIELD_PREP(EDP_PHY_SSC_EN, 0x0));
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0, EDP_PHY_PD_PLL,
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FIELD_PREP(EDP_PHY_PD_PLL, 0));
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0, EDP_PHY_TX_PD,
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FIELD_PREP(EDP_PHY_TX_PD, ~GENMASK(dp->lanes - 1, 0)));
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ret = regmap_read_poll_timeout(edpphy->grf, EDP_PHY_GRF_STATUS0,
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value, value & PLL_RDY, 100, 1000);
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if (ret) {
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dev_err(edpphy->dev, "pll is not ready: %d\n", ret);
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return ret;
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}
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5, EDP_PHY_TX_MODE,
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FIELD_PREP(EDP_PHY_TX_MODE, 0x0));
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0, EDP_PHY_TX_IDLE,
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FIELD_PREP(EDP_PHY_TX_IDLE, ~GENMASK(dp->lanes - 1, 0)));
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return 0;
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}
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static int rockchip_edp_phy_verify_config(struct rockchip_edp_phy *edpphy,
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struct phy_configure_opts_dp *dp)
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{
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int i;
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/* If changing link rate was required, verify it's supported. */
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if (dp->set_rate) {
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switch (dp->link_rate) {
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case 1620:
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case 2700:
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/* valid bit rate */
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break;
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default:
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return -EINVAL;
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}
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}
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/* Verify lane count. */
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switch (dp->lanes) {
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case 1:
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case 2:
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case 4:
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/* valid lane count. */
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break;
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default:
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return -EINVAL;
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}
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/*
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* If changing voltages is required, check swing and pre-emphasis
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* levels, per-lane.
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*/
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if (dp->set_voltages) {
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/* Lane count verified previously. */
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for (i = 0; i < dp->lanes; i++) {
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if (dp->voltage[i] > 3 || dp->pre[i] > 3)
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return -EINVAL;
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/*
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* Sum of voltage swing and pre-emphasis levels cannot
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* exceed 3.
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*/
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if (dp->voltage[i] + dp->pre[i] > 3)
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return -EINVAL;
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}
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}
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return 0;
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}
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static int rockchip_edp_phy_configure(struct phy *phy,
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union phy_configure_opts *opts)
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{
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struct rockchip_edp_phy *edpphy = phy_get_drvdata(phy);
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int ret;
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ret = rockchip_edp_phy_verify_config(edpphy, &opts->dp);
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if (ret) {
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dev_err(edpphy->dev, "invalid params for phy configure\n");
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return ret;
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}
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if (opts->dp.set_rate) {
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ret = rockchip_edp_phy_set_rate(edpphy, &opts->dp);
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if (ret) {
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dev_err(edpphy->dev,
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"rockchip_edp_phy_set_rate failed\n");
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return ret;
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}
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}
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if (opts->dp.set_voltages) {
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ret = rockchip_edp_phy_set_voltages(edpphy, &opts->dp);
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if (ret) {
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dev_err(edpphy->dev,
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"rockchip_edp_phy_set_voltages failed\n");
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return ret;
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}
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}
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return 0;
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}
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static bool rockchip_edp_phy_enabled(struct rockchip_edp_phy *edpphy)
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{
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u32 val;
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regmap_read(edpphy->grf, EDP_PHY_GRF_STATUS0, &val);
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return FIELD_GET(PLL_RDY, val);
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}
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static int rockchip_edp_phy_power_on(struct phy *phy)
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{
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struct rockchip_edp_phy *edpphy = phy_get_drvdata(phy);
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clk_prepare_enable(edpphy->refclk);
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if (rockchip_edp_phy_enabled(edpphy))
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return 0;
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON10,
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EDP_PHY_AUX_RCV_PD | EDP_PHY_AUX_DRV_PD | EDP_PHY_AUX_IDLE,
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FIELD_PREP(EDP_PHY_AUX_RCV_PD, 0x1) |
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FIELD_PREP(EDP_PHY_AUX_DRV_PD, 0x1) |
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FIELD_PREP(EDP_PHY_AUX_IDLE, 0x1));
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0,
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EDP_PHY_TX_IDLE | EDP_PHY_TX_PD | EDP_PHY_PD_PLL,
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FIELD_PREP(EDP_PHY_TX_IDLE, 0xf) |
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FIELD_PREP(EDP_PHY_TX_PD, 0xf) |
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FIELD_PREP(EDP_PHY_PD_PLL, 0x1));
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usleep_range(100, 101);
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON11,
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EDP_PHY_AUX_RCV_VCM | EDP_PHY_AUX_MODE |
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EDP_PHY_AUX_AMP_SCALE | EDP_PHY_AUX_AMP |
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EDP_PHY_AUX_RTERM,
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FIELD_PREP(EDP_PHY_AUX_RCV_VCM, 0x4) |
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FIELD_PREP(EDP_PHY_AUX_MODE, 0x1) |
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FIELD_PREP(EDP_PHY_AUX_AMP_SCALE, 0x1) |
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FIELD_PREP(EDP_PHY_AUX_AMP, 0x3) |
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FIELD_PREP(EDP_PHY_AUX_RTERM, 0x1));
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON10,
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EDP_PHY_AUX_RCV_PD | EDP_PHY_AUX_DRV_PD,
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FIELD_PREP(EDP_PHY_AUX_RCV_PD, 0x0) |
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FIELD_PREP(EDP_PHY_AUX_DRV_PD, 0x0));
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usleep_range(100, 101);
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON10,
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EDP_PHY_AUX_IDLE,
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FIELD_PREP(EDP_PHY_AUX_IDLE, 0x0));
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usleep_range(10000, 11000);
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return 0;
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}
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static int rockchip_edp_phy_power_off(struct phy *phy)
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{
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struct rockchip_edp_phy *edpphy = phy_get_drvdata(phy);
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0,
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EDP_PHY_TX_IDLE | EDP_PHY_TX_PD,
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FIELD_PREP(EDP_PHY_TX_IDLE, 0xf) |
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FIELD_PREP(EDP_PHY_TX_PD, 0xf));
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usleep_range(100, 101);
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5, EDP_PHY_TX_MODE,
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FIELD_PREP(EDP_PHY_TX_MODE, 0x3));
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0, EDP_PHY_PD_PLL,
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FIELD_PREP(EDP_PHY_PD_PLL, 0x1));
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rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON10,
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EDP_PHY_AUX_RCV_PD | EDP_PHY_AUX_DRV_PD | EDP_PHY_AUX_IDLE,
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FIELD_PREP(EDP_PHY_AUX_RCV_PD, 0x1) |
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FIELD_PREP(EDP_PHY_AUX_DRV_PD, 0x1) |
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FIELD_PREP(EDP_PHY_AUX_IDLE, 0x1));
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clk_disable_unprepare(edpphy->refclk);
|
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return 0;
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}
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static const struct phy_ops rockchip_edp_phy_ops = {
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.power_on = rockchip_edp_phy_power_on,
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.power_off = rockchip_edp_phy_power_off,
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.configure = rockchip_edp_phy_configure,
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.owner = THIS_MODULE,
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};
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static int rockchip_edp_phy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct rockchip_edp_phy *edpphy;
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struct phy *phy;
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struct phy_provider *phy_provider;
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int ret;
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edpphy = devm_kzalloc(dev, sizeof(*edpphy), GFP_KERNEL);
|
if (!edpphy)
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return -ENOMEM;
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edpphy->dev = dev;
|
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edpphy->grf = syscon_node_to_regmap(dev->parent->of_node);
|
if (IS_ERR(edpphy->grf)) {
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ret = PTR_ERR(edpphy->grf);
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dev_err(dev, "failed to get grf: %d\n", ret);
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return ret;
|
}
|
|
edpphy->refclk = devm_clk_get(dev, "refclk");
|
if (IS_ERR(edpphy->refclk)) {
|
ret = PTR_ERR(edpphy->refclk);
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dev_err(dev, "failed to get refclk: %d\n", ret);
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return ret;
|
}
|
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phy = devm_phy_create(dev, NULL, &rockchip_edp_phy_ops);
|
if (IS_ERR(phy)) {
|
ret = PTR_ERR(phy);
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dev_err(dev, "failed to create PHY: %d\n", ret);
|
return ret;
|
}
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phy_set_drvdata(phy, edpphy);
|
|
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
if (IS_ERR(phy_provider)) {
|
dev_err(dev, "failed to register phy provider\n");
|
return PTR_ERR(phy_provider);
|
}
|
|
return 0;
|
}
|
|
static const struct of_device_id rockchip_edp_phy_of_match[] = {
|
{ .compatible = "rockchip,rk3568-edp-phy", },
|
{}
|
};
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MODULE_DEVICE_TABLE(of, rockchip_edp_phy_of_match);
|
|
static struct platform_driver rockchip_edp_phy_driver = {
|
.driver = {
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.name = "rockchip-edpphy-naneng",
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.of_match_table = of_match_ptr(rockchip_edp_phy_of_match),
|
},
|
.probe = rockchip_edp_phy_probe,
|
};
|
module_platform_driver(rockchip_edp_phy_driver);
|
|
MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
|
MODULE_DESCRIPTION("Rockchip Naneng eDP Transmitter PHY driver");
|
MODULE_LICENSE("GPL v2");
|
