// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Rockchip PCIe Apis For WIFI
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*
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* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/aspm_ext.h>
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#include <linux/errno.h>
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static u32 rockchip_pcie_pcie_access_cap(struct pci_dev *pdev, int cap, uint offset,
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bool is_ext, bool is_write, u32 writeval)
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{
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int cap_ptr = 0;
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u32 ret = -1;
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u32 readval;
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if (!(pdev)) {
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pci_err(pdev, "%s: pdev is NULL\n", __func__);
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return ret;
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}
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/* Find Capability offset */
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if (is_ext) {
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/* removing max EXT_CAP_ID check as
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* linux kernel definition's max value is not updated yet as per spec
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*/
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cap_ptr = pci_find_ext_capability(pdev, cap);
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} else {
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/* removing max PCI_CAP_ID_MAX check as
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* previous kernel versions dont have this definition
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*/
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cap_ptr = pci_find_capability(pdev, cap);
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}
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/* Return if capability with given ID not found */
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if (cap_ptr == 0) {
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pci_err(pdev, "%s: PCI Cap(0x%02x) not supported.\n",
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__func__, cap);
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return -EINVAL;
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}
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if (is_write) {
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pci_write_config_dword(pdev, (cap_ptr + offset), writeval);
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ret = 0;
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} else {
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pci_read_config_dword(pdev, (cap_ptr + offset), &readval);
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ret = readval;
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}
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return ret;
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}
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static bool rockchip_pcie_bus_aspm_enable_dev(char *device, struct pci_dev *dev, bool enable)
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{
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u32 linkctrl_before;
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u32 linkctrl_after = 0;
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u8 linkctrl_asm;
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linkctrl_before = rockchip_pcie_pcie_access_cap(dev, PCI_CAP_ID_EXP, PCI_EXP_LNKCTL,
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false, false, 0);
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linkctrl_asm = (linkctrl_before & PCI_EXP_LNKCTL_ASPMC);
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if (enable) {
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if (linkctrl_asm == PCI_EXP_LNKCTL_ASPM_L1) {
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pci_err(dev, "%s: %s already enabled linkctrl: 0x%x\n",
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__func__, device, linkctrl_before);
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return false;
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}
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/* Enable only L1 ASPM (bit 1) */
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rockchip_pcie_pcie_access_cap(dev, PCI_CAP_ID_EXP, PCI_EXP_LNKCTL, false,
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true, (linkctrl_before | PCI_EXP_LNKCTL_ASPM_L1));
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} else {
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if (linkctrl_asm == 0) {
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pci_err(dev, "%s: %s already disabled linkctrl: 0x%x\n",
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__func__, device, linkctrl_before);
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return false;
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}
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/* Disable complete ASPM (bit 1 and bit 0) */
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rockchip_pcie_pcie_access_cap(dev, PCI_CAP_ID_EXP, PCI_EXP_LNKCTL, false,
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true, (linkctrl_before & (~PCI_EXP_LNKCTL_ASPMC)));
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}
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linkctrl_after = rockchip_pcie_pcie_access_cap(dev, PCI_CAP_ID_EXP, PCI_EXP_LNKCTL,
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false, false, 0);
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pci_err(dev, "%s: %s %s, linkctrl_before: 0x%x linkctrl_after: 0x%x\n",
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__func__, device, (enable ? "ENABLE " : "DISABLE"),
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linkctrl_before, linkctrl_after);
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return true;
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}
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static bool rockchip_pcie_bus_aspm_enable_rc_ep(struct pci_dev *child, struct pci_dev *parent, bool enable)
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{
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bool ret;
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if (enable) {
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/* Enable only L1 ASPM first RC then EP */
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ret = rockchip_pcie_bus_aspm_enable_dev("RC", parent, enable);
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ret = rockchip_pcie_bus_aspm_enable_dev("EP", child, enable);
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} else {
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/* Disable complete ASPM first EP then RC */
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ret = rockchip_pcie_bus_aspm_enable_dev("EP", child, enable);
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ret = rockchip_pcie_bus_aspm_enable_dev("RC", parent, enable);
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}
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return ret;
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}
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static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos,
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u32 clear, u32 set)
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{
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u32 val;
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pci_read_config_dword(pdev, pos, &val);
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val &= ~clear;
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val |= set;
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pci_write_config_dword(pdev, pos, val);
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}
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/* Convert L1SS T_pwr encoding to usec */
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static u32 calc_l1ss_pwron(struct pci_dev *pdev, u32 scale, u32 val)
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{
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switch (scale) {
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case 0:
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return val * 2;
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case 1:
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return val * 10;
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case 2:
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return val * 100;
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}
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return 0;
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}
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static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value)
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{
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u32 threshold_ns = threshold_us * 1000;
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/* See PCIe r3.1, sec 7.33.3 and sec 6.18 */
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if (threshold_ns < 32) {
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*scale = 0;
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*value = threshold_ns;
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} else if (threshold_ns < 1024) {
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*scale = 1;
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*value = threshold_ns >> 5;
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} else if (threshold_ns < 32768) {
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*scale = 2;
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*value = threshold_ns >> 10;
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} else if (threshold_ns < 1048576) {
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*scale = 3;
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*value = threshold_ns >> 15;
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} else if (threshold_ns < 33554432) {
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*scale = 4;
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*value = threshold_ns >> 20;
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} else {
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*scale = 5;
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*value = threshold_ns >> 25;
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}
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}
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/* Calculate L1.2 PM substate timing parameters */
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static void aspm_calc_l1ss_info(struct pci_dev *child, struct pci_dev *parent)
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{
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u32 val1, val2, scale1, scale2;
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u32 t_common_mode, t_power_on, l1_2_threshold, scale, value;
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u32 ctl1 = 0, ctl2 = 0;
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u32 pctl1, pctl2, cctl1, cctl2;
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u32 pl1_2_enables, cl1_2_enables;
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u32 parent_l1ss_cap, child_l1ss_cap;
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/* Setup L1 substate */
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pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CAP,
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&parent_l1ss_cap);
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pci_read_config_dword(child, child->l1ss + PCI_L1SS_CAP,
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&child_l1ss_cap);
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/* Choose the greater of the two Port Common_Mode_Restore_Times */
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val1 = (parent_l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
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val2 = (child_l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
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t_common_mode = max(val1, val2);
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/* Choose the greater of the two Port T_POWER_ON times */
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val1 = (parent_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
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scale1 = (parent_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
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val2 = (child_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
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scale2 = (child_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
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if (calc_l1ss_pwron(parent, scale1, val1) >
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calc_l1ss_pwron(child, scale2, val2)) {
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ctl2 |= scale1 | (val1 << 3);
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t_power_on = calc_l1ss_pwron(parent, scale1, val1);
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} else {
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ctl2 |= scale2 | (val2 << 3);
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t_power_on = calc_l1ss_pwron(child, scale2, val2);
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}
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/* Set LTR_L1.2_THRESHOLD to the time required to transition the
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* Link from L0 to L1.2 and back to L0 so we enter L1.2 only if
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* downstream devices report (via LTR) that they can tolerate at
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* least that much latency.
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*
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* Based on PCIe r3.1, sec 5.5.3.3.1, Figures 5-16 and 5-17, and
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* Table 5-11. T(POWER_OFF) is at most 2us and T(L1.2) is at
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* least 4us.
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*/
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l1_2_threshold = 2 + 4 + t_common_mode + t_power_on;
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encode_l12_threshold(l1_2_threshold, &scale, &value);
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ctl1 |= t_common_mode << 8 | scale << 29 | value << 16;
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pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, &pctl1);
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pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, &pctl2);
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pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1, &cctl1);
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pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL2, &cctl2);
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if (ctl1 == pctl1 && ctl1 == cctl1 &&
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ctl2 == pctl2 && ctl2 == cctl2)
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return;
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/* Disable L1.2 while updating. See PCIe r5.0, sec 5.5.4, 7.8.3.3 */
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pl1_2_enables = pctl1 & PCI_L1SS_CTL1_L1_2_MASK;
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cl1_2_enables = cctl1 & PCI_L1SS_CTL1_L1_2_MASK;
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if (pl1_2_enables || cl1_2_enables) {
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pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
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PCI_L1SS_CTL1_L1_2_MASK, 0);
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pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
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PCI_L1SS_CTL1_L1_2_MASK, 0);
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}
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/* Program T_POWER_ON times in both ports */
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pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, ctl2);
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pci_write_config_dword(child, child->l1ss + PCI_L1SS_CTL2, ctl2);
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/* Program Common_Mode_Restore_Time in upstream device */
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pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
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PCI_L1SS_CTL1_CM_RESTORE_TIME, ctl1);
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/* Program LTR_L1.2_THRESHOLD time in both ports */
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pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
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PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
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PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1);
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pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
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PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
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PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1);
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if (pl1_2_enables || cl1_2_enables) {
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pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1, 0,
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pl1_2_enables);
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pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1, 0,
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cl1_2_enables);
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}
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}
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static void rockchip_pcie_bus_l1ss_enable_dev(char *device, struct pci_dev *dev, bool enable)
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{
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u32 l1ssctrl_before;
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u32 l1ssctrl_after = 0;
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u8 l1ss_ep;
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/* Extendend Capacility Reg */
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l1ssctrl_before = rockchip_pcie_pcie_access_cap(dev, PCI_EXT_CAP_ID_L1SS,
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PCI_L1SS_CTL1, true, false, 0);
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l1ss_ep = (l1ssctrl_before & PCI_L1SS_CTL1_L1SS_MASK);
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if (enable) {
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if (l1ss_ep == PCI_L1SS_CTL1_L1SS_MASK) {
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pci_err(dev, "%s: %s already enabled, l1ssctrl: 0x%x\n",
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__func__, device, l1ssctrl_before);
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return;
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}
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rockchip_pcie_pcie_access_cap(dev, PCI_EXT_CAP_ID_L1SS, PCI_L1SS_CTL1,
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true, true, (l1ssctrl_before | PCI_L1SS_CTL1_L1SS_MASK));
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} else {
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if (l1ss_ep == 0) {
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pci_err(dev, "%s: %s already disabled, l1ssctrl: 0x%x\n",
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__func__, device, l1ssctrl_before);
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return;
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}
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rockchip_pcie_pcie_access_cap(dev, PCI_EXT_CAP_ID_L1SS, PCI_L1SS_CTL1,
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true, true, (l1ssctrl_before & (~PCI_L1SS_CTL1_L1SS_MASK)));
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}
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l1ssctrl_after = rockchip_pcie_pcie_access_cap(dev, PCI_EXT_CAP_ID_L1SS,
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PCI_L1SS_CTL1, true, false, 0);
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pci_err(dev, "%s: %s %s, l1ssctrl_before: 0x%x l1ssctrl_after: 0x%x\n",
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__func__, device, (enable ? "ENABLE " : "DISABLE"),
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l1ssctrl_before, l1ssctrl_after);
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}
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bool pcie_aspm_ext_is_rc_ep_l1ss_capable(struct pci_dev *child, struct pci_dev *parent)
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{
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u32 parent_l1ss_cap, child_l1ss_cap;
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/* Setup L1 substate */
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pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CAP,
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&parent_l1ss_cap);
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pci_read_config_dword(child, child->l1ss + PCI_L1SS_CAP,
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&child_l1ss_cap);
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if (!(parent_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS))
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parent_l1ss_cap = 0;
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if (!(child_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS))
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child_l1ss_cap = 0;
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if (parent_l1ss_cap && child_l1ss_cap)
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return true;
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else
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return false;
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}
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EXPORT_SYMBOL(pcie_aspm_ext_is_rc_ep_l1ss_capable);
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void pcie_aspm_ext_l1ss_enable(struct pci_dev *child, struct pci_dev *parent, bool enable)
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{
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bool ret;
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/* Disable ASPM of RC and EP */
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ret = rockchip_pcie_bus_aspm_enable_rc_ep(child, parent, false);
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if (enable) {
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/* LRT enable bits loss after wifi off, enable it after power on */
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if (parent->ltr_path)
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pcie_capability_set_word(parent, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_LTR_EN);
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/* Enable RC then EP */
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aspm_calc_l1ss_info(child, parent);
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rockchip_pcie_bus_l1ss_enable_dev("RC", parent, enable);
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rockchip_pcie_bus_l1ss_enable_dev("EP", child, enable);
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} else {
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/* Disable EP then RC */
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rockchip_pcie_bus_l1ss_enable_dev("EP", child, enable);
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rockchip_pcie_bus_l1ss_enable_dev("RC", parent, enable);
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}
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/* Enable ASPM of RC and EP only if this API disabled */
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if (ret)
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rockchip_pcie_bus_aspm_enable_rc_ep(child, parent, true);
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}
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EXPORT_SYMBOL(pcie_aspm_ext_l1ss_enable);
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MODULE_LICENSE("GPL");
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