// SPDX-License-Identifier: GPL-2.0
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/*
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* RK628 eFuse Driver
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*
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* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
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*
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* Author: Weixin Zhou <zwx@rock-chips.com>
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/nvmem-provider.h>
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#include <linux/slab.h>
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#include <linux/gpio/consumer.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/mfd/rk628.h>
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#define EFUSE_SIZE 64
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#define T_CSB_P_S 0
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#define T_PGENB_P_S (15 + 200)
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#define T_LOAD_P_S 0
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#define T_ADDR_P_S (15 + 200 + 5)
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#define T_STROBE_P_S ((150 + 2000 + 100) / 9)
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#define T_CSB_P_L 0
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#define T_PGENB_P_L (15 + 200 + 10 + 200 + 190 + 10)
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#define T_LOAD_P_L (15 + 200 + 200 + 190 + 10 + 100 + 15)
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#define T_ADDR_P_L (15 + 200 + 5 + 200 + 5)
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#define T_STROBE_P_L ((150 + 2000 + 100 + 2000) / 9)
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#define T_CSB_R_S 0
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#define T_PGENB_R_S 0
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#define T_LOAD_R_S 15
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#define T_ADDR_R_S (15 + 9)
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#define T_STROBE_R_S ((150 + 100) / 9)
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#define T_CSB_R_L 0
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#define T_PGENB_R_L 0
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#define T_LOAD_R_L (15 + 5 + 5 + 10 + 15)
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#define T_ADDR_R_L (15 + 10 + 5 + 1)
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#define T_STROBE_R_L ((150 + 100 + 50) / 8)
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#define T_CSB_P 0x28
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#define T_PGENB_P 0x2c
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#define T_LOAD_P 0x30
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#define T_ADDR_P 0x34
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#define T_STROBE_P 0x38
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#define T_CSB_R 0x3c
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#define T_PGENB_R 0x40
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#define T_LOAD_R 0x44
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#define T_ADDR_R 0x48
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#define T_STROBE_R 0x4c
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#define EFUSE_REVISION 0x50
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#define RK628_EFUSE_BASE 0xb0000
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#define RK628_MOD 0x00
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#define RK628_INT_STATUS 0x0018
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#define RK628_DOUT 0x0020
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#define RK628_AUTO_CTRL 0x0024
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#define RK628_USER_MODE BIT(0)
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#define RK628_INT_FINISH BIT(0)
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#define RK628_AUTO_ENB BIT(0)
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#define RK628_AUTO_RD BIT(1)
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#define RK628_ADDR_ROW 16
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#define RK628_ADDR_COL 22
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#define RK628_A_SHIFT 16
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#define RK628_A_MASK 0x3ff
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#define RK628_NBYTES 1
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#define REG_EFUSE_CTRL 0x0000
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#define REG_EFUSE_DOUT 0x0004
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struct rk628_efuse_chip {
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struct device *dev;
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u32 base;
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struct clk *clk;
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struct regmap *regmap;
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struct gpio_desc *avdd_gpio;
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};
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static int rk628_read(struct regmap *regmap, u32 reg)
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{
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int ret;
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u32 val;
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struct rk628_efuse_chip *efuse = container_of(regmap, struct rk628_efuse_chip, regmap);
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ret = regmap_read(regmap, reg, &val);
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if (ret) {
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dev_err(efuse->dev, "rk628-efuse:failed to read reg 0x%x\n", reg);
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return ret;
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}
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return val;
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}
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static int rk628_write(struct regmap *regmap, u32 val, u32 reg)
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{
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int ret;
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struct rk628_efuse_chip *efuse = container_of(regmap, struct rk628_efuse_chip, regmap);
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ret = regmap_write(regmap, reg, val);
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if (ret)
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dev_err(efuse->dev, "rk628-efuse:failed to write reg 0x%x\n", reg);
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return ret;
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}
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static void rk628_efuse_timing_init(struct rk628_efuse_chip *efuse)
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{
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u32 base = efuse->base;
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/* enable auto mode */
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rk628_write(efuse->regmap,
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rk628_read(efuse->regmap, base + RK628_MOD) & (~RK628_USER_MODE),
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base + RK628_MOD);
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/* setup efuse timing */
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rk628_write(efuse->regmap, (T_CSB_P_S << 16) | T_CSB_P_L, base + T_CSB_P);
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rk628_write(efuse->regmap, (T_PGENB_P_S << 16) | T_PGENB_P_L, base + T_PGENB_P);
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rk628_write(efuse->regmap, (T_LOAD_P_S << 16) | T_LOAD_P_L, base + T_LOAD_P);
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rk628_write(efuse->regmap, (T_ADDR_P_S << 16) | T_ADDR_P_L, base + T_ADDR_P);
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rk628_write(efuse->regmap, (T_STROBE_P_S << 16) | T_STROBE_P_L, base + T_STROBE_P);
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rk628_write(efuse->regmap, (T_CSB_R_S << 16) | T_CSB_R_L, base + T_CSB_R);
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rk628_write(efuse->regmap, (T_PGENB_R_S << 16) | T_PGENB_R_L, base + T_PGENB_R);
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rk628_write(efuse->regmap, (T_LOAD_R_S << 16) | T_LOAD_R_L, base + T_LOAD_R);
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rk628_write(efuse->regmap, (T_ADDR_R_S << 16) | T_ADDR_R_L, base + T_ADDR_R);
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rk628_write(efuse->regmap, (T_STROBE_R_S << 16) | T_STROBE_R_L, base + T_STROBE_R);
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}
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static void rk628_efuse_timing_deinit(struct rk628_efuse_chip *efuse)
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{
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u32 base = efuse->base;
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/* disable auto mode */
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rk628_write(efuse->regmap,
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rk628_read(efuse->regmap, base + RK628_MOD) | RK628_USER_MODE, base + RK628_MOD);
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/* clear efuse timing */
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rk628_write(efuse->regmap, 0, base + T_CSB_P);
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rk628_write(efuse->regmap, 0, base + T_PGENB_P);
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rk628_write(efuse->regmap, 0, base + T_LOAD_P);
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rk628_write(efuse->regmap, 0, base + T_ADDR_P);
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rk628_write(efuse->regmap, 0, base + T_STROBE_P);
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rk628_write(efuse->regmap, 0, base + T_CSB_R);
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rk628_write(efuse->regmap, 0, base + T_PGENB_R);
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rk628_write(efuse->regmap, 0, base + T_LOAD_R);
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rk628_write(efuse->regmap, 0, base + T_ADDR_R);
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rk628_write(efuse->regmap, 0, base + T_STROBE_R);
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}
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static int rk628_efuse_read(void *context, unsigned int offset,
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void *val, size_t bytes)
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{
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struct rk628_efuse_chip *efuse = context;
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unsigned int addr_start, addr_end, addr_offset, addr_len;
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u32 out_value, status;
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u8 *buf;
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int ret, i = 0;
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ret = clk_prepare_enable(efuse->clk);
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if (ret < 0) {
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dev_err(efuse->dev, "failed to prepare/enable efuse pclk\n");
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return ret;
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}
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addr_start = rounddown(offset, RK628_NBYTES) / RK628_NBYTES;
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addr_end = roundup(offset + bytes, RK628_NBYTES) / RK628_NBYTES;
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addr_offset = offset % RK628_NBYTES;
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addr_len = addr_end - addr_start;
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buf = kzalloc(sizeof(*buf) * addr_len * RK628_NBYTES, GFP_KERNEL);
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if (!buf) {
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ret = -ENOMEM;
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goto nomem;
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}
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rk628_efuse_timing_init(efuse);
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while (addr_len--) {
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rk628_write(efuse->regmap, RK628_AUTO_RD | RK628_AUTO_ENB |
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((addr_start++ & RK628_A_MASK) << RK628_A_SHIFT),
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efuse->base + RK628_AUTO_CTRL);
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udelay(2);
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status = rk628_read(efuse->regmap, efuse->base + RK628_INT_STATUS);
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if (!(status & RK628_INT_FINISH)) {
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ret = -EIO;
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goto err;
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}
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out_value = rk628_read(efuse->regmap, efuse->base + RK628_DOUT);
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rk628_write(efuse->regmap, RK628_INT_FINISH, efuse->base + RK628_INT_STATUS);
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memcpy(&buf[i], &out_value, RK628_NBYTES);
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i += RK628_NBYTES;
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}
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memcpy(val, buf + addr_offset, bytes);
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err:
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rk628_efuse_timing_deinit(efuse);
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kfree(buf);
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nomem:
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clk_disable_unprepare(efuse->clk);
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return ret;
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}
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static struct nvmem_config econfig = {
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.name = "rk628-efuse",
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.owner = THIS_MODULE,
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.stride = 1,
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.word_size = 1,
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.read_only = true,
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};
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static const struct regmap_range rk628_efuse_readable_ranges[] = {
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regmap_reg_range(RK628_EFUSE_BASE, RK628_EFUSE_BASE + EFUSE_REVISION),
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};
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static const struct regmap_access_table rk628_efuse_readable_table = {
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.yes_ranges = rk628_efuse_readable_ranges,
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.n_yes_ranges = ARRAY_SIZE(rk628_efuse_readable_ranges),
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};
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static const struct regmap_config rk628_efuse_regmap_config = {
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.name = "rk628-efuse",
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = RK628_EFUSE_BASE + EFUSE_REVISION,
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.reg_format_endian = REGMAP_ENDIAN_LITTLE,
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.val_format_endian = REGMAP_ENDIAN_LITTLE,
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.rd_table = &rk628_efuse_readable_table,
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};
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static const struct of_device_id rk628_efuse_match[] = {
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{
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.compatible = "rockchip,rk628-efuse",
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},
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, rk628_efuse_match);
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static int __init rk628_efuse_probe(struct platform_device *pdev)
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{
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struct nvmem_device *nvmem;
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struct rk628_efuse_chip *efuse;
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struct device *dev = &pdev->dev;
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struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent);
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int ret;
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efuse = devm_kzalloc(&pdev->dev, sizeof(struct rk628_efuse_chip),
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GFP_KERNEL);
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if (!efuse)
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return -ENOMEM;
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efuse->regmap = devm_regmap_init_i2c(rk628->client,
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&rk628_efuse_regmap_config);
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if (IS_ERR(efuse->regmap)) {
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ret = PTR_ERR(efuse->regmap);
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dev_err(dev, "failed to allocate register map: %d\n",
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ret);
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return ret;
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}
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efuse->clk = devm_clk_get(&pdev->dev, "pclk");
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if (IS_ERR(efuse->clk)) {
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dev_err(dev, "failed to get pclk: %ld\n", PTR_ERR(efuse->clk));
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return PTR_ERR(efuse->clk);
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}
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efuse->avdd_gpio = devm_gpiod_get_optional(dev, "efuse", GPIOD_OUT_LOW);
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efuse->base = RK628_EFUSE_BASE;
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efuse->dev = &pdev->dev;
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econfig.size = EFUSE_SIZE;
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econfig.reg_read = (void *)&rk628_efuse_read;
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econfig.priv = efuse;
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econfig.dev = efuse->dev;
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nvmem = devm_nvmem_register(&econfig);
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if (IS_ERR(nvmem))
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return PTR_ERR(nvmem);
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platform_set_drvdata(pdev, nvmem);
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return 0;
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}
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static struct platform_driver rk628_efuse_driver = {
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.probe = rk628_efuse_probe,
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.driver = {
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.name = "rk628-efuse",
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.of_match_table = rk628_efuse_match,
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},
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};
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module_platform_driver(rk628_efuse_driver);
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MODULE_DESCRIPTION("rk628_efuse driver");
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MODULE_LICENSE("GPL v2");
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