/******************************************************************************
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*
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* Copyright(c) 2019 - 2023 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef _RTW_GENERAL_DEF_H_
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#define _RTW_GENERAL_DEF_H_
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#define SEC_CAP_CHK_BMC BIT0
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#define BIT0 0x00000001
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#define BIT1 0x00000002
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#define BIT2 0x00000004
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#define BIT3 0x00000008
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#define BIT4 0x00000010
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#define BIT5 0x00000020
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#define BIT6 0x00000040
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#define BIT7 0x00000080
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#define BIT8 0x00000100
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#define BIT9 0x00000200
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#define BIT10 0x00000400
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#define BIT11 0x00000800
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#define BIT12 0x00001000
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#define BIT13 0x00002000
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#define BIT14 0x00004000
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#define BIT15 0x00008000
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#define BIT16 0x00010000
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#define BIT17 0x00020000
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#define BIT18 0x00040000
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#define BIT19 0x00080000
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#define BIT20 0x00100000
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#define BIT21 0x00200000
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#define BIT22 0x00400000
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#define BIT23 0x00800000
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#define BIT24 0x01000000
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#define BIT25 0x02000000
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#define BIT26 0x04000000
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#define BIT27 0x08000000
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#define BIT28 0x10000000
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#define BIT29 0x20000000
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#define BIT30 0x40000000
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#define BIT31 0x80000000
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#define RTW_U32_MAX 0xFFFFFFFF
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enum rtl_ic_id {
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RTL8852A,
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RTL8834A,
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RTL8852B,
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RTL8852C,
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RTL8852D,
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RTL8192XB,
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RTL8832BR,
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RTL8852BP,
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RTL8851B,
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RTL8852BT,
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MAX_IC_ID
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};
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/* BIT definition for combination */
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enum rtw_hci_type {
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RTW_HCI_PCIE = BIT0,
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RTW_HCI_USB = BIT1,
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RTW_HCI_SDIO = BIT2,
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RTW_HCI_GSPI = BIT3,
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RTW_HCI_MAX,
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};
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#define SM_PS_STATIC 0
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#define SM_PS_DYNAMIC 1
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#define SM_PS_INVALID 2
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#define SM_PS_DISABLE 3
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#define MAC_ADDRESS_LENGTH 6
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#define IPV4_ADDRESS_LENGTH 4
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#define IPV6_ADDRESS_LENGTH 16
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/* Core shall translate system condition into device state for PHL controller */
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enum rtw_dev_state {
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RTW_DEV_WORKING = BIT0,
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RTW_DEV_SUSPENDING = BIT1,
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RTW_DEV_RESUMING = BIT2,
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RTW_DEV_SURPRISE_REMOVAL = BIT3,
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RTW_DEV_IN_DFS_CAC_PERIOD = BIT4,
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RTW_DEV_SHUTTING_DOWN = BIT5, /* set by core */
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RTW_DEV_SUSPENDED = BIT6,
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RTW_DEV_MAX
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};
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#define RTW_RATE_MODE_MASK (BIT(7) | BIT(8))
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#define RTW_RATE_MODE_SHIFT 7
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#define RTW_RATE_INDEX_MASK 0x007f
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#define RTW_GET_RATE_MODE(_rtw_data_rate) (u16)((_rtw_data_rate & RTW_RATE_MODE_MASK) >> RTW_RATE_MODE_SHIFT)
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#define RTW_GET_RATE_INDEX(_rtw_data_rate) (u16)(_rtw_data_rate & RTW_RATE_INDEX_MASK)
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enum rtw_rate_mode {
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RTW_LEGACY_MODE = 0,
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RTW_HT_MODE = 1,
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RTW_VHT_MODE = 2,
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RTW_HE_MODE = 3
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};
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enum rtw_data_rate {
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RTW_DATA_RATE_CCK1 = 0x0,
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RTW_DATA_RATE_CCK2 = 0x1,
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RTW_DATA_RATE_CCK5_5 = 0x2,
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RTW_DATA_RATE_CCK11 = 0x3,
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RTW_DATA_RATE_OFDM6 = 0x4,
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RTW_DATA_RATE_OFDM9 = 0x5,
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RTW_DATA_RATE_OFDM12 = 0x6,
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RTW_DATA_RATE_OFDM18 = 0x7,
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RTW_DATA_RATE_OFDM24 = 0x8,
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RTW_DATA_RATE_OFDM36 = 0x9,
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RTW_DATA_RATE_OFDM48 = 0xA,
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RTW_DATA_RATE_OFDM54 = 0xB,
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RTW_DATA_RATE_MCS0 = 0x80,
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RTW_DATA_RATE_MCS1 = 0x81,
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RTW_DATA_RATE_MCS2 = 0x82,
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RTW_DATA_RATE_MCS3 = 0x83,
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RTW_DATA_RATE_MCS4 = 0x84,
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RTW_DATA_RATE_MCS5 = 0x85,
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RTW_DATA_RATE_MCS6 = 0x86,
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RTW_DATA_RATE_MCS7 = 0x87,
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RTW_DATA_RATE_MCS8 = 0x88,
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RTW_DATA_RATE_MCS9 = 0x89,
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RTW_DATA_RATE_MCS10 = 0x8A,
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RTW_DATA_RATE_MCS11 = 0x8B,
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RTW_DATA_RATE_MCS12 = 0x8C,
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RTW_DATA_RATE_MCS13 = 0x8D,
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RTW_DATA_RATE_MCS14 = 0x8E,
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RTW_DATA_RATE_MCS15 = 0x8F,
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RTW_DATA_RATE_MCS16 = 0x90,
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RTW_DATA_RATE_MCS17 = 0x91,
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RTW_DATA_RATE_MCS18 = 0x92,
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RTW_DATA_RATE_MCS19 = 0x93,
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RTW_DATA_RATE_MCS20 = 0x94,
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RTW_DATA_RATE_MCS21 = 0x95,
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RTW_DATA_RATE_MCS22 = 0x96,
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RTW_DATA_RATE_MCS23 = 0x97,
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RTW_DATA_RATE_MCS24 = 0x98,
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RTW_DATA_RATE_MCS25 = 0x99,
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RTW_DATA_RATE_MCS26 = 0x9A,
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RTW_DATA_RATE_MCS27 = 0x9B,
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RTW_DATA_RATE_MCS28 = 0x9C,
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RTW_DATA_RATE_MCS29 = 0x9D,
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RTW_DATA_RATE_MCS30 = 0x9E,
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RTW_DATA_RATE_MCS31 = 0x9F,
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RTW_DATA_RATE_VHT_NSS1_MCS0 = 0x100,
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RTW_DATA_RATE_VHT_NSS1_MCS1 = 0x101,
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RTW_DATA_RATE_VHT_NSS1_MCS2 = 0x102,
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RTW_DATA_RATE_VHT_NSS1_MCS3 = 0x103,
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RTW_DATA_RATE_VHT_NSS1_MCS4 = 0x104,
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RTW_DATA_RATE_VHT_NSS1_MCS5 = 0x105,
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RTW_DATA_RATE_VHT_NSS1_MCS6 = 0x106,
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RTW_DATA_RATE_VHT_NSS1_MCS7 = 0x107,
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RTW_DATA_RATE_VHT_NSS1_MCS8 = 0x108,
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RTW_DATA_RATE_VHT_NSS1_MCS9 = 0x109,
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RTW_DATA_RATE_VHT_NSS2_MCS0 = 0x110,
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RTW_DATA_RATE_VHT_NSS2_MCS1 = 0x111,
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RTW_DATA_RATE_VHT_NSS2_MCS2 = 0x112,
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RTW_DATA_RATE_VHT_NSS2_MCS3 = 0x113,
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RTW_DATA_RATE_VHT_NSS2_MCS4 = 0x114,
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RTW_DATA_RATE_VHT_NSS2_MCS5 = 0x115,
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RTW_DATA_RATE_VHT_NSS2_MCS6 = 0x116,
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RTW_DATA_RATE_VHT_NSS2_MCS7 = 0x117,
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RTW_DATA_RATE_VHT_NSS2_MCS8 = 0x118,
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RTW_DATA_RATE_VHT_NSS2_MCS9 = 0x119,
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RTW_DATA_RATE_VHT_NSS3_MCS0 = 0x120,
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RTW_DATA_RATE_VHT_NSS3_MCS1 = 0x121,
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RTW_DATA_RATE_VHT_NSS3_MCS2 = 0x122,
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RTW_DATA_RATE_VHT_NSS3_MCS3 = 0x123,
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RTW_DATA_RATE_VHT_NSS3_MCS4 = 0x124,
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RTW_DATA_RATE_VHT_NSS3_MCS5 = 0x125,
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RTW_DATA_RATE_VHT_NSS3_MCS6 = 0x126,
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RTW_DATA_RATE_VHT_NSS3_MCS7 = 0x127,
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RTW_DATA_RATE_VHT_NSS3_MCS8 = 0x128,
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RTW_DATA_RATE_VHT_NSS3_MCS9 = 0x129,
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RTW_DATA_RATE_VHT_NSS4_MCS0 = 0x130,
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RTW_DATA_RATE_VHT_NSS4_MCS1 = 0x131,
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RTW_DATA_RATE_VHT_NSS4_MCS2 = 0x132,
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RTW_DATA_RATE_VHT_NSS4_MCS3 = 0x133,
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RTW_DATA_RATE_VHT_NSS4_MCS4 = 0x134,
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RTW_DATA_RATE_VHT_NSS4_MCS5 = 0x135,
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RTW_DATA_RATE_VHT_NSS4_MCS6 = 0x136,
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RTW_DATA_RATE_VHT_NSS4_MCS7 = 0x137,
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RTW_DATA_RATE_VHT_NSS4_MCS8 = 0x138,
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RTW_DATA_RATE_VHT_NSS4_MCS9 = 0x139,
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RTW_DATA_RATE_HE_NSS1_MCS0 = 0x180,
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RTW_DATA_RATE_HE_NSS1_MCS1 = 0x181,
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RTW_DATA_RATE_HE_NSS1_MCS2 = 0x182,
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RTW_DATA_RATE_HE_NSS1_MCS3 = 0x183,
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RTW_DATA_RATE_HE_NSS1_MCS4 = 0x184,
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RTW_DATA_RATE_HE_NSS1_MCS5 = 0x185,
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RTW_DATA_RATE_HE_NSS1_MCS6 = 0x186,
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RTW_DATA_RATE_HE_NSS1_MCS7 = 0x187,
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RTW_DATA_RATE_HE_NSS1_MCS8 = 0x188,
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RTW_DATA_RATE_HE_NSS1_MCS9 = 0x189,
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RTW_DATA_RATE_HE_NSS1_MCS10 = 0x18A,
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RTW_DATA_RATE_HE_NSS1_MCS11 = 0x18B,
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RTW_DATA_RATE_HE_NSS2_MCS0 = 0x190,
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RTW_DATA_RATE_HE_NSS2_MCS1 = 0x191,
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RTW_DATA_RATE_HE_NSS2_MCS2 = 0x192,
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RTW_DATA_RATE_HE_NSS2_MCS3 = 0x193,
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RTW_DATA_RATE_HE_NSS2_MCS4 = 0x194,
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RTW_DATA_RATE_HE_NSS2_MCS5 = 0x195,
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RTW_DATA_RATE_HE_NSS2_MCS6 = 0x196,
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RTW_DATA_RATE_HE_NSS2_MCS7 = 0x197,
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RTW_DATA_RATE_HE_NSS2_MCS8 = 0x198,
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RTW_DATA_RATE_HE_NSS2_MCS9 = 0x199,
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RTW_DATA_RATE_HE_NSS2_MCS10 = 0x19A,
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RTW_DATA_RATE_HE_NSS2_MCS11 = 0x19B,
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RTW_DATA_RATE_HE_NSS3_MCS0 = 0x1A0,
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RTW_DATA_RATE_HE_NSS3_MCS1 = 0x1A1,
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RTW_DATA_RATE_HE_NSS3_MCS2 = 0x1A2,
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RTW_DATA_RATE_HE_NSS3_MCS3 = 0x1A3,
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RTW_DATA_RATE_HE_NSS3_MCS4 = 0x1A4,
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RTW_DATA_RATE_HE_NSS3_MCS5 = 0x1A5,
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RTW_DATA_RATE_HE_NSS3_MCS6 = 0x1A6,
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RTW_DATA_RATE_HE_NSS3_MCS7 = 0x1A7,
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RTW_DATA_RATE_HE_NSS3_MCS8 = 0x1A8,
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RTW_DATA_RATE_HE_NSS3_MCS9 = 0x1A9,
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RTW_DATA_RATE_HE_NSS3_MCS10 = 0x1AA,
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RTW_DATA_RATE_HE_NSS3_MCS11 = 0x1AB,
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RTW_DATA_RATE_HE_NSS4_MCS0 = 0x1B0,
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RTW_DATA_RATE_HE_NSS4_MCS1 = 0x1B1,
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RTW_DATA_RATE_HE_NSS4_MCS2 = 0x1B2,
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RTW_DATA_RATE_HE_NSS4_MCS3 = 0x1B3,
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RTW_DATA_RATE_HE_NSS4_MCS4 = 0x1B4,
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RTW_DATA_RATE_HE_NSS4_MCS5 = 0x1B5,
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RTW_DATA_RATE_HE_NSS4_MCS6 = 0x1B6,
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RTW_DATA_RATE_HE_NSS4_MCS7 = 0x1B7,
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RTW_DATA_RATE_HE_NSS4_MCS8 = 0x1B8,
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RTW_DATA_RATE_HE_NSS4_MCS9 = 0x1B9,
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RTW_DATA_RATE_HE_NSS4_MCS10 = 0x1BA,
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RTW_DATA_RATE_HE_NSS4_MCS11 = 0x1BB,
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RTW_DATA_RATE_MAX = 0x1FF
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};
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enum rtw_gi_ltf {
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RTW_GILTF_LGI_4XHE32 = 0,
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RTW_GILTF_SGI_4XHE08 = 1,
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RTW_GILTF_2XHE16 = 2,
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RTW_GILTF_2XHE08 = 3,
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RTW_GILTF_1XHE16 = 4,
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RTW_GILTF_1XHE08 = 5,
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RTW_GILTF_MAX
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};
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/* 11ax spec define for HE Trigger Frame, only used for HE Trigger Frame! */
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enum rtw_gi_ltf_ul_tb {
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RTW_TB_GILTF_1XHE16 = 0,
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RTW_TB_GILTF_2XHE16 = 1,
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RTW_TB_GILTF_4XHE32 = 2,
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RTW_TB_GILTF_MAX
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};
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#define RTW_PHL_MAX_RF_PATH 4
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enum rf_path {
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RF_PATH_A = 0,
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RF_PATH_B = 1,
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RF_PATH_C = 2,
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RF_PATH_D = 3,
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RF_PATH_AB,
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RF_PATH_AC,
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RF_PATH_AD,
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RF_PATH_BC,
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RF_PATH_BD,
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RF_PATH_CD,
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RF_PATH_ABC,
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RF_PATH_ABD,
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RF_PATH_ACD,
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RF_PATH_BCD,
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RF_PATH_ABCD,
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};
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/*HW SPEC & SW/HW CAP*/
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#define PROTO_CAP_11B BIT0
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#define PROTO_CAP_11G BIT1
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#define PROTO_CAP_11N BIT2
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#define PROTO_CAP_11AC BIT3
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#define PROTO_CAP_11AX BIT4
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#define PROTO_CAP_BIT_NUM 4
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enum wlan_mode {
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WLAN_MD_INVALID = 0,
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WLAN_MD_11B = BIT0,
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WLAN_MD_11A = BIT1,
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WLAN_MD_11G = BIT2,
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WLAN_MD_11N = BIT3,
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WLAN_MD_11AC = BIT4,
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WLAN_MD_11AX = BIT5,
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/* Type for current wireless mode */
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WLAN_MD_11BG = (WLAN_MD_11B | WLAN_MD_11G),
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WLAN_MD_11GN = (WLAN_MD_11G | WLAN_MD_11N),
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WLAN_MD_11AN = (WLAN_MD_11A | WLAN_MD_11N),
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WLAN_MD_11BN = (WLAN_MD_11B | WLAN_MD_11N),
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WLAN_MD_11BGN = (WLAN_MD_11B | WLAN_MD_11G | WLAN_MD_11N),
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WLAN_MD_11BGAC = (WLAN_MD_11B | WLAN_MD_11G | WLAN_MD_11AC),
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WLAN_MD_11BGAX = (WLAN_MD_11B | WLAN_MD_11G | WLAN_MD_11AX),
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WLAN_MD_11GAC = (WLAN_MD_11G | WLAN_MD_11AC),
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WLAN_MD_11GAX = (WLAN_MD_11G | WLAN_MD_11AX),
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WLAN_MD_11A_AC = (WLAN_MD_11A | WLAN_MD_11AC),
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WLAN_MD_11A_AX = (WLAN_MD_11A | WLAN_MD_11AX),
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/* Capability -Type for registry default wireless mode */
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WLAN_MD_11AGN = (WLAN_MD_11A | WLAN_MD_11G | WLAN_MD_11N ),
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WLAN_MD_11ABGN = (WLAN_MD_11A | WLAN_MD_11B | WLAN_MD_11G | WLAN_MD_11N ),
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WLAN_MD_11ANAC = (WLAN_MD_11A | WLAN_MD_11N | WLAN_MD_11AC),
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WLAN_MD_11BGNAC = (WLAN_MD_11B | WLAN_MD_11G | WLAN_MD_11N | WLAN_MD_11AC),
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WLAN_MD_11GNAC = (WLAN_MD_11G | WLAN_MD_11N | WLAN_MD_11AC),
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WLAN_MD_24G_MIX = (WLAN_MD_11B | WLAN_MD_11G | WLAN_MD_11N | WLAN_MD_11AC | WLAN_MD_11AX),
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WLAN_MD_5G_MIX = (WLAN_MD_11A | WLAN_MD_11N | WLAN_MD_11AC | WLAN_MD_11AX),
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WLAN_MD_6G_MIX = (WLAN_MD_11A | WLAN_MD_11AX),
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WLAN_MD_MAX = (WLAN_MD_24G_MIX|WLAN_MD_5G_MIX),
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};
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enum band_type {
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BAND_ON_24G = 0,
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BAND_ON_5G = 1,
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BAND_ON_6G = 2,
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BAND_MAX,
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};
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/*HW SPEC & SW/HW CAP*/
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#define BAND_CAP_2G BIT(BAND_ON_24G)
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#define BAND_CAP_5G BIT(BAND_ON_5G)
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#define BAND_CAP_6G BIT(BAND_ON_6G)
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#define BAND_CAP_BIT_NUM 3
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enum channel_width {
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CHANNEL_WIDTH_20 = 0,
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CHANNEL_WIDTH_40 = 1,
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CHANNEL_WIDTH_80 = 2,
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CHANNEL_WIDTH_160 = 3,
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CHANNEL_WIDTH_80_80 = 4,
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CHANNEL_WIDTH_5 = 5,
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CHANNEL_WIDTH_10 = 6,
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CHANNEL_WIDTH_MAX = 7,
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};
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/*HW SPEC & SW/HW CAP*/
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#define BW_CAP_20M BIT(CHANNEL_WIDTH_20)
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#define BW_CAP_40M BIT(CHANNEL_WIDTH_40)
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#define BW_CAP_80M BIT(CHANNEL_WIDTH_80)
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#define BW_CAP_160M BIT(CHANNEL_WIDTH_160)
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#define BW_CAP_80_80M BIT(CHANNEL_WIDTH_80_80)
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#define BW_CAP_5M BIT(CHANNEL_WIDTH_5)
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#define BW_CAP_10M BIT(CHANNEL_WIDTH_10)
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#define BW_CAP_BIT_NUM 7
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|
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/*
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* Represent Extention Channel Offset in HT Capabilities
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* Secondary Channel Offset
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* 0 -SCN, 1 -SCA, 2 -RSVD, 3 - SCB
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*
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*/
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enum chan_offset {
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CHAN_OFFSET_NO_EXT = 0, /*SCN - no secondary channel*/
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CHAN_OFFSET_UPPER = 1, /*SCA - secondary channel above*/
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CHAN_OFFSET_NO_DEF = 2, /*Reserved*/
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CHAN_OFFSET_LOWER = 3, /*SCB - secondary channel below*/
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CHAN_OFFSET_40M_UPPER = 4,
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CHAN_OFFSET_40M_LOWER = 5,
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CHAN_OFFSET_80M_UPPER = 6,
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CHAN_OFFSET_80M_LOWER = 7,
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};
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enum rf_type {
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RF_1T1R = 0,
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RF_1T2R = 1,
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RF_2T2R = 2,
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RF_2T3R = 3,
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RF_2T4R = 4,
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RF_3T3R = 5,
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RF_3T4R = 6,
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RF_4T4R = 7,
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RF_TYPE_MAX,
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};
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enum rtw_rf_state {
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RTW_RF_ON,
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RTW_RF_OFF,
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RTW_RF_MAX
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};
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enum rtw_usb_speed {
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RTW_USB_SPEED_LOW = 0, /*U2 (2.0)- 1.0 - 1.5 Mbps - 0.192MBs*/
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RTW_USB_SPEED_FULL = 1, /*U2 (2.0)- 1.1 - 12 Mbps - 1.5MBs*/
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RTW_USB_SPEED_HIGH = 2, /*U2 (2.0)- 2.1 - 480 Mbps - 60MBs*/
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RTW_USB_SPEED_SUPER = 3, /*U3 (3.2 Gen 1)- 3.0 - 5 Gbps - 640MBs*/
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RTW_USB_SPEED_SUPER_10G = 4, /*U3 (3.2 Gen 2)- 3.1 - 10 Gbps - 1280MBs*/
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RTW_USB_SPEED_SUPER_20G = 5, /*U3 (3.2 Gen 2x2)- 3.2 - 20 Gbps - 2560MBs*/
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/* keep last */
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RTW_USB_SPEED_MAX,
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RTW_USB_SPEED_UNKNOWN = RTW_USB_SPEED_MAX,
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};
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#define USB_SUPER_SPEED_BULK_SIZE 1024 /* usb 3.0 */
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#define USB_HIGH_SPEED_BULK_SIZE 512 /* usb 2.0 */
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#define USB_FULL_SPEED_BULK_SIZE 64 /* usb 1.1 */
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#define IV_LENGTH 8
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enum rtw_enc_algo {
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RTW_ENC_NONE,
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RTW_ENC_WEP40,
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RTW_ENC_WEP104,
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RTW_ENC_TKIP,
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RTW_ENC_WAPI,
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RTW_ENC_GCMSMS4,
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RTW_ENC_CCMP,
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RTW_ENC_CCMP256,
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RTW_ENC_GCMP,
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RTW_ENC_GCMP256,
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RTW_ENC_BIP_CCMP128,
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RTW_ENC_MAX
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};
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enum rtw_sec_ent_mode {
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RTW_SEC_ENT_MODE_0, /* No key */
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RTW_SEC_ENT_MODE_1, /* WEP */
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RTW_SEC_ENT_MODE_2, /* 2 unicast + 3 multicast + 2 BIP keys */
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RTW_SEC_ENT_MODE_3, /* 2 unicast + 4 multicast + 1 BIP keys */
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};
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enum rtw_sec_key_type {
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RTW_SEC_KEY_UNICAST,
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RTW_SEC_KEY_MULTICAST,
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RTW_SEC_KEY_BIP,
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RTW_SEC_KEY_MAX
|
};
|
|
/**
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* Figure 27-7 + Table 9-31h from Ax Spec D4.2
|
* B7-B1:
|
* RU26 : 0 1 2 3 4 5 6 7 8 9 10 ... 36
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* RU52 : 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
|
* RU106 : 53 54 55 56 57 58 59 60
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* RU242 : 61 62 63 64
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* RU484 : 65 66
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* RU996 : 67
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* RU996x2: 68
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**/
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enum rtw_he_ru_idx {
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/* 20MHz - 1 */
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RTW_HE_RU26_1 = 0,
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RTW_HE_RU26_2,
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RTW_HE_RU26_3,
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RTW_HE_RU26_4,
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RTW_HE_RU26_5,
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RTW_HE_RU26_6,
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RTW_HE_RU26_7,
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RTW_HE_RU26_8,
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RTW_HE_RU26_9,
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/* 20MHz - 2 */
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RTW_HE_RU26_10,
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RTW_HE_RU26_11,
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RTW_HE_RU26_12,
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RTW_HE_RU26_13,
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RTW_HE_RU26_14,
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RTW_HE_RU26_15,
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RTW_HE_RU26_16,
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RTW_HE_RU26_17,
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RTW_HE_RU26_18,
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/* Center 26-tone */
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RTW_HE_RU26_19,
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/* 20MHz - 3 */
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RTW_HE_RU26_20,
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RTW_HE_RU26_21,
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RTW_HE_RU26_22,
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RTW_HE_RU26_23,
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RTW_HE_RU26_24,
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RTW_HE_RU26_25,
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RTW_HE_RU26_26,
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RTW_HE_RU26_27,
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RTW_HE_RU26_28,
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/* 20MHz - 4 */
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RTW_HE_RU26_29,
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RTW_HE_RU26_30,
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RTW_HE_RU26_31,
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RTW_HE_RU26_32,
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RTW_HE_RU26_33,
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RTW_HE_RU26_34,
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RTW_HE_RU26_35,
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RTW_HE_RU26_36,
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RTW_HE_RU26_37 = 36,
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/* 20MHz - 1 */
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RTW_HE_RU52_1 = 37,
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RTW_HE_RU52_2,
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RTW_HE_RU52_3,
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RTW_HE_RU52_4,
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/* 20MHz - 2 */
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RTW_HE_RU52_5,
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RTW_HE_RU52_6,
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RTW_HE_RU52_7,
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RTW_HE_RU52_8,
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/* 20MHz - 3 */
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RTW_HE_RU52_9,
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RTW_HE_RU52_10,
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RTW_HE_RU52_11,
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RTW_HE_RU52_12,
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/* 20MHz - 4 */
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RTW_HE_RU52_13,
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RTW_HE_RU52_14,
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RTW_HE_RU52_15,
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RTW_HE_RU52_16 = 52,
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/* 20MHz - 1 */
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RTW_HE_RU106_1 = 53,
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RTW_HE_RU106_2,
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/* 20MHz - 2 */
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RTW_HE_RU106_3,
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RTW_HE_RU106_4,
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/* 20MHz - 3 */
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RTW_HE_RU106_5,
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RTW_HE_RU106_6,
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/* 20MHz - 4 */
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RTW_HE_RU106_7,
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RTW_HE_RU106_8 = 60,
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/* 20MHz */
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RTW_HE_RU242_1 = 61,
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RTW_HE_RU242_2,
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RTW_HE_RU242_3,
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RTW_HE_RU242_4 = 64,
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/* 40MHz */
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RTW_HE_RU484_1 = 65,
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RTW_HE_RU484_2 = 66,
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/* 80MHz */
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RTW_HE_RU996_1 = 67,
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/* 160MHz */
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RTW_HE_RU2x996_1 = 68,
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};
|
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enum rtw_protect_mode {
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RTW_PROTECT_DISABLE = 0,
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RTW_PROTECT_RTS = 1,
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RTW_PROTECT_CTS2SELF = 2,
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RTW_PROTECT_HW_RTS = 3
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};
|
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enum rtw_ac {
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RTW_AC_BE = 0,
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RTW_AC_BK = 1,
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RTW_AC_VI = 2,
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RTW_AC_VO = 3,
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RTW_AC_MAX
|
};
|
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enum rtw_edcca_mode {
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RTW_EDCCA_NORMAL,
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RTW_EDCCA_ETSI,
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RTW_EDCCA_JP,
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RTW_EDCCA_FCC,
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RTW_EDCCA_MAX
|
};
|
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enum rtw_mac_pwr_st {
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RTW_MAC_PWR_NONE = 0,
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RTW_MAC_PWR_OFF = 1,
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RTW_MAC_PWR_ON = 2,
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RTW_MAC_PWR_LPS = 3,
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RTW_MAC_PWR_MAX = 0x4
|
};
|
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enum rtw_pcie_bus_func_cap_t {
|
RTW_PCIE_BUS_FUNC_DISABLE = 0,
|
RTW_PCIE_BUS_FUNC_ENABLE = 1,
|
RTW_PCIE_BUS_FUNC_DEFAULT = 2,
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RTW_PCIE_BUS_FUNC_IGNORE = 3
|
};
|
|
/* follow mac's definetion, mac_ax_sw_io_mode*/
|
enum rtw_gpio_mode {
|
RTW_AX_SW_IO_MODE_INPUT,
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RTW_AX_SW_IO_MODE_OUTPUT_OD,
|
RTW_AX_SW_IO_MODE_OUTPUT_PP,
|
RTW_AX_SW_IO_MODE_MAX
|
};
|
|
enum rtw_p2p_app_type {
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RTW_P2P_APP_NONE = 0,
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RTW_P2P_APP_UNKNOWN = 1,
|
RTW_P2P_APP_GC = 2,
|
RTW_P2P_APP_GO_HOTSPOT =3,
|
RTW_P2P_APP_GO_SRC = 4,
|
RTW_P2P_APP_GO_SINK = 5,
|
RTW_P2P_APP_GO_SRC_SINK = 6,
|
RTW_P2P_SESSION_MAX
|
};
|
|
/*MAC_AX_PCIE_L0SDLY_IGNORE = 0xFF, MAC_AX_PCIE_L1DLY_IGNORE = 0xFF, MAC_AX_PCIE_CLKDLY_IGNORE = 0xFF */
|
#define RTW_PCIE_BUS_ASPM_DLY_IGNORE 0xFF /* Fully controlled by HW */
|
|
#define RTW_FRAME_TYPE_MGNT 0
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#define RTW_FRAME_TYPE_CTRL 1
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#define RTW_FRAME_TYPE_DATA 2
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#define RTW_FRAME_TYPE_EXT_RSVD 3
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/* Association Related PKT Type + SubType */
|
|
#define FRAME_OFFSET_FRAME_CONTROL 0
|
#define FRAME_OFFSET_DURATION 2
|
#define FRAME_OFFSET_ADDRESS1 4
|
#define FRAME_OFFSET_ADDRESS2 10
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#define FRAME_OFFSET_ADDRESS3 16
|
#define FRAME_OFFSET_SEQUENCE 22
|
#define FRAME_OFFSET_ADDRESS4 24
|
#define PHL_GET_80211_HDR_TYPE(_hdr) LE_BITS_TO_2BYTE((u8 *)_hdr, 2, 6)
|
#define PHL_GET_80211_HDR_MORE_FRAG(_hdr) LE_BITS_TO_2BYTE((u8 *)_hdr, 10, 1)
|
#define PHL_GET_80211_HDR_RETRY(_hdr) LE_BITS_TO_2BYTE((u8 *)_hdr, 11, 1)
|
#define PHL_GET_80211_HDR_FRAG_NUM(_hdr) LE_BITS_TO_2BYTE((u8 *)_hdr + 22, 0, 4)
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#define PHL_GET_80211_HDR_SEQUENCE(_hdr) LE_BITS_TO_2BYTE((u8 *)_hdr + 22, 4, 12)
|
#define PHL_GET_80211_HDR_ADDRESS2(_d, _hdr, _val) \
|
_os_mem_cpy(_d, (u8 *)_val, (u8 *)_hdr + FRAME_OFFSET_ADDRESS2, 6)
|
#define PHL_GET_80211_HDR_ADDRESS3(_d, _hdr, _val) \
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_os_mem_cpy(_d, (u8 *)_val, (u8 *)_hdr + FRAME_OFFSET_ADDRESS3, 6)
|
|
#define RTW_FRAME_TYPE_BEACON 32
|
#define RTW_FRAME_TYPE_PROBE_RESP 20
|
#define RTW_FRAME_TYPE_ASOC_REQ 0
|
#define RTW_FRAME_TYPE_ASOC_RESP 4
|
#define RTW_FRAME_TYPE_REASOC_REQ 8
|
#define RTW_FRAME_TYPE_REASOC_RESP 12
|
#define RTW_FRAME_TYPE_ACK 53
|
#define RTW_IS_ASOC_PKT(_TYPE) \
|
((_TYPE == RTW_FRAME_TYPE_REASOC_RESP) || \
|
(_TYPE == RTW_FRAME_TYPE_REASOC_REQ) || \
|
(_TYPE == RTW_FRAME_TYPE_ASOC_RESP) || \
|
(_TYPE == RTW_FRAME_TYPE_ASOC_REQ)) ? true : false
|
|
#define RTW_IS_ASOC_REQ_PKT(_TYPE) \
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((_TYPE == RTW_FRAME_TYPE_REASOC_REQ) || \
|
(_TYPE == RTW_FRAME_TYPE_ASOC_REQ)) ? true : false
|
|
#define RTW_IS_BEACON_OR_PROBE_RESP_PKT(_TYPE) \
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((_TYPE == RTW_FRAME_TYPE_BEACON) || \
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(_TYPE == RTW_FRAME_TYPE_PROBE_RESP)) ? true : false
|
|
#define TU 1024 /* Time Unit (TU): 1024 us*/
|
|
#define RTW_MAX_ETH_PKT_LEN 1536
|
|
#define WL_SEQ_MASK 0xfff /* PHL_RXSC_AMPDU */
|
|
#define RX_DESC_PPDU_T_LCCK 0
|
#define RX_DESC_PPDU_T_SCCK 1
|
#define RX_DESC_PPDU_T_OFDM 2
|
#define RX_DESC_PPDU_T_HT 3
|
#define RX_DESC_PPDU_T_HTGF 4
|
#define RX_DESC_PPDU_T_VHT_SU 5
|
#define RX_DESC_PPDU_T_VHT_MU 6
|
#define RX_DESC_PPDU_T_HE_SU 7
|
#define RX_DESC_PPDU_T_HE_ERSU 8
|
#define RX_DESC_PPDU_T_HE_MU 9
|
#define RX_DESC_PPDU_T_HE_TB 10
|
#define RX_DESC_PPDU_T_UNKNOWN 15
|
|
#endif /*_RTW_GENERAL_DEF_H_*/
|
