/******************************************************************************
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*
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* Copyright(c) 2019 - 2021 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef _PHL_STRUCT_H_
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#define _PHL_STRUCT_H_
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#define PHL_STA_TID_NUM (16) /* TODO: */
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struct hci_info_t {
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/* enum rtw_hci_type hci_type; */
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#if defined(CONFIG_PCI_HCI)
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u8 total_txch_num;
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u8 total_rxch_num;
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u8 *txbd_buf;
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u8 *rxbd_buf;
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#if defined(PCIE_TRX_MIT_EN)
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u8 fixed_mitigation; /*no watchdog dynamic setting*/
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u8 rx_mit_counter_high;
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u32 rx_mit_timer_high;
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#endif
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void *wd_dma_pool;
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void *h2c_dma_pool;
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#elif defined(CONFIG_USB_HCI)
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u16 usb_bulkout_size;
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#elif defined(CONFIG_SDIO_HCI)
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u32 tx_drop_cnt; /* bit31 means overflow or not */
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#ifdef SDIO_TX_THREAD
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_os_sema tx_thrd_sema;
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_os_thread tx_thrd;
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#ifdef CONFIG_PHL_SDIO_TX_CB_THREAD
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#ifndef RTW_WKARD_SDIO_TX_USE_YIELD
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_os_lock tx_buf_lock;
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_os_event *tx_buf_event;
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#endif /* !RTW_WKARD_SDIO_TX_USE_YIELD */
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#endif /* CONFIG_PHL_SDIO_TX_CB_THREAD */
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#endif /* SDIO_TX_THREAD */
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#endif
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u8 *wd_ring;
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u8 *txbuf_pool;
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u8 *rxbuf_pool;
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u8 *wp_tag;
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u16 wp_seq[PHL_MACID_MAX_NUM]; /* maximum macid number */
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};
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#define MAX_PHL_RING_STATUS_NUMBER PHL_MACID_MAX_NUM
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#define RX_REORDER_RING_NUMBER PHL_MACID_MAX_NUM
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#define PCIE_BUS_EFFICIENCY 4
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#define ETH_ALEN 6
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struct phl_ring_status {
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_os_list list;
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u8 band;/*0 or 1*/
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u8 wmm;/*0 or 1*/
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u8 port;
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/*u8 mbssid*/
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u16 req_busy;
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struct rtw_phl_tx_ring *ring_ptr;
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};
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struct phl_ring_sts_pool {
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struct phl_ring_status ring_sts[MAX_PHL_RING_STATUS_NUMBER];
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_os_list idle;
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_os_list busy;
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_os_lock idle_lock;
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_os_lock busy_lock;
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};
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/**
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* struct phl_hci_trx_ops - interface specific operations
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*
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* @hci_trx_init: the function for HCI trx init
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* @hci_trx_deinit: the function for HCI trx deinit
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* @prepare_tx: prepare packets for hal transmission
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* @recycle_rx_buf: recycle rx buffer
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* @tx: tx packet to hw
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* @rx: rx packet to sw
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*/
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struct phl_info_t;
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struct phl_hci_trx_ops {
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enum rtw_phl_status (*hci_trx_init)(struct phl_info_t *phl);
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void (*hci_trx_deinit)(struct phl_info_t *phl);
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enum rtw_phl_status (*prepare_tx)(struct phl_info_t *phl,
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struct rtw_xmit_req *tx_req);
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enum rtw_phl_status (*recycle_rx_buf)(struct phl_info_t *phl,
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void *r, u8 ch, enum rtw_rx_type type);
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enum rtw_phl_status (*tx)(struct phl_info_t *phl);
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enum rtw_phl_status (*rx)(struct phl_info_t *phl);
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enum rtw_phl_status (*trx_cfg)(struct phl_info_t *phl);
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void (*trx_stop)(struct phl_info_t *phl);
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enum rtw_phl_status (*pltfm_tx)(struct phl_info_t *phl, void *pkt);
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void (*free_h2c_pkt_buf)(struct phl_info_t *phl_info,
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struct rtw_h2c_pkt *_h2c_pkt);
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enum rtw_phl_status (*alloc_h2c_pkt_buf)(struct phl_info_t *phl_info,
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struct rtw_h2c_pkt *_h2c_pkt, u32 buf_len);
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void (*trx_reset)(struct phl_info_t *phl, u8 type);
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void (*trx_resume)(struct phl_info_t *phl, u8 type);
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void (*tx_reset_hwband)(struct phl_info_t *phl_info, enum phl_band_idx band_idx);
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void (*req_tx_stop)(struct phl_info_t *phl);
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void (*req_rx_stop)(struct phl_info_t *phl);
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bool (*is_tx_pause)(struct phl_info_t *phl);
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bool (*is_rx_pause)(struct phl_info_t *phl);
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void *(*get_txbd_buf)(struct phl_info_t *phl);
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void *(*get_rxbd_buf)(struct phl_info_t *phl);
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void (*recycle_rx_pkt)(struct phl_info_t *phl,
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struct rtw_phl_rx_pkt *phl_rx);
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void (*rx_handle_normal)(struct phl_info_t *phl_info,
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struct rtw_phl_rx_pkt *phl_rx);
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void (*tx_watchdog)(struct phl_info_t *phl_info);
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#ifdef CONFIG_PCI_HCI
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enum rtw_phl_status (*recycle_busy_wd)(struct phl_info_t *phl);
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enum rtw_phl_status (*recycle_busy_h2c)(struct phl_info_t *phl);
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void (*return_tx_wps)(struct phl_info_t *phl);
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void (*read_hw_rx)(struct phl_info_t *phl);
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#endif
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#ifdef CONFIG_USB_HCI
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enum rtw_phl_status (*pend_rxbuf)(struct phl_info_t *phl, void *rxobj,
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u32 inbuf_len, u8 status_code);
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enum rtw_phl_status (*recycle_tx_buf)(void *phl, u8 *tx_buf_ptr);
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#endif
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#if defined(CONFIG_SDIO_HCI) && defined(CONFIG_PHL_SDIO_READ_RXFF_IN_INT)
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enum rtw_phl_status (*recv_rxfifo)(struct phl_info_t *phl);
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#endif
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#ifdef CONFIG_PCI_HCI
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void (*dump_wd_info)(struct phl_info_t *phl, u32 val);
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#endif
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};
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/**
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* struct phl_tid_ampdu_rx - TID aggregation information (Rx).
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*
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* @reorder_buf: buffer to reorder incoming aggregated MPDUs.
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* @reorder_time: time when frame was added
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* @sta: station we are attached to
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* @head_seq_num: head sequence number in reordering buffer.
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* @stored_mpdu_num: number of MPDUs in reordering buffer
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* @ssn: Starting Sequence Number expected to be aggregated.
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* @buf_size: buffer size for incoming A-MPDUs
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* @timeout: reset timer value (in TUs).
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* @tid: TID number
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* @started: this session has started (head ssn or higher was received)
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*/
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struct phl_tid_ampdu_rx {
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struct rtw_phl_rx_pkt **reorder_buf;
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u32 *reorder_time;
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struct rtw_phl_stainfo_t *sta;
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u16 head_seq_num;
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u16 stored_mpdu_num;
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u16 ssn;
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u16 buf_size;
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u16 tid;
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u8 started:1,
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removed:1,
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sleep:1;
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void *drv_priv;
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struct phl_info_t *phl_info;
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};
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#ifdef DEBUG_PHL_RX
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struct phl_rx_stats {
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u32 rx_isr;
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u32 phl_rx;
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u32 rx_type_all;
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u32 rx_type_wifi;
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u32 rx_type_ppdu;
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u32 rx_type_wp;
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u32 rx_type_c2h;
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u32 rx_amsdu;
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u32 rx_dont_reorder;
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u32 rx_put_reorder;
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u32 rx_drop_get;
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u32 rx_rdy_fail;
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u32 rxbd_fail;
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u32 rx_drop_reorder;
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u32 reorder_seq_less;
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u32 reorder_dup;
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#ifdef PHL_RXSC_AMPDU
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u32 rxsc_ampdu[3];
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#endif
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u32 rx_pkt_core;
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u32 rx_pktsz_phl;
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u32 rx_pktsz_core;
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#ifdef CONFIG_DYNAMIC_RX_BUF
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u32 rxbuf_empty;
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#endif
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};
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#endif /* DEBUG_PHL_RX */
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struct macid_ctl_t {
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_os_lock lock;
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/* used macid bitmap share for all wifi role */
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u32 used_map[PHL_MACID_MAX_ARRAY_NUM];
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u32 used_mld_map[PHL_MACID_MAX_ARRAY_NUM];
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u32 used_legacy_map[PHL_MACID_MAX_ARRAY_NUM];
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/* record bmc macid bitmap for all wifi role */
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u32 bmc_map[PHL_MACID_MAX_ARRAY_NUM];
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/* record used macid bitmap for each wifi role */
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u32 wifi_role_usedmap[MAX_WIFI_ROLE_NUMBER][PHL_MACID_MAX_ARRAY_NUM];
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/* record bmc TX macid for wifi role */
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u16 wrole_bmc[MAX_WIFI_ROLE_NUMBER][RTW_RLINK_MAX];
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/* record total stainfo by macid */
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struct rtw_phl_stainfo_t *sta[PHL_MACID_MAX_NUM];
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u16 max_num;
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};
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struct stainfo_ctl_t {
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struct phl_info_t *phl_info;
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u8 *allocated_stainfo_buf;
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int allocated_stainfo_sz;
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u8 *stainfo_buf;
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struct phl_queue free_sta_queue;
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};
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struct mld_ctl_t {
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struct phl_info_t *phl_info;
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u8 *allocated_mld_buf;
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int allocated_mld_sz;
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u8 *mld_buf;
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struct phl_queue free_mld_queue;
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};
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struct phl_h2c_pkt_pool {
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struct rtw_h2c_pkt *h2c_pkt_buf;
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struct phl_queue idle_h2c_pkt_cmd_list;
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struct phl_queue idle_h2c_pkt_data_list;
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struct phl_queue idle_h2c_pkt_ldata_list;
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struct phl_queue busy_h2c_pkt_list;
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_os_lock recycle_lock;
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};
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struct gtimer_ctx {
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u8 en;
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u8 timer_type;
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u32 duration;
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};
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#define _GT3_ENABLE 1
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#define _GT3_DISABLE 0
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#define _GT3_TYPE_SH_TASK 1
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struct lifetime_ctx {
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u8 hw_band;
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u8 en;
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u16 val;
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};
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#define _LIFETIME_ENABLE 1
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#define _LIFETIME_DISABLE 0
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struct power_offset_ctx {
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u8 hw_band;
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s8 ofst_mode;
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s8 ofst_bw;
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};
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enum phl_tx_status {
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PHL_TX_STATUS_IDLE = 0,
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PHL_TX_STATUS_RUNNING = 1,
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PHL_TX_STATUS_STOP_INPROGRESS = 2,
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PHL_TX_STATUS_SW_PAUSE = 3,
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PHL_TX_STATUS_MAX = 0xFF
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};
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enum phl_rx_status {
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PHL_RX_STATUS_IDLE = 0,
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PHL_RX_STATUS_RUNNING = 1,
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PHL_RX_STATUS_STOP_INPROGRESS = 2,
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PHL_RX_STATUS_SW_PAUSE = 3,
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PHL_RX_STATUS_MAX = 0xFF
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};
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enum data_ctrl_mdl {
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DATA_CTRL_MDL_NONE = 0,
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DATA_CTRL_MDL_CMD_CTRLER = BIT0,
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DATA_CTRL_MDL_SER = BIT1,
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DATA_CTRL_MDL_PS = BIT2,
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DATA_CTRL_MDL_MRC = BIT3,
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DATA_CTRL_MDL_ECSA = BIT4,
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DATA_CTRL_MDL_MAX = BIT7
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};
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enum data_ctrl_err_code {
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CTRL_ERR_SW_TX_PAUSE_POLLTO = 1,
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CTRL_ERR_SW_TX_PAUSE_FAIL = 2,
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CTRL_ERR_SW_TX_RESUME_FAIL = 3,
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CTRL_ERR_SW_RX_PAUSE_POLLTO = 4,
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CTRL_ERR_SW_RX_PAUSE_FAIL = 5,
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CTRL_ERR_SW_RX_RESUME_FAIL = 6,
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CTRL_ERR_HW_TRX_PAUSE_FAIL = 7,
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CTRL_ERR_HW_TRX_RESUME_FAIL = 8,
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CTRL_ERR_MAX = 0xFF
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};
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#ifdef CONFIG_POWER_SAVE
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struct phl_ps_info {
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bool init;
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_os_atomic tx_ntfy;
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};
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#endif
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#define PHL_CTRL_TX BIT0
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#define PHL_CTRL_RX BIT1
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#define PHL_CTRL_IN_PIPE BIT2
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#define PHL_CTRL_OUT_PIPE BIT3
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#define POLL_SW_TX_PAUSE_MAX_MS 500
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#define POLL_SW_RX_PAUSE_MAX_MS 500
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#if defined(CONFIG_VW_REFINE) || defined(CONFIG_ONE_TXQ)
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#define WP_MAX_CNT 4096
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#define WP_USED_SEQ 0xFFFF
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#endif
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struct phl_info_t {
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struct macid_ctl_t macid_ctrl;
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struct stainfo_ctl_t sta_ctrl;
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struct mld_ctl_t mld_ctrl;
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struct phl_acs_info *acs_info;
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struct rtw_regulation_interface rg_interface;
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struct rtw_phl_com_t *phl_com;
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struct rtw_phl_handler phl_tx_handler;
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struct rtw_phl_handler phl_rx_handler;
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struct rtw_phl_handler phl_ser_handler;
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struct rtw_phl_handler phl_event_handler;
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struct rtw_phl_rx_ring phl_rx_ring;
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_os_atomic phl_sw_tx_sts;
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_os_atomic phl_sw_tx_more;
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_os_atomic phl_sw_tx_req_pwr;
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_os_atomic phl_sw_rx_sts;
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_os_atomic phl_sw_rx_more;
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_os_atomic phl_sw_rx_req_pwr;
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_os_atomic is_hw_trx_pause;
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enum data_ctrl_mdl pause_tx_id;
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enum data_ctrl_mdl pause_rx_id;
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_os_lock t_ring_list_lock;
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_os_lock rx_ring_lock;
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_os_lock t_fctrl_result_lock;
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_os_list t_ring_list;
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_os_list t_fctrl_result;
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struct phl_queue t_ring_free_q;
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void *ring_sts_pool;
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void *rx_pkt_pool;
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struct phl_h2c_pkt_pool *h2c_pool;
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struct hci_info_t *hci;
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struct phl_hci_trx_ops *hci_trx_ops;
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struct pkt_ofld_obj *pkt_ofld;
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struct phl_cmd_dispatch_engine disp_eng;
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struct phl_watchdog wdog;
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void *msg_hub;
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void *cmd_que;
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void *hal;
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#ifdef CONFIG_FSM
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void *fsm_root;
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void *cmd_fsm;
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void *cmd_obj;
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void *ser_fsm;
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void *ser_obj;
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void *snd_fsm;
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#endif /*CONFIG_FSM*/
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void *snd_obj;
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void *ps_obj;
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void *led_ctrl;
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void *ecsa_ctrl;
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#ifdef CONFIG_PHL_TDLS
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struct phl_tdls_info_t tdls_info;
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#endif
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void *phl_twt_info; /* struct phl_twt_info */
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#ifdef PHL_RX_BATCH_IND
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u8 rx_new_pending;
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#endif
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#ifdef DEBUG_PHL_RX
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struct phl_rx_stats rx_stats;
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u32 cnt_rx_pktsz;
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#endif
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struct phl_wow_info wow_info;
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#ifdef CONFIG_POWER_SAVE
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struct phl_ps_info ps_info;
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#endif
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#ifdef CONFIG_PHL_TEST_SUITE
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void *trx_test;
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struct rtw_phl_handler sw_tx_handler;
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#endif
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struct gtimer_ctx gt3_ctx;
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struct lifetime_ctx lt_ctx;
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struct power_offset_ctx pwr_ofst_ctx;
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#if defined(CONFIG_VW_REFINE) || defined(CONFIG_ONE_TXQ)
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u16 free_wp[WP_MAX_CNT];
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u16 fw_ptr, fr_ptr; /* wp management r/w ptr */
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#endif
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u8 use_onetxring;
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};
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#define phl_to_drvpriv(_phl) (_phl->phl_com->drv_priv)
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#define phlcom_to_test_mgnt(_phl_com) ((_phl_com)->test_mgnt)
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#define phlcom_to_mr_ctrl(_phl_com) (&(_phl_com->mr_ctrl))
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#define phl_to_mr_ctrl(_phl) (&(((struct phl_info_t *)_phl)->phl_com->mr_ctrl))
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#define phl_to_mac_ctrl(_phlinfo) (&(_phlinfo->macid_ctrl))
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#define phl_to_sta_ctrl(_phlinfo) (&(_phlinfo->sta_ctrl))
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#define get_band_ctrl(_phl, _band) (&(phl_to_mr_ctrl(_phl)->band_ctrl[_band]))
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#define phl_to_p2pps_info(_phl) (((_phl)->phl_com->p2pps_info))
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#define get_role_idx(_wrole) (_wrole->id)
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#define phl_to_mld_ctrl(_phlinfo) (&(_phlinfo->mld_ctrl))
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#define get_rlink(_wrole, _idx) (&(_wrole->rlink[_idx]))
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#endif /*_PHL_STRUCT_H_*/
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