/******************************************************************************
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*
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* Copyright(c) 2019 - 2021 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef _PHL_CHAN_INFO_DEF_H_
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#define _PHL_CHAN_INFO_DEF_H_
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#ifdef CONFIG_PHL_CHANNEL_INFO
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#ifdef CONFIG_WKARD_CSI_PKT_SIZE
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#define CHAN_INFO_MAX_SIZE 2048
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#define MAX_CHAN_INFO_PKT_KEEP 10
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#else
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#define CHAN_INFO_MAX_SIZE 65535
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#define MAX_CHAN_INFO_PKT_KEEP 2
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#endif
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#define CHAN_INFO_PKT_TOTAL MAX_CHAN_INFO_PKT_KEEP + 1
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#define MAX_CHAN_INFO_CLIENT PHL_MACID_MAX_NUM
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#define MAX_CHAN_INFO_CLIENT_ARR_SZ (MAX_CHAN_INFO_CLIENT >> 3)
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struct csi_header_t {
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u8 mac_addr[6]; /* mdata: u8 ta[6]? */
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u32 hw_assigned_timestamp; /* mdata: u32 freerun_cnt */
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u8 channel; /* Drv define */
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u8 bandwidth; /* mdata: u8 bw */
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u16 rx_data_rate; /* mdata: u16 rx_rate */
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u8 nc; /* ch_rpt_hdr_info */
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u8 nr; /* ch_rpt_hdr_info */
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u16 num_sub_carrier; /* Drv define*/
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u8 num_bit_per_tone; /* Drv define per I/Q */
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u8 avg_idle_noise_pwr; /* ch_rpt_hdr_info */
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u8 evm[2]; /* ch_rpt_hdr_info */
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u8 rssi[2]; /* phy_info_rpt */
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u32 csi_data_length; /* ch_rpt_hdr_info */
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u8 rxsc; /* phy_info_rpt */
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u8 ch_matrix_report; /* mdata: u8 get_ch_info */
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u8 csi_valid; /* ch_rpt_hdr_info */
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};
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struct chan_info_t {
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_os_list list;
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u8* chan_info_buffer;
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u32 length;
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struct csi_header_t csi_header;
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};
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struct rx_chan_info_pool {
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struct chan_info_t channl_info_pkt[CHAN_INFO_PKT_TOTAL];
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_os_list idle;
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_os_list busy;
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_os_lock idle_lock; /* spinlock */
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_os_lock busy_lock; /* spinlock */
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u32 idle_cnt;
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u32 busy_cnt;
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};
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enum phl_chinfo_action {
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CHINFO_ACT_EN,/*enable or disable*/
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CHINFO_ACT_CFG,
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CHINFO_ACT_MAX
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};
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enum phl_chinfo_group_num {
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CHINFO_GROUP_NUM_1 = 0,
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CHINFO_GROUP_NUM_2,
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CHINFO_GROUP_NUM_4,
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CHINFO_GROUP_NUM_16,
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CHINFO_GROUP_NUM_MAX
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};
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enum phl_chinfo_mode {
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CHINFO_MODE_ACK,
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CHINFO_MODE_MACID,
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CHINFO_MODE_NDP,
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CHINFO_MODE_MAX,
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};
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/*
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Compression (I/Q bits)
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CHINFO_ACCU_1BYTE: S(8,4),
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CHINFO_ACCU_2BYTES: S(16,12)
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*/
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enum phl_chinfo_accuracy {
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CHINFO_ACCU_1BYTE = 0,
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CHINFO_ACCU_2BYTES,
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CHINFO_ACCU_MAX,
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};
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enum phl_chinfo_enable_mode {
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CHINFO_EN_LIGHT_MODE= 0,
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CHINFO_EN_RICH_MODE,
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CHINFO_EN_AUTO_MODE,
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CHINFO_EN_RICH_MAX,
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};
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struct rtw_chinfo_action_parm {
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struct rtw_phl_stainfo_t *sta;
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enum phl_chinfo_group_num group_num;
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enum phl_chinfo_mode mode;
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enum phl_chinfo_enable_mode enable_mode;
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enum phl_chinfo_action act;
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enum phl_chinfo_accuracy accuracy;
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#ifdef CONFIG_PHL_CHANNEL_INFO_DBG
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u32 ele_bitmap;
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#endif
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u8 enable;
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u16 trig_period;
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u8 tx_nss;
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u8 rx_nss;
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#ifdef CONFIG_PHL_WKARD_CHANNEL_INFO_ACK
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/* decided by core layer */
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u8 chk_ack_rate;
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#endif
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#ifdef CONFIG_PHL_WKARD_CHANNEL_INFO_SAP
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u8 ap_csi;
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u8 assign_client_mac[MAC_ALEN];
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#endif
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};
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struct rtw_chinfo_cur_parm {
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struct rtw_chinfo_action_parm action_parm;
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#ifdef CONFIG_PHL_WKARD_CHANNEL_INFO_ACK
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enum rtw_data_rate rate;
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#endif
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u8 macid_bitmap[MAX_CHAN_INFO_CLIENT_ARR_SZ];
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u8 num;
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};
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#endif
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#endif /*_PHL_CHAN_INFO_DEF_H_*/
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