/******************************************************************************
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*
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* Copyright(c) 2019 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef _HALRF_PWR_TRACK_H_
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#define _HALRF_PWR_TRACK_H_
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/*@--------------------------Define Parameters-------------------------------*/
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#define AVG_THERMAL_NUM 8
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#define MAX_RF_PATH 4
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#define DELTA_SWINGIDX_SIZE 30
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#define BAND_NUM 4
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#define BAND_NUM_6G 4
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#define DELTA_SWINTSSI_SIZE 61
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#define TSSI_EFUSE_NUM 32
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#define TSSI_BW_DIFF_EFUSE_NUM 14
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#define TSSI_HIDE_EFUSE_NUM 8
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#define TSSI_HIDE_EFUSE_NUM_6G 8
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#define AVG_THERMAL_NUM_TSSI 2
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#define MAX_CH_NUM 67
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#define TSSI_ALIMK_VAULE_NUM 8
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#define MAX_HALRF_PATH 2
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#define TSSI_EXTRA_GROUP_BIT (BIT(31))
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#define TSSI_EXTRA_GROUP(idx) (TSSI_EXTRA_GROUP_BIT | (idx))
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#define IS_TSSI_EXTRA_GROUP(group) ((group) & TSSI_EXTRA_GROUP_BIT)
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#define TSSI_EXTRA_GET_GROUP_IDX1(group) ((group) & ~TSSI_EXTRA_GROUP_BIT)
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#define TSSI_EXTRA_GET_GROUP_IDX2(group) (TSSI_EXTRA_GET_GROUP_IDX1(group) + 1)
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/*@---------------------------End Define Parameters---------------------------*/
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u8 halrf_get_limit_ch_idx_to_ch_idx(struct rf_info *rf, u8 band, u8 channel);
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enum halrf_tssi_rate_type {
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EFUSE_TSSI_CCK = 0,
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EFUSE_TSSI_MCS,
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EFUSE_TSSI_6G,
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EFUSE_TSSI_RATE_MAX
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};
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enum halrf_tssi_type{
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TSSI_OFF = 0,
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TSSI_ON,
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TSSI_CAL
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};
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enum halrf_tssi_slope_type{
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TSSI_SLOPE_DEFAULT = 0,
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TSSI_SLOPE_ON,
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TSSI_SLOPE_OFF
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};
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enum halrf_tssi_alimk_band{
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TSSI_ALIMK_2G = 0,
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TSSI_ALIMK_5GL,
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TSSI_ALIMK_5GM,
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TSSI_ALIMK_5GH,
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TSSI_ALIMK_MAX
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};
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enum halrf_tssi_dz {
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DZ_TSSI_ALIMTK_TIMEOUT = BIT(0),
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};
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struct halrf_pwr_track_info {
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/* u8 is_txpowertracking; */
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u8 tx_powercount;
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bool is_txpowertracking_init;
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bool is_txpowertracking;
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u8 txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */
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u8 tm_trigger;
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u8 internal_pa_5g[2]; /* pathA / pathB */
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u8 thermal_meter[2]; /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
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u8 thermal_value;
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u8 thermal_value_path[MAX_RF_PATH];
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u8 thermal_value_lck;
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u8 thermal_value_iqk;
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s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */
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u8 thermal_value_avg[AVG_THERMAL_NUM];
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u8 thermal_value_avg_path[MAX_RF_PATH][AVG_THERMAL_NUM];
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u8 thermal_value_avg_index;
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u8 thermal_value_avg_index_path[MAX_RF_PATH];
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s8 power_index_offset_path[MAX_RF_PATH];
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u8 thermal_value_rx_gain;
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u8 thermal_value_crystal;
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u8 thermal_value_dpk_store;
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u8 thermal_value_dpk_track;
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bool txpowertracking_in_progress;
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bool is_reloadtxpowerindex;
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u8 is_rf_pi_enable;
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u32 txpowertracking_callback_cnt; /* cosa add for debug */
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u8 is_cck_in_ch14;
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u8 CCK_index;
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u8 OFDM_index[MAX_RF_PATH];
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s8 power_index_offset;
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s8 delta_power_index;
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s8 delta_power_index_path[MAX_RF_PATH];
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s8 delta_power_index_last;
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s8 delta_power_index_last_path[MAX_RF_PATH];
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bool is_tx_power_changed;
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/*struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];*/
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u8 delta_lck;
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s8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_6ga_p[BAND_NUM_6G][DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_6ga_n[BAND_NUM_6G][DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_6gb_p[BAND_NUM_6G][DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_6gb_n[BAND_NUM_6G][DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_6gc_p[BAND_NUM_6G][DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_6gc_n[BAND_NUM_6G][DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_6gd_p[BAND_NUM_6G][DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_6gd_n[BAND_NUM_6G][DELTA_SWINGIDX_SIZE];
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s8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
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s8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
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s8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
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s8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
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s8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
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s8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
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s8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
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s8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
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s8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
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s8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
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s8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
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s8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
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s8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
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u8 bb_swing_idx_ofdm[MAX_RF_PATH];
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u8 bb_swing_idx_ofdm_current;
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u8 bb_swing_idx_ofdm_base;
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u8 bb_swing_idx_ofdm_base_path[MAX_RF_PATH];
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bool bb_swing_flag_ofdm;
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u8 bb_swing_idx_cck;
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u8 bb_swing_idx_cck_current;
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u8 bb_swing_idx_cck_base;
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u8 default_ofdm_index;
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u8 default_cck_index;
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bool bb_swing_flag_cck;
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s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
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s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
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s8 absolute_cck_swing_idx[MAX_RF_PATH];
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s8 remnant_cck_swing_idx;
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s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */
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bool modify_tx_agc_flag_path_a;
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bool modify_tx_agc_flag_path_b;
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bool modify_tx_agc_flag_path_c;
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bool modify_tx_agc_flag_path_d;
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bool modify_tx_agc_flag_path_a_cck;
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bool modify_tx_agc_flag_path_b_cck;
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s8 kfree_offset[MAX_RF_PATH];
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/*Add by Yuchen for Kfree Phydm*/
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u8 reg_rf_kfree_enable; /*for registry*/
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u8 rf_kfree_enable; /*for efuse enable check*/
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};
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struct halrf_tssi_info{
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u8 thermal[MAX_HALRF_PATH];
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u8 do_tssi_thermal[MAX_HALRF_PATH];
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s32 tssi_de[MAX_HALRF_PATH];
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u8 tssi_type[MAX_HALRF_PATH];
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s8 tssi_efuse[MAX_HALRF_PATH][EFUSE_TSSI_RATE_MAX][TSSI_EFUSE_NUM];
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s8 tssi_bw_diff_efuse[MAX_HALRF_PATH][EFUSE_TSSI_RATE_MAX][CHANNEL_WIDTH_MAX][TSSI_BW_DIFF_EFUSE_NUM];
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s8 tssi_efuse_slope_gain_diff[MAX_HALRF_PATH][EFUSE_TSSI_RATE_MAX][TSSI_EFUSE_NUM];
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s8 tssi_efuse_slope_cw_diff[MAX_HALRF_PATH][EFUSE_TSSI_RATE_MAX][TSSI_EFUSE_NUM];
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bool tssi_slope_no_pg;
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s8 tssi_trim[MAX_HALRF_PATH][TSSI_HIDE_EFUSE_NUM];
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s8 tssi_trim_6g[MAX_HALRF_PATH][TSSI_HIDE_EFUSE_NUM_6G];
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s32 tssi_xdbm;
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s8 curr_tssi_cck_de[MAX_HALRF_PATH];
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s8 curr_tssi_efuse_cck_de[MAX_HALRF_PATH];
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s8 curr_tssi_ofdm_de[MAX_HALRF_PATH];
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s8 curr_tssi_ofdm_de_20m[MAX_HALRF_PATH];
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s8 curr_tssi_ofdm_de_80m[MAX_HALRF_PATH];
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s8 curr_tssi_ofdm_de_160m[MAX_HALRF_PATH];
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s8 curr_tssi_efuse_ofdm_de[MAX_HALRF_PATH];
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s8 curr_tssi_ofdm_de_diff_20m[MAX_HALRF_PATH];
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s8 curr_tssi_ofdm_de_diff_80m[MAX_HALRF_PATH];
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s8 curr_tssi_ofdm_de_diff_160m[MAX_HALRF_PATH];
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s8 curr_tssi_trim_de[MAX_HALRF_PATH];
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s8 tssi_de_160m_adc_wa_20m;
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s8 tssi_de_160m_adc_wa_40m;
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s8 tssi_de_160m_adc_wa_80m;
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s8 tssi_de_160m_adc_wa_160m;
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bool do_tssi;
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bool base_thermal_check[MAX_HALRF_PATH];
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u32 base_thermal[MAX_HALRF_PATH];
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u32 tssi_stop_power[MAX_HALRF_PATH];
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bool tssi_tracking_check[MAX_HALRF_PATH];
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u8 ther_avg[MAX_HALRF_PATH][AVG_THERMAL_NUM_TSSI]; /*path*/
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u8 ther_avg_idx[MAX_HALRF_PATH];
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u8 ther_avg_fifo_idx[MAX_HALRF_PATH];
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u32 ther_avg_final[MAX_HALRF_PATH];
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s8 extra_ofst[MAX_HALRF_PATH];
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/*bool normal_tssi_tracking;*/
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u8 normal_tssi_tracking_times;
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u8 default_txagc_offset_check;
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u8 default_txagc_offset_times;
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u32 default_txagc_offset[MAX_HALRF_PATH];
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s16 ref_pow_ofdm; /*-> HW: s(9,2)*/
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s16 ref_pow_ofdm_offset;
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u32 high_pwr_rst_cnt;
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u8 cur_ch;
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u8 cur_bw;
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u32 backup_txagc_offset[MAX_HALRF_PATH][MAX_CH_NUM];
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u8 backup_txagc_oft_ther[MAX_HALRF_PATH][MAX_CH_NUM];
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bool check_backup_txagc[MAX_CH_NUM];
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bool check_backup_aligmk[MAX_HALRF_PATH][MAX_CH_NUM];
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u32 start_time, finish_time;
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u32 alignment_value[MAX_HALRF_PATH][TSSI_ALIMK_MAX][TSSI_ALIMK_VAULE_NUM];
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u32 alignment_backup_by_ch[MAX_HALRF_PATH][MAX_CH_NUM][TSSI_ALIMK_VAULE_NUM];
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bool alignment_done[MAX_HALRF_PATH][TSSI_ALIMK_MAX];
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u32 tssi_total_time;
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u32 tssi_alimk_time;
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u32 tssi_slope_time;
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s32 slopek_cw_diff[MAX_HALRF_PATH];
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};
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struct halrf_xtal_info{
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s8 delta_swing_xtal_table_idx_p[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_xtal_table_idx_n[DELTA_SWINGIDX_SIZE];
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};
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#endif
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