/******************************************************************************
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*
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* Copyright(c) 2019 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef _HALRF_PWR_TABLE_H_
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#define _HALRF_PWR_TABLE_H_
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/*@--------------------------Define Parameters-------------------------------*/
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#define TX_TABLE_TO_TX_PWR 4
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#define TX_PWR_BY_RATE_NUM_RF 4
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#define PW_LMT_MAX_2G_BANDWITH_NUM 2
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#define PW_LMT_MAX_CHANNEL_NUMBER_2G 14
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#define PW_LMT_MAX_CHANNEL_NUMBER_5G 53
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#define PW_LMT_MAX_CHANNEL_NUMBER_6G 120
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#define TX_PWR_BY_RATE_NUM_MAC 44
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#define TX_PWR_LIMIT_NUM_MAC 80
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#define TX_PWR_LIMIT_RU_NUM_MAC 30
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#define RADIO_TO_FW_PAGE_SIZE 6
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#define RADIO_TO_FW_DATA_SIZE 500
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/*@-----------------------End Define Parameters-----------------------*/
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/*power by rate*/
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enum halrf_pw_by_rate_para_type {
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PW_BYRATE_PARA_NSS1,
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PW_BYRATE_PARA_NSS2,
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PW_BYRATE_PARA_OFFS = 0xF
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};
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enum halrf_pw_by_rate_rate_type {
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PW_BYRATE_RATE_11M_1M = 0,
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PW_BYRATE_RATE_18M_6M = 1,
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PW_BYRATE_RATE_54M_24M = 2,
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PW_BYRATE_RATE_MCS3_0 = 3,
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PW_BYRATE_RATE_MCS7_4 = 4,
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PW_BYRATE_RATE_MCS11_8 = 5,
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PW_BYRATE_RATE_DCM4_0 = 6,
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PW_BYRATE_RATE_AllRate2_1 = 7, /* CCK, OFDM, HT, VHT */
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PW_BYRATE_RATE_AllRate2_2 = 8, /* HE_HEDCM */
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PW_BYRATE_RATE_AllRate5_1 = 9, /* OFDM, HT, VHT, HE_HEDCM */
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PW_BYRATE_RATE_AllRate6_1 = 10, /* OFDM, HT, VHT, HE_HEDCM */
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PW_BYRATE_RATE_NULL = 0xF
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};
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struct _halrf_file_regd_ext {
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u16 domain;
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char country[2];
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char reg_name[10];
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};
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/*power limit*/
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struct halrf_tx_pw_lmt {
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u8 band;
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u8 bw;
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u8 ntx;
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u8 rs;
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u8 bf;
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u8 reg;
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u8 ch;
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s8 val;
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u8 tx_shap_idx;
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};
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struct halrf_tx_pw_lmt_ru {
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u8 band;
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u8 bw;
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u8 ntx;
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u8 rs;
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u8 reg;
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u8 ch;
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s8 val;
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u8 tx_shap_idx;
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};
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enum halrf_tx_pw_lmt_ru_bandwidth_type {
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PW_LMT_RU_BW_RU26 = 0,
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PW_LMT_RU_BW_RU52,
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PW_LMT_RU_BW_RU106,
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PW_LMT_RU_BW_NULL
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};
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enum halrf_pw_lmt_regulation_type {
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PW_LMT_REGU_NULL = 0, /* declare this to 0xFF after limit array remove usage of PW_LMT_REGU_NULL */
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PW_LMT_REGU_NA = 1, /* declare this to 0xFE after limit array remove usage of PW_LMT_REGU_NA */
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PW_LMT_REGU_WW13 = 2,
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PW_LMT_REGU_INTERSECT = 3,
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PW_LMT_REGU_EXT_PWR = 4,
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/* place share index item above */
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PW_LMT_REGU_ETSI = 5,
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PW_LMT_REGU_FCC = 6,
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PW_LMT_REGU_MKK = 7,
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PW_LMT_REGU_IC = 8,
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PW_LMT_REGU_KCC = 9,
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PW_LMT_REGU_ACMA = 10,
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PW_LMT_REGU_NCC = 11,
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PW_LMT_REGU_MEXICO = 12,
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PW_LMT_REGU_CHILE = 13,
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PW_LMT_REGU_UKRAINE = 14,
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PW_LMT_REGU_CNOLD = 15,
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PW_LMT_REGU_QATAR = 16,
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PW_LMT_REGU_UK = 17,
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PW_LMT_REGU_CN = 18,
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PW_LMT_REGU_THAILAND = 19,
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/* place predefined ones above */
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PW_LMT_REGU_PREDEF_NUM,
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PW_LMT_MAX_REGULATION_NUM = 32
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};
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enum halrf_pw_lmt_regulation_type_6g {
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PW_LMT_REGU_6G_NULL = 0, /* declare this to 0xFF after limit array remove usage of PW_LMT_REGU_NULL */
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PW_LMT_REGU_6G_NA = 1, /* declare this to 0xFE after limit array remove usage of PW_LMT_REGU_NA */
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PW_LMT_REGU_6G_WW13 = 2,
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PW_LMT_REGU_6G_INTERSECT = 3,
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PW_LMT_REGU_6G_EXT_PWR = 4,
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/* place share index item above */
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PW_LMT_REGU_6G_ETSI_LPI = 5,
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PW_LMT_REGU_6G_ETSI_STD = 6,
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PW_LMT_REGU_6G_ETSI_VLP = 7,
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PW_LMT_REGU_6G_FCC_LPI = 8,
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PW_LMT_REGU_6G_FCC_STD = 9,
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PW_LMT_REGU_6G_FCC_VLP = 10,
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PW_LMT_REGU_6G_MKK_LPI = 11,
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PW_LMT_REGU_6G_MKK_STD = 12,
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PW_LMT_REGU_6G_MKK_VLP = 13,
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PW_LMT_REGU_6G_IC_LPI = 14,
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PW_LMT_REGU_6G_IC_STD = 15,
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PW_LMT_REGU_6G_IC_VLP = 16,
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PW_LMT_REGU_6G_KCC_LPI = 17,
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PW_LMT_REGU_6G_KCC_STD = 18,
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PW_LMT_REGU_6G_KCC_VLP = 19,
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PW_LMT_REGU_6G_ACMA_LPI = 20,
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PW_LMT_REGU_6G_ACMA_STD = 21,
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PW_LMT_REGU_6G_ACMA_VLP = 22,
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PW_LMT_REGU_6G_NCC_LPI = 23,
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PW_LMT_REGU_6G_NCC_STD = 24,
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PW_LMT_REGU_6G_NCC_VLP = 25,
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PW_LMT_REGU_6G_MEXICO_LPI = 26,
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PW_LMT_REGU_6G_MEXICO_STD = 27,
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PW_LMT_REGU_6G_MEXICO_VLP = 28,
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PW_LMT_REGU_6G_CHILE_LPI = 29,
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PW_LMT_REGU_6G_CHILE_STD = 30,
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PW_LMT_REGU_6G_CHILE_VLP = 31,
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PW_LMT_REGU_6G_UKRAINE_LPI = 32,
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PW_LMT_REGU_6G_UKRAINE_STD = 33,
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PW_LMT_REGU_6G_UKRAINE_VLP = 34,
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PW_LMT_REGU_6G_CNOLD_LPI = 35,
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PW_LMT_REGU_6G_CNOLD_STD = 36,
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PW_LMT_REGU_6G_CNOLD_VLP = 37,
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PW_LMT_REGU_6G_QATAR_LPI = 38,
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PW_LMT_REGU_6G_QATAR_STD = 39,
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PW_LMT_REGU_6G_QATAR_VLP = 40,
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PW_LMT_REGU_6G_UK_LPI = 41,
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PW_LMT_REGU_6G_UK_STD = 42,
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PW_LMT_REGU_6G_UK_VLP = 43,
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PW_LMT_REGU_6G_CN_LPI = 44,
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PW_LMT_REGU_6G_CN_STD = 45,
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PW_LMT_REGU_6G_CN_VLP = 46,
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PW_LMT_REGU_6G_THAILAND_LPI = 47,
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PW_LMT_REGU_6G_THAILAND_STD = 48,
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PW_LMT_REGU_6G_THAILAND_VLP = 49,
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/* place predefined ones above */
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PW_LMT_REGU_6G_PREDEF_NUM = 50,
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PW_LMT_MAX_6G_REGULATION_NUM = 51
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};
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#define PW_LMT_MAX_PER_BAND_REGU_NUM ((u8)PW_LMT_MAX_REGULATION_NUM > (u8)PW_LMT_MAX_6G_REGULATION_NUM ? PW_LMT_MAX_REGULATION_NUM : PW_LMT_MAX_6G_REGULATION_NUM)
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enum halrf_tx_shape_modu_type {
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TX_SHAPE_CCK,
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TX_SHAPE_OFDM,
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TX_SHAPE_MAX
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};
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enum halrf_pw_lmt_band_type {
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PW_LMT_BAND_2_4G = 0,
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PW_LMT_BAND_5G = 1,
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PW_LMT_BAND_6G = 2,
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PW_LMT_MAX_BAND = 3
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};
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enum halrf_pw_lmt_bandwidth_type {
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PW_LMT_BW_20M = 0,
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PW_LMT_BW_40M = 1,
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PW_LMT_BW_80M = 2,
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PW_LMT_BW_160M = 3,
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PW_LMT_MAX_BANDWIDTH_NUM = 4
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};
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enum halrf_pw_lmt_ratesection_type {
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PW_LMT_RS_CCK = 0,
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PW_LMT_RS_OFDM = 1,
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PW_LMT_RS_HT = 2,
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PW_LMT_RS_VHT = 3,
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PW_LMT_RS_HE = 4,
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PW_LMT_MAX_RS_NUM = 5
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};
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enum halrf_pw_lmt_rfpath_type {
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PW_LMT_PH_1T = 0,
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PW_LMT_PH_2T = 1,
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PW_LMT_PH_3T = 2,
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PW_LMT_PH_4T = 3,
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PW_LMT_MAX_PH_NUM = 4
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};
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enum halrf_pw_lmt_beamforming_type {
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PW_LMT_NONBF = 0,
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PW_LMT_BF = 1,
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PW_LMT_MAX_BF_NUM = 2
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};
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enum halrf_data_rate {
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HALRF_DATA_RATE_CCK1 = 0,
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HALRF_DATA_RATE_CCK2 = 0x1,
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HALRF_DATA_RATE_CCK5_5,
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HALRF_DATA_RATE_CCK11,
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HALRF_DATA_RATE_OFDM6,
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HALRF_DATA_RATE_OFDM9,
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HALRF_DATA_RATE_OFDM12,
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HALRF_DATA_RATE_OFDM18,
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HALRF_DATA_RATE_OFDM24,
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HALRF_DATA_RATE_OFDM36,
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HALRF_DATA_RATE_OFDM48 = 10,
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HALRF_DATA_RATE_OFDM54,
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HALRF_DATA_RATE_MCS0,
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HALRF_DATA_RATE_MCS1,
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HALRF_DATA_RATE_MCS2,
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HALRF_DATA_RATE_MCS3,
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HALRF_DATA_RATE_MCS4,
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HALRF_DATA_RATE_MCS5,
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HALRF_DATA_RATE_MCS6,
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HALRF_DATA_RATE_MCS7,
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HALRF_DATA_RATE_MCS8 = 20,
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HALRF_DATA_RATE_MCS9,
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HALRF_DATA_RATE_MCS10,
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HALRF_DATA_RATE_MCS11,
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HALRF_DATA_RATE_MCS12,
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HALRF_DATA_RATE_MCS13,
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HALRF_DATA_RATE_MCS14,
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HALRF_DATA_RATE_MCS15,
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HALRF_DATA_RATE_MCS16,
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HALRF_DATA_RATE_MCS17,
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HALRF_DATA_RATE_MCS18 = 30,
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HALRF_DATA_RATE_MCS19,
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HALRF_DATA_RATE_MCS20,
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HALRF_DATA_RATE_MCS21,
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HALRF_DATA_RATE_MCS22,
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HALRF_DATA_RATE_MCS23,
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HALRF_DATA_RATE_MCS24,
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HALRF_DATA_RATE_MCS25,
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HALRF_DATA_RATE_MCS26,
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HALRF_DATA_RATE_MCS27,
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HALRF_DATA_RATE_MCS28 = 40,
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HALRF_DATA_RATE_MCS29,
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HALRF_DATA_RATE_MCS30,
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HALRF_DATA_RATE_MCS31,
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HALRF_DATA_RATE_VHT_NSS1_MCS0,
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HALRF_DATA_RATE_VHT_NSS1_MCS1,
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HALRF_DATA_RATE_VHT_NSS1_MCS2,
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HALRF_DATA_RATE_VHT_NSS1_MCS3,
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HALRF_DATA_RATE_VHT_NSS1_MCS4,
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HALRF_DATA_RATE_VHT_NSS1_MCS5,
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HALRF_DATA_RATE_VHT_NSS1_MCS6 = 50,
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HALRF_DATA_RATE_VHT_NSS1_MCS7,
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HALRF_DATA_RATE_VHT_NSS1_MCS8,
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HALRF_DATA_RATE_VHT_NSS1_MCS9,
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HALRF_DATA_RATE_VHT_NSS2_MCS0,
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HALRF_DATA_RATE_VHT_NSS2_MCS1,
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HALRF_DATA_RATE_VHT_NSS2_MCS2,
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HALRF_DATA_RATE_VHT_NSS2_MCS3,
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HALRF_DATA_RATE_VHT_NSS2_MCS4,
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HALRF_DATA_RATE_VHT_NSS2_MCS5,
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HALRF_DATA_RATE_VHT_NSS2_MCS6 = 60,
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HALRF_DATA_RATE_VHT_NSS2_MCS7,
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HALRF_DATA_RATE_VHT_NSS2_MCS8,
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HALRF_DATA_RATE_VHT_NSS2_MCS9,
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HALRF_DATA_RATE_VHT_NSS3_MCS0,
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HALRF_DATA_RATE_VHT_NSS3_MCS1,
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HALRF_DATA_RATE_VHT_NSS3_MCS2,
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HALRF_DATA_RATE_VHT_NSS3_MCS3,
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HALRF_DATA_RATE_VHT_NSS3_MCS4,
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HALRF_DATA_RATE_VHT_NSS3_MCS5,
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HALRF_DATA_RATE_VHT_NSS3_MCS6 = 70,
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HALRF_DATA_RATE_VHT_NSS3_MCS7,
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HALRF_DATA_RATE_VHT_NSS3_MCS8,
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HALRF_DATA_RATE_VHT_NSS3_MCS9,
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HALRF_DATA_RATE_VHT_NSS4_MCS0,
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HALRF_DATA_RATE_VHT_NSS4_MCS1,
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HALRF_DATA_RATE_VHT_NSS4_MCS2,
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HALRF_DATA_RATE_VHT_NSS4_MCS3,
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HALRF_DATA_RATE_VHT_NSS4_MCS4,
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HALRF_DATA_RATE_VHT_NSS4_MCS5,
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HALRF_DATA_RATE_VHT_NSS4_MCS6 = 80,
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HALRF_DATA_RATE_VHT_NSS4_MCS7,
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HALRF_DATA_RATE_VHT_NSS4_MCS8,
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HALRF_DATA_RATE_VHT_NSS4_MCS9,
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HALRF_DATA_RATE_HE_NSS1_MCS0,
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HALRF_DATA_RATE_HE_NSS1_MCS1,
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HALRF_DATA_RATE_HE_NSS1_MCS2,
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HALRF_DATA_RATE_HE_NSS1_MCS3,
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HALRF_DATA_RATE_HE_NSS1_MCS4,
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HALRF_DATA_RATE_HE_NSS1_MCS5,
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HALRF_DATA_RATE_HE_NSS1_MCS6 = 90,
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HALRF_DATA_RATE_HE_NSS1_MCS7,
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HALRF_DATA_RATE_HE_NSS1_MCS8,
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HALRF_DATA_RATE_HE_NSS1_MCS9,
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HALRF_DATA_RATE_HE_NSS1_MCS10,
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HALRF_DATA_RATE_HE_NSS1_MCS11,
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HALRF_DATA_RATE_HE_NSS2_MCS0,
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HALRF_DATA_RATE_HE_NSS2_MCS1,
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HALRF_DATA_RATE_HE_NSS2_MCS2,
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HALRF_DATA_RATE_HE_NSS2_MCS3,
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HALRF_DATA_RATE_HE_NSS2_MCS4 = 100,
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HALRF_DATA_RATE_HE_NSS2_MCS5,
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HALRF_DATA_RATE_HE_NSS2_MCS6,
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HALRF_DATA_RATE_HE_NSS2_MCS7,
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HALRF_DATA_RATE_HE_NSS2_MCS8,
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HALRF_DATA_RATE_HE_NSS2_MCS9,
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HALRF_DATA_RATE_HE_NSS2_MCS10,
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HALRF_DATA_RATE_HE_NSS2_MCS11,
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HALRF_DATA_RATE_HE_NSS3_MCS0,
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HALRF_DATA_RATE_HE_NSS3_MCS1,
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HALRF_DATA_RATE_HE_NSS3_MCS2 = 110,
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HALRF_DATA_RATE_HE_NSS3_MCS3,
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HALRF_DATA_RATE_HE_NSS3_MCS4,
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HALRF_DATA_RATE_HE_NSS3_MCS5,
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HALRF_DATA_RATE_HE_NSS3_MCS6,
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HALRF_DATA_RATE_HE_NSS3_MCS7,
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HALRF_DATA_RATE_HE_NSS3_MCS8,
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HALRF_DATA_RATE_HE_NSS3_MCS9,
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HALRF_DATA_RATE_HE_NSS3_MCS10,
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HALRF_DATA_RATE_HE_NSS3_MCS11,
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HALRF_DATA_RATE_HE_NSS4_MCS0 = 120,
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HALRF_DATA_RATE_HE_NSS4_MCS1,
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HALRF_DATA_RATE_HE_NSS4_MCS2,
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HALRF_DATA_RATE_HE_NSS4_MCS3,
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HALRF_DATA_RATE_HE_NSS4_MCS4,
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HALRF_DATA_RATE_HE_NSS4_MCS5,
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HALRF_DATA_RATE_HE_NSS4_MCS6,
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HALRF_DATA_RATE_HE_NSS4_MCS7,
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HALRF_DATA_RATE_HE_NSS4_MCS8,
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HALRF_DATA_RATE_HE_NSS4_MCS9,
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HALRF_DATA_RATE_HE_NSS4_MCS10 = 130,
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HALRF_DATA_RATE_HE_NSS4_MCS11,
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HALRF_DATA_RATE_HEDCM_NSS1_MCS0,
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HALRF_DATA_RATE_HEDCM_NSS1_MCS1,
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HALRF_DATA_RATE_HEDCM_NSS1_MCS3,
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HALRF_DATA_RATE_HEDCM_NSS1_MCS4,
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HALRF_DATA_RATE_HEDCM_NSS2_MCS0,
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HALRF_DATA_RATE_HEDCM_NSS2_MCS1,
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HALRF_DATA_RATE_HEDCM_NSS2_MCS3,
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HALRF_DATA_RATE_HEDCM_NSS2_MCS4,
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HALRF_DATA_RATE_HEDCM_OFFSET = 140,
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HALRF_DATA_RATE_VHT_OFFSET,
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HALRF_DATA_RATE_HT_OFFSET,
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HALRF_DATA_RATE_OFDM_OFFSET,
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HALRF_DATA_RATE_CCK_OFFSET,
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HALRF_DATA_RATE_MAX
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};
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enum halrf_pw_lmt_6g_type {
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PW_LMT_6G_LOW = 0,
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PW_LMT_6G_STD = 1,
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PW_LMT_6G_VLOW = 2,
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PW_LMT_6G_MAX
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};
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enum halrf_pw_lmt_tbl_ru {
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PW_LMT_TBL_NONE_RU = 0,
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PW_LMT_TBL_RU = 1,
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PW_LMT_TBL_RU_MAX
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};
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enum halrf_pw_lmt_tbl_band {
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PW_LMT_TBL = 0,
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PW_LMT_TBL_6G = 1,
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PW_LMT_TBL_BAND_MAX
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};
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struct halrf_pwr_info {
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/*Power by Rate and Power Limit Switch*/
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u8 pwr_table_switch_efuse;
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u8 pwr_by_rate_switch;
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u8 pwr_limit_switch;
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// bool regulation[PW_LMT_MAX_BAND][PW_LMT_MAX_PER_BAND_REGU_NUM];
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bool regulation[PW_LMT_MAX_BAND][PW_LMT_MAX_PER_BAND_REGU_NUM];
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u8 tx_shap_idx[PW_LMT_MAX_BAND][TX_SHAPE_MAX][PW_LMT_MAX_PER_BAND_REGU_NUM];
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u8 tx_shap_idx_ru[PW_LMT_MAX_BAND][TX_SHAPE_MAX][PW_LMT_MAX_PER_BAND_REGU_NUM];
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s8 tx_pwr_by_rate[PW_LMT_MAX_BAND][HALRF_DATA_RATE_MAX];
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s8 tx_pwr_limit_2g[PW_LMT_MAX_REGULATION_NUM][PW_LMT_MAX_2G_BANDWITH_NUM]
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[PW_LMT_MAX_RS_NUM][PW_LMT_MAX_BF_NUM][PW_LMT_MAX_CHANNEL_NUMBER_2G][MAX_HALRF_PATH];
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s8 tx_pwr_limit_5g[PW_LMT_MAX_REGULATION_NUM][PW_LMT_MAX_BANDWIDTH_NUM]
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[PW_LMT_MAX_RS_NUM][PW_LMT_MAX_BF_NUM][PW_LMT_MAX_CHANNEL_NUMBER_5G][MAX_HALRF_PATH];
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s8 tx_pwr_limit_6g[PW_LMT_MAX_6G_REGULATION_NUM][PW_LMT_MAX_BANDWIDTH_NUM]
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[PW_LMT_MAX_RS_NUM][PW_LMT_MAX_BF_NUM][PW_LMT_MAX_CHANNEL_NUMBER_6G][MAX_HALRF_PATH];
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s8 tx_pwr_limit_ru_2g[PW_LMT_MAX_REGULATION_NUM][PW_LMT_RU_BW_NULL]
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[PW_LMT_MAX_RS_NUM][PW_LMT_MAX_CHANNEL_NUMBER_2G][MAX_HALRF_PATH];
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s8 tx_pwr_limit_ru_5g[PW_LMT_MAX_REGULATION_NUM][PW_LMT_RU_BW_NULL]
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[PW_LMT_MAX_RS_NUM][PW_LMT_MAX_CHANNEL_NUMBER_5G][MAX_HALRF_PATH];
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s8 tx_pwr_limit_ru_6g[PW_LMT_MAX_6G_REGULATION_NUM][PW_LMT_RU_BW_NULL]
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[PW_LMT_MAX_RS_NUM][PW_LMT_MAX_CHANNEL_NUMBER_6G][MAX_HALRF_PATH];
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s8 tx_pwr_by_rate_mac[HW_PHY_MAX][TX_PWR_BY_RATE_NUM_MAC];
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s8 tx_pwr_limit_mac[HW_PHY_MAX][TX_PWR_LIMIT_NUM_MAC];
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s8 tx_pwr_limit_ru_mac[HW_PHY_MAX][TX_PWR_LIMIT_RU_NUM_MAC];
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s16 tx_pwr_limit_ru26_mac[HW_PHY_MAX];
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s16 tx_pwr_limit_ru52_mac[HW_PHY_MAX];
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s16 tx_pwr_limit_ru106_mac[HW_PHY_MAX];
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bool coex_pwr_ctl_enable;
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bool dpk_pwr_ctl_enable;
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s32 coex_pwr;
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s32 dpk_pwr;
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u8 mp_regulation;
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u8 regulation_idx;
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u8 regulation_str[10];
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bool fix_power[MAX_HALRF_PATH];
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s8 fix_power_dbm[MAX_HALRF_PATH];
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bool set_tx_ptrn_shap_en;
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u8 set_tx_ptrn_shap_idx[PW_LMT_MAX_BAND][TX_SHAPE_MAX];
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u16 extra_regd_idx;
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u16 extra_regd_idx_6g;
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u8 power_constraint[HW_PHY_MAX];
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s8 dpk_mcc_power;
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s8 tx_rate_power_control[HW_PHY_MAX];
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s8 max_tx_rate_power[HW_PHY_MAX];
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bool max_tx_rate_power_en;
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s8 pwr_by_rate_bw_oft[PW_LMT_MAX_BAND];
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bool pwr_by_rate_bw_oft_en;
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/*Force Regulation*/
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bool regulation_force_en;
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u8 reg_2g;
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u8 reg_5g;
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u8 reg_6g;
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u8 reg_array_2g[PW_LMT_MAX_REGULATION_NUM];
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u8 reg_array_5g[PW_LMT_MAX_REGULATION_NUM];
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u8 reg_array_6g[PW_LMT_MAX_6G_REGULATION_NUM];
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u8 reg_2g_len;
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u8 reg_5g_len;
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u8 reg_6g_len;
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s8 ext_pwr[MAX_HALRF_PATH];
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s8 ext_pwr_diff[MAX_HALRF_PATH];
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s8 ext_pwr_org[MAX_HALRF_PATH];
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s8 ext_pwr_diff_2_4g[MAX_HALRF_PATH];
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s8 ext_pwr_diff_5g_band1[MAX_HALRF_PATH];
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s8 ext_pwr_diff_5g_band2[MAX_HALRF_PATH];
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s8 ext_pwr_diff_5g_band3[MAX_HALRF_PATH];
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s8 ext_pwr_diff_5g_band4[MAX_HALRF_PATH];
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s8 ext_pwr_diff_lmt_6g_unii_5_1[MAX_HALRF_PATH];
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s8 ext_pwr_diff_lmt_6g_unii_5_2[MAX_HALRF_PATH];
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s8 ext_pwr_diff_lmt_6g_unii_6[MAX_HALRF_PATH];
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s8 ext_pwr_diff_lmt_6g_unii_7_1[MAX_HALRF_PATH];
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s8 ext_pwr_diff_lmt_6g_unii_7_2[MAX_HALRF_PATH];
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s8 ext_pwr_diff_lmt_6g_unii_8[MAX_HALRF_PATH];
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u8 power_limit_6g_type;
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u8 ant_gain_reg[PW_LMT_MAX_REGULATION_NUM];
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s8 ant_gain_2g_oft[PW_LMT_MAX_REGULATION_NUM];
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s8 ant_gain_5g_oft[PW_LMT_MAX_REGULATION_NUM];
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s8 ant_gain_6g_oft[PW_LMT_MAX_6G_REGULATION_NUM];
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u8 ant_type;
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};
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|
#define TX_NUM 2 /*1TX, 2TX*/
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#define BW20M_2G_5G_CH_NUM 42 /*2G CCK + 5G OFDM ch list*/
|
|
struct halrf_fw_scan_pwr_info {
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u8 fw_scan_pwr_enable;
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u32 cck_11m_1m;
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u32 ofdm_2g_18m_6m;
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u32 ofdm_5g_18m_6m;
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s8 pwr_lmt[TX_NUM][BW20M_2G_5G_CH_NUM];
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};
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extern const char * const _pw_lmt_regu_type_str[PW_LMT_MAX_REGULATION_NUM];
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#define pw_lmt_regu_type_str(lmt) ((lmt) < PW_LMT_MAX_REGULATION_NUM ? _pw_lmt_regu_type_str[(lmt)] : NULL)
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|
extern const char * const _pw_lmt_regu_type_str_6g[PW_LMT_MAX_6G_REGULATION_NUM];
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#define pw_lmt_regu_type_str_6g(lmt) ((lmt) < PW_LMT_MAX_6G_REGULATION_NUM ? _pw_lmt_regu_type_str_6g[(lmt)] : NULL)
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|
const char *pw_lmt_regu_type_of_band_str(u8 band, u8 lmt);
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|
void halrf_power_by_rate_store_to_array(struct rf_info *rf,
|
u32 band, u32 tx_num, u32 rate_id, u32 data);
|
void halrf_power_limit_store_to_array(struct rf_info *rf,
|
u8 regulation, u8 band, u8 bandwidth, u8 rate,
|
u8 tx_num, u8 beamforming, u8 chnl, s8 val);
|
void halrf_power_limit_set_worldwide(struct rf_info *rf);
|
void halrf_power_limit_ru_store_to_array(struct rf_info *rf,
|
u8 band, u8 bandwidth, u8 tx_num, u8 rate,
|
u8 regulation, u8 chnl, s8 val);
|
void halrf_power_limit_ru_set_worldwide(struct rf_info *rf);
|
|
#ifndef RF_8730A_SUPPORT
|
const char *halrf_get_pw_lmt_regu_type_str_extra(struct rf_info *rf, u8 band);
|
void halrf_get_power_limit_extra(struct rf_info *rf);
|
#endif
|
|
void halrf_modify_pwr_table_bitmask(struct rf_info *rf,
|
enum phl_phy_idx phy, enum phl_pwr_table pwr_table);
|
|
s8 halrf_get_pwr_control(struct rf_info *rf, enum phl_phy_idx phy);
|
|
s8 halrf_get_tx_rate_pwr_control(struct rf_info *rf, enum phl_phy_idx phy);
|
|
bool halrf_pwr_is_minus(struct rf_info *rf, u32 reg_tmp);
|
|
s32 halrf_show_pwr_table(struct rf_info *rf, u32 reg_tmp);
|
|
void halrf_set_scan_power_table_to_fw_no_6g(struct rf_info *rf);
|
|
#endif
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