/******************************************************************************
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*
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* Copyright(c) 2007 - 2020 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#include "halrf_precomp.h"
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u32 halrf_get_sys_time(struct rf_info *rf)
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{
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return 0;
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}
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u32 halrf_cal_bit_shift(u32 bit_mask)
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{
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u32 i;
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for (i = 0; i <= 31; i++) {
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if ((bit_mask >> i) & BIT0)
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break;
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}
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return i;
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}
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void halrf_wmac(struct rf_info *rf, u32 addr, u32 mask, u32 val)
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{
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u32 ori_val, bit_shift;
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#if defined(HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT) || defined(HALRF_CONFIG_FW_IO_OFLD_SUPPORT)
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struct rtw_mac_cmd cmd = {0};
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//u32 fw_ofld = rf->phl_com->dev_cap.fw_cap.offload_cap & BIT(0);
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bool fw_ofld = rf->phl_com->dev_cap.io_ofld;
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u32 rtn;
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#ifdef HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT
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fw_ofld = 1;
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#endif
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if (fw_ofld == true && rf->fw_ofld_enable == true) {
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rf->fw_ofld_start = true;
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RF_DBG(rf, DBG_RF_FW,
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"[FW_Ofld] MAC addr=0x%08x val=0x%08x\n",
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addr, val);
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cmd.src = RTW_MAC_MAC_CMD_OFLD;
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cmd.type = RTW_MAC_WRITE_OFLD;
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cmd.lc = 0;
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cmd.offset = (u16)addr;
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cmd.value = val;
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cmd.mask = mask;
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rtn = halrf_mac_add_cmd_ofld(rf, &cmd);
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if (rtn) {
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RF_WARNING("======>%s return fail error code = %d !!!\n",
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__func__, rtn);
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}
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rf->fw_w_count++;
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}
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else
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#endif
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{
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if (mask != MASKDWORD) {
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ori_val = halrf_rmac32(rf, addr);
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bit_shift = halrf_cal_bit_shift(mask);
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val = ((ori_val) & (~mask)) |( ((val << bit_shift)) & mask);
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}
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halrf_wmac32(rf, addr, val);
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}
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rf->w_count++;
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}
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u32 halrf_rmac32(struct rf_info *rf, u32 addr)
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{
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u32 reg_val = 0;
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#if defined(HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT) || defined(HALRF_CONFIG_FW_IO_OFLD_SUPPORT)
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if (rf->fw_ofld_start == true)
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halrf_write_fwofld_end(rf);
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#endif
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rf->r_count++;
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reg_val = hal_read32((rf)->hal_com, addr);
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return reg_val;
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}
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void halrf_wreg(struct rf_info *rf, u32 addr, u32 mask, u32 val)
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{
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u32 ori_val, bit_shift;
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#if defined(HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT) || defined(HALRF_CONFIG_FW_IO_OFLD_SUPPORT)
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struct rtw_mac_cmd cmd = {0};
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// u32 fw_ofld = rf->phl_com->dev_cap.io_ofld; //rf->phl_com->dev_cap.fw_cap.offload_cap & BIT(0);
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bool fw_ofld = rf->phl_com->dev_cap.io_ofld;
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u32 rtn;
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#endif
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#ifdef HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT
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fw_ofld = 1;
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#endif
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// u32 page_temp;
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// u32 offset_temp;
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// u32 temp = 0;
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// page_temp = addr & 0xff00;
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// offset_temp = addr & 0xff;
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// if ((page_temp != 0x4c00) && (page_temp != 0x4d00)) {
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// if (offset_temp <= 0x9c)
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// temp = halrf_r32(rf, offset_temp | 0x4c00);
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// }
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#if defined(HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT) || defined(HALRF_CONFIG_FW_IO_OFLD_SUPPORT)
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if (fw_ofld == true && rf->fw_ofld_enable == true) {
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rf->fw_ofld_start = true;
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RF_DBG(rf, DBG_RF_FW,
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"[FW_Ofld] BB addr=0x%08x mask=0x%08x val=0x%08x\n",
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addr, mask, val);
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cmd.src = RTW_MAC_BB_CMD_OFLD;
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cmd.type = RTW_MAC_WRITE_OFLD;
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cmd.lc = 0;
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cmd.offset = (u16)addr;
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cmd.value = val;
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cmd.mask = mask;
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rtn = halrf_mac_add_cmd_ofld(rf, &cmd);
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if (rtn) {
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RF_WARNING("======>%s return fail error code = %d !!!\n",
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__func__, rtn);
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}
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rf->fw_w_count++;
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}
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else
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#endif
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{
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if (mask != MASKDWORD) {
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ori_val = halrf_r32(rf, addr);
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bit_shift = halrf_cal_bit_shift(mask);
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val = ((ori_val) & (~mask)) |( ((val << bit_shift)) & mask);
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}
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halrf_w32(rf, addr, val);
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}
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rf->w_count++;
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// if ((page_temp != 0x4c00) && (page_temp != 0x4d00)) {
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// if (offset_temp <= 0x9c)
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// halrf_w32(rf, offset_temp | 0x4c00, temp);
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// }
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}
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u32 halrf_rreg(struct rf_info *rf, u32 addr, u32 mask)
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{
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u32 reg_val = 0, ori_val, bit_shift;
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#if defined(HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT) || defined(HALRF_CONFIG_FW_IO_OFLD_SUPPORT)
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if (rf->fw_ofld_start == true)
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halrf_write_fwofld_trigger(rf);
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#endif
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ori_val = halrf_r32(rf, addr);
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bit_shift = halrf_cal_bit_shift(mask);
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reg_val = (ori_val & mask) >> bit_shift;
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rf->r_count++;
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return reg_val;
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}
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u32 halrf_rrf(struct rf_info *rf, enum rf_path path, u32 addr, u32 mask)
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{
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static u32 operate2 = 0;
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u32 val = 0;
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if (_os_atomic_inc_return(rf->hal_com->drv_priv, (void*)&operate2) > 1) {
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RF_WARNING("RF read race %x %x %x!!!!!!!!!!!!!!", path, addr, mask);
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}
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#if defined(HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT) || defined(HALRF_CONFIG_FW_IO_OFLD_SUPPORT)
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if (rf->fw_ofld_start == true)
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halrf_write_fwofld_trigger(rf);
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#endif
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val = rtw_hal_read_rf_reg((rf)->hal_com, path, addr, mask);
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_os_atomic_dec(rf->hal_com->drv_priv, (void*)&operate2);
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rf->r_count++;
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return val;
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}
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void halrf_wrf(struct rf_info *rf, enum rf_path path, u32 addr, u32 mask, u32 val)
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{
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static u32 operate2 = 0;
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#if defined(HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT) || defined(HALRF_CONFIG_FW_IO_OFLD_SUPPORT)
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struct rtw_mac_cmd cmd = {0};
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// u32 fw_ofld = rf->phl_com->dev_cap.fw_cap.offload_cap & BIT(0);
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bool fw_ofld = rf->phl_com->dev_cap.io_ofld;
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u32 rtn;
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u32 direct_addr, offset_write_rf[2] = {0xe000, 0xf000};
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#ifdef HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT
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fw_ofld = 1;
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#endif
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if (_os_atomic_inc_return(rf->hal_com->drv_priv, (void*)&operate2) > 1) {
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RF_WARNING("RF write race %x %x %x %x!!!!!!!!!!!!!!", path, addr, mask, val);
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}
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if (fw_ofld == true && rf->fw_ofld_enable == true) {
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rf->fw_ofld_start = true;
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RF_DBG(rf, DBG_RF_FW,
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"[FW_Ofld] RF addr=0x%08x mask=0x%08x val=0x%08x path=%d\n",
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addr, mask, val, path);
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if (addr & BIT(16)) { /*RF D-die*/
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/*==== Calculate offset ====*/
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addr &= 0xff;
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direct_addr = offset_write_rf[path] + (addr << 2);
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cmd.src = RTW_MAC_BB_CMD_OFLD;
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cmd.type = RTW_MAC_WRITE_OFLD;
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cmd.lc = 0;
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cmd.offset = (u16)direct_addr;
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cmd.value = val;
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cmd.mask = mask;
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} else {
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cmd.src = RTW_MAC_RF_CMD_OFLD;
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cmd.type = RTW_MAC_WRITE_OFLD;
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cmd.lc = 0;
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cmd.rf_path = path;
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cmd.offset = (u16)addr;
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cmd.value = val;
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cmd.mask = mask;
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}
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RF_DBG(rf, DBG_RF_FW,
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"[FW_Ofld] cmd.src=0x%x addr=0x%x\n", cmd.src, addr);
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rtn = halrf_mac_add_cmd_ofld(rf, &cmd);
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if (rtn) {
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RF_WARNING("======>%s return fail error code = %d !!!\n",
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__func__, rtn);
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}
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rf->fw_w_count++;
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} else
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#endif
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rtw_hal_write_rf_reg((rf)->hal_com, path, addr, mask, val);
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_os_atomic_dec(rf->hal_com->drv_priv, (void*)&operate2);
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rf->w_count++;
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}
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bool halrf_polling_bb(struct rf_info *rf, u32 addr, u32 mask, u32 val, u32 count)
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{
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bool result = true;
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#if defined(HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT) || defined(HALRF_CONFIG_FW_IO_OFLD_SUPPORT)
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struct rtw_mac_cmd cmd = {0};
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// u32 fw_ofld = rf->phl_com->dev_cap.fw_cap.offload_cap & BIT(0);
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bool fw_ofld = rf->phl_com->dev_cap.io_ofld;
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u32 rtn;
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#ifdef HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT
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fw_ofld = 1;
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#endif
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if (fw_ofld == true && rf->fw_ofld_enable == true) {
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rf->fw_ofld_start = true;
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RF_DBG(rf, DBG_RF_FW,
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"[FW_Ofld] Polling BB addr=0x%08x mask=0x%08x val=0x%08x\n",
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addr, mask, val);
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cmd.src = RTW_MAC_BB_CMD_OFLD;
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cmd.type = RTW_MAC_COMPARE_OFLD;
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cmd.lc = 0;
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cmd.offset = (u16)addr;
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cmd.value = val;
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cmd.mask = mask;
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rtn = halrf_mac_add_cmd_ofld(rf, &cmd);
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if (rtn) {
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RF_WARNING("======>%s return fail error code = %d !!!\n",
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__func__, rtn);
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}
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if (rtn == 0)
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result = true;
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else
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result = false;
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}
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else
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#endif
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{
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u32 c = 0;
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while (halrf_rreg(rf, addr, mask) != val) {
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c++;
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halrf_delay_us(rf, 1);
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if (c > count) {
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result = false;
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break;
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}
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}
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}
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return result;
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}
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bool halrf_polling_rf(struct rf_info *rf, u32 path, u32 addr, u32 mask, u32 val, u32 count)
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{
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bool result = true;
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#if defined(HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT) || defined(HALRF_CONFIG_FW_IO_OFLD_SUPPORT)
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struct rtw_mac_cmd cmd = {0};
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// u32 fw_ofld = rf->phl_com->dev_cap.fw_cap.offload_cap & BIT(0);
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bool fw_ofld = rf->phl_com->dev_cap.io_ofld;
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u32 rtn;
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#ifdef HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT
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fw_ofld = 1;
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#endif
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if (fw_ofld == true && rf->fw_ofld_enable == true) {
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rf->fw_ofld_start = true;
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RF_DBG(rf, DBG_RF_FW,
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"[FW_Ofld] Polling RF path=%d addr=0x%08x mask=0x%08x val=0x%08x\n",
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path, addr, mask, val);
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if (addr & BIT(16))
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cmd.src = RTW_MAC_RF_DDIE_CMD_OFLD;
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else
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cmd.src = RTW_MAC_RF_CMD_OFLD;
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cmd.type = RTW_MAC_COMPARE_OFLD;
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cmd.lc = 0;
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cmd.rf_path = path;
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cmd.offset = (u16)addr;
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cmd.value = val;
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cmd.mask = mask;
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rtn = halrf_mac_add_cmd_ofld(rf, &cmd);
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if (rtn) {
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RF_WARNING("======>%s return fail error code = %d !!!\n",
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__func__, rtn);
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}
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if (rtn == 0)
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result = true;
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else
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result = false;
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}
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else
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#endif
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{
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u32 c = 0;
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while (halrf_rrf(rf, path, addr, mask) != val) {
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c++;
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halrf_delay_us(rf, 1);
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if (c > count) {
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result = false;
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break;
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}
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}
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}
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return result;
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}
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void halrf_delay_us(struct rf_info *rf, u32 count)
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{
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#if defined(HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT) || defined(HALRF_CONFIG_FW_IO_OFLD_SUPPORT)
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struct rtw_mac_cmd cmd = {0};
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// u32 fw_ofld = rf->phl_com->dev_cap.fw_cap.offload_cap & BIT(0);
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bool fw_ofld = rf->phl_com->dev_cap.io_ofld;
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u32 rtn;
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#ifdef HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT
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fw_ofld = 1;
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#endif
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if (fw_ofld == true && rf->fw_ofld_enable == true) {
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rf->fw_ofld_start= true;
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RF_DBG(rf, DBG_RF_FW,
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"[FW_Ofld] ======>%s count=%d\n",
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__func__, count);
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cmd.type = RTW_MAC_DELAY_OFLD;
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cmd.lc = 0;
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cmd.value = count;
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rtn = halrf_mac_add_cmd_ofld(rf, &cmd);
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if (rtn) {
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RF_WARNING("======>%s return fail error code = %d !!!\n",
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__func__, rtn);
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}
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rf->fw_delay_us_count = rf->fw_delay_us_count + count;
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}
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else
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#endif
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{
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u32 i;
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for (i = 0; i < count; i++)
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halrf_os_delay_us(rf, 1);
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}
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}
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void halrf_fill_h2c_cmd(struct rf_info *rf, u16 cmdlen, u8 cmdid,
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u8 classid, u32 cmdtype, u32 *pval)
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{
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u32 rt_val = 0;
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struct rtw_g6_h2c_hdr hdr = {0};
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struct rtw_hal_com_t *hal_com = NULL;
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hdr.h2c_class = classid;
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hdr.h2c_func = cmdid;
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hdr.type = cmdtype;
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hdr.content_len = cmdlen;
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hal_com = rf->hal_com;
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RF_DBG(rf, DBG_RF_IQK, "[IQK]======>%s H2C: %x %x %x\n",
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__func__, classid, cmdid, cmdlen);
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rt_val = rtw_hal_mac_send_h2c(hal_com, &hdr, pval);
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if (rt_val != 0) {
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RF_WARNING("Error H2C CLASS=%d, ID=%d\n", classid, cmdid);
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RF_DBG(rf, DBG_RF_IQK, "Error H2C CLASS=%d, ID=%d\n", classid, cmdid);
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}
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}
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