/******************************************************************************
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*
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* Copyright(c) 2007 - 2020 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __HALBB_STATISTICS_H__
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#define __HALBB_STATISTICS_H__
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#include "halbb_statistics_ex.h"
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/*@--------------------------[Define] ---------------------------------------*/
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#define CHK_HANG_L_SIG_TH 3
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#define HANG_RECOVERY true // Disable auto-recovery mechanism for 52A CBV
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#define HANG_LIMIT 1
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/*@--------------------------[Enum]------------------------------------------*/
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#if 0
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enum stat_type_sel {
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STATE_PROBE_RESP = 1,
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STATE_BEACON = 2,
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STATE_ACTION = 3,
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STATE_BFRP = 4,
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STATE_NDPA = 5,
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STATE_BA = 6,
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STATE_RTS = 7,
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STATE_CTS = 8,
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STATE_ACK = 9,
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STATE_DATA = 10,
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STATE_NULL = 11,
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STATE_QOS = 12,
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};
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enum stat_mac_type {
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TYPE_PROBE_RESP = 0x05,
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TYPE_BEACON = 0x08,
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TYPE_ACTION = 0x0d,
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TYPE_BFRP = 0x14,
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TYPE_NDPA = 0x15,
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TYPE_BA = 0x19,
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TYPE_RTS = 0x1b,
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TYPE_CTS = 0x1c,
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TYPE_ACK = 0x1d,
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TYPE_DATA = 0x20,
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TYPE_NULL = 0x24,
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TYPE_QOS = 0x28,
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};
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/*@--------------------------[Structure]-------------------------------------*/
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struct bb_usr_set_info {
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u16 ofdm2_rate_idx;
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u16 ht2_rate_idx;
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u16 vht2_rate_idx;
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u16 he2_rate_idx;
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u16 eht2_rate_idx;
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enum stat_mac_type stat_mac_type_i;
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enum stat_type_sel stat_type_sel_i;
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};
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struct bb_cca_info {
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u32 cnt_ofdm_cca;
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u32 cnt_cck_cca;
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u32 cnt_cca_all;
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u32 cnt_cck_spoofing;
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u32 cnt_ofdm_spoofing;
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u32 cnt_cca_spoofing_all;
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u32 pop_cnt;
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};
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struct bb_crc_info {
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u32 cnt_ampdu_miss;
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u32 cnt_ampdu_crc_error;
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u32 cnt_ampdu_crc_ok;
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u32 cnt_cck_crc32_error;
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u32 cnt_cck_crc32_ok;
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u32 cnt_ofdm_crc32_error;
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u32 cnt_ofdm_crc32_ok;
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u32 cnt_ht_crc32_error;
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u32 cnt_ht_crc32_ok;
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u32 cnt_vht_crc32_error;
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u32 cnt_vht_crc32_ok;
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u32 cnt_he_crc32_ok;
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u32 cnt_he_crc32_error;
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u32 cnt_eht_crc32_ok;
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u32 cnt_eht_crc32_error;
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u32 cnt_crc32_error_all;
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u32 cnt_crc32_ok_all;
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};
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struct bb_crc2_info {
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u32 cnt_ofdm2_crc32_error;
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u32 cnt_ofdm2_crc32_ok;
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u8 ofdm2_pcr;
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u32 cnt_ht2_crc32_error;
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u32 cnt_ht2_crc32_ok;
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u8 ht2_pcr;
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u32 cnt_vht2_crc32_error;
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u32 cnt_vht2_crc32_ok;
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u8 vht2_pcr;
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u32 cnt_he2_crc32_error;
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u32 cnt_he2_crc32_ok;
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u8 he2_pcr;
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u32 cnt_eht2_crc32_ok;
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u32 cnt_eht2_crc32_error;
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u8 eht2_pcr;
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u32 cnt_ofdm3_crc32_error;
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u32 cnt_ofdm3_crc32_ok;
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};
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struct bb_cck_fa_info {
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u32 sfd_gg_cnt;
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u32 sig_gg_cnt;
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u32 cnt_cck_crc_16;
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};
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struct bb_legacy_fa_info {
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u32 cnt_lsig_brk_s_th;
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u32 cnt_lsig_brk_l_th;
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u32 cnt_parity_fail;
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u32 cnt_rate_illegal;
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u32 cnt_sb_search_fail;
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};
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struct bb_ht_fa_info {
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u32 cnt_crc8_fail;
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u32 cnt_crc8_fail_s_th;
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u32 cnt_crc8_fail_l_th;
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u32 cnt_mcs_fail;
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};
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struct bb_vht_fa_info {
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u32 cnt_crc8_fail_vhta;
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/*u32 cnt_crc8_fail_vhtb; removed at RXD*/
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u32 cnt_mcs_fail_vht;
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};
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struct bb_he_fa_info {
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u32 cnt_crc4_fail_hea_su;
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u32 cnt_crc4_fail_hea_ersu;
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u32 cnt_crc4_fail_hea_mu;
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u32 cnt_crc4_fail_heb_ch1_mu;
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u32 cnt_crc4_fail_heb_ch2_mu;
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u32 cnt_mcs_fail_he_bcc;
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u32 cnt_mcs_fail_he;
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u32 cnt_mcs_fail_he_dcm;
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};
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struct bb_fa_info {
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u32 cnt_total_brk;
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u32 cnt_cck_fail;
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u32 cnt_ofdm_fail;
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u32 cnt_fail_all;
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struct bb_cck_fa_info bb_cck_fa_i;
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struct bb_legacy_fa_info bb_legacy_fa_i;
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struct bb_ht_fa_info bb_ht_fa_i;
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struct bb_vht_fa_info bb_vht_fa_i;
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struct bb_he_fa_info bb_he_fa_i;
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};
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struct bb_tx_cnt_info {
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u32 cck_mac_txen;
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u32 cck_phy_txon;
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u32 ofdm_mac_txen;
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u32 ofdm_phy_txon;
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};
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#endif
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struct bb_stat_cr_info {
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u32 cck_cca;
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u32 cck_cca_m;
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u32 cck_crc16fail;
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u32 cck_crc16fail_m;
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u32 cck_crc32ok;
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u32 cck_crc32ok_m;
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u32 cck_crc32fail;
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u32 cck_crc32fail_m;
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u32 cca_spoofing;
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u32 cca_spoofing_m;
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u32 lsig_brk_s_th;
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u32 lsig_brk_s_th_m;
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u32 lsig_brk_l_th;
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u32 lsig_brk_l_th_m;
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u32 htsig_crc8_err_s_th;
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u32 htsig_crc8_err_s_th_m;
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u32 htsig_crc8_err_l_th;
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u32 htsig_crc8_err_l_th_m;
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u32 brk;
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u32 brk_m;
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u32 brk_sel;
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u32 brk_sel_m;
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u32 rxl_err_parity;
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u32 rxl_err_parity_m;
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u32 rxl_err_rate;
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u32 rxl_err_rate_m;
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u32 ht_err_crc8;
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u32 ht_err_crc8_m;
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u32 vht_err_siga_crc8;
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u32 vht_err_siga_crc8_m;
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u32 ht_not_support_mcs;
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u32 ht_not_support_mcs_m;
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u32 vht_not_support_mcs;
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u32 vht_not_support_mcs_m;
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u32 err_during_bt_tx;
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u32 err_during_bt_tx_m;
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u32 err_during_bt_rx;
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u32 err_during_bt_rx_m;
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u32 edge_murx_nsts0;
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u32 edge_murx_nsts0_m;
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u32 search_fail;
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u32 search_fail_m;
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u32 ofdm_cca;
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u32 ofdm_cca_m;
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u32 ofdm_cca_s20;
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u32 ofdm_cca_s20_m;
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u32 ofdm_cca_s40;
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u32 ofdm_cca_s40_m;
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u32 ofdm_cca_s80;
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u32 ofdm_cca_s80_m;
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u32 ccktxen;
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u32 ccktxen_m;
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u32 ccktxon;
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u32 ccktxon_m;
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u32 ofdmtxon;
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u32 ofdmtxon_m;
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u32 ofdmtxen;
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u32 ofdmtxen_m;
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u32 drop_trig;
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u32 drop_trig_m;
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u32 pop_trig;
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u32 pop_trig_m;
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u32 tx_conflict;
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u32 tx_conflict_m;
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u32 wmac_rstb;
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u32 wmac_rstb_m;
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u32 en_tb_ppdu_fix_gain;
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u32 en_tb_ppdu_fix_gain_m;
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u32 en_tb_cca_pw_th;
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u32 en_tb_cca_pw_th_m;
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u32 eht_crc_ok;
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u32 eht_crc_ok_m;
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u32 eht_crc_err;
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u32 eht_crc_err_m;
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u32 he_crc_ok;
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u32 he_crc_ok_m;
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u32 he_crc_err;
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u32 he_crc_err_m;
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u32 vht_crc_ok;
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u32 vht_crc_ok_m;
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u32 vht_crc_err;
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u32 vht_crc_err_m;
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u32 ht_crc_ok;
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u32 ht_crc_ok_m;
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u32 ht_crc_err;
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u32 ht_crc_err_m;
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u32 l_crc_ok;
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u32 l_crc_ok_m;
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u32 l_crc_err;
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u32 l_crc_err_m;
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u32 eht_crc_ok2;
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u32 eht_crc_ok2_m;
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u32 eht_crc_err2;
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u32 eht_crc_err2_m;
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u32 he_crc_ok2;
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u32 he_crc_ok2_m;
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u32 he_crc_err2;
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u32 he_crc_err2_m;
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u32 vht_crc_ok2;
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u32 vht_crc_ok2_m;
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u32 vht_crc_err2;
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u32 vht_crc_err2_m;
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u32 ht_crc_ok2;
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u32 ht_crc_ok2_m;
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u32 ht_crc_err2;
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u32 ht_crc_err2_m;
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u32 l_crc_ok2;
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u32 l_crc_ok2_m;
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u32 l_crc_err2;
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u32 l_crc_err2_m;
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u32 l_crc_ok3;
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u32 l_crc_ok3_m;
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u32 l_crc_err3;
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u32 l_crc_err3_m;
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u32 ampdu_rxon;
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u32 ampdu_rxon_m;
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u32 ampdu_miss;
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u32 ampdu_miss_m;
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u32 ampdu_crc_ok;
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u32 ampdu_crc_ok_m;
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u32 ampdu_crc_err;
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u32 ampdu_crc_err_m;
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u32 hesu_err_sig_a_crc4;
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u32 hesu_err_sig_a_crc4_m;
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u32 heersu_err_sig_a_crc4;
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u32 heersu_err_sig_a_crc4_m;
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u32 hemu_err_sig_a_crc4;
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u32 hemu_err_sig_a_crc4_m;
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u32 hemu_err_sigb_ch1_comm_crc4;
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u32 hemu_err_sigb_ch1_comm_crc4_m;
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u32 hemu_err_sigb_ch2_comm_crc4;
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u32 hemu_err_sigb_ch2_comm_crc4_m;
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u32 he_u0_err_bcc_mcs;
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u32 he_u0_err_bcc_mcs_m;
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u32 he_u0_err_mcs;
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u32 he_u0_err_mcs_m;
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u32 he_u0_err_dcm_mcs;
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u32 he_u0_err_dcm_mcs_m;
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u32 r1b_rx_rpt_rst;
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u32 r1b_rx_rpt_rst_m;
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u32 r1b_rr_sel;
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u32 r1b_rr_sel_m;
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u32 rst_all_cnt;
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u32 rst_all_cnt_m;
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u32 enable_all_cnt;
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u32 enable_all_cnt_m;
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u32 enable_ofdm;
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u32 enable_ofdm_m;
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u32 enable_cck;
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u32 enable_cck_m;
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u32 r1b_rx_dis_cca;
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u32 r1b_rx_dis_cca_m;
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u32 intf_r_rate;
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u32 intf_r_rate_m;
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u32 intf_r_mcs;
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u32 intf_r_mcs_m;
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u32 intf_r_vht_mcs;
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u32 intf_r_vht_mcs_m;
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u32 intf_r_he_mcs;
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u32 intf_r_he_mcs_m;
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u32 intf_r_eht_mcs;
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u32 intf_r_eht_mcs_m;
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u32 intf_r_vht_nss;
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u32 intf_r_vht_nss_m;
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u32 intf_r_he_nss;
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u32 intf_r_he_nss_m;
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u32 intf_r_eht_nss;
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u32 intf_r_eht_nss_m;
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u32 intf_r_mac_hdr_type;
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u32 intf_r_mac_hdr_type_m;
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u32 intf_r_pkt_type;
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u32 intf_r_pkt_type_m;
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u32 dbcc;
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u32 dbcc_m;
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u32 dbcc_2p4g_band_sel;
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u32 dbcc_2p4g_band_sel_m;
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u32 cnt_pop_trig;
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u32 cnt_pop_trig_m;
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u32 max_cnt_pop;
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u32 max_cnt_pop_m;
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u32 break_option;
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u32 break_option_m;
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};
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struct bb_stat_info {
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struct bb_stat_cr_info bb_stat_cr_i;
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u32 cnt_bw_usc;
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u32 cnt_bw_lsc;
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u32 time_fa_all;
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u32 dbg_port0;
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u32 chk_hang_cnt;
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u8 chk_hang_limit;
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bool hang_recovery_en;
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bool cnt_reset_en;
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bool cck_block_enable;
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bool ofdm_block_enable;
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struct bb_tx_cnt_info bb_tx_cnt_i;
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struct bb_cca_info bb_cca_i;
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struct bb_crc_info bb_crc_i;
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struct bb_crc2_info bb_crc2_i;
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struct bb_fa_info bb_fa_i;
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struct bb_usr_set_info bb_usr_set_i;
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struct bb_stat_hang_info bb_stat_hang_i;
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};
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struct bb_info;
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/*@--------------------------[Prptotype]-------------------------------------*/
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void halbb_chk_hang(struct bb_info *bb);
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void halbb_print_cnt3(struct bb_info *bb, enum phl_phy_idx phy_idx);
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void halbb_print_cnt2(struct bb_info *bb, enum phl_phy_idx phy_idx);
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void halbb_print_cnt(struct bb_info *bb, bool cck_enable, enum phl_phy_idx phy_idx, enum phl_phy_idx phy_idx_2);
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void halbb_cnt_reg_reset(struct bb_info *bb);
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void halbb_set_crc32_cnt2_rate(struct bb_info *bb, u16 rate_idx);
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void halbb_set_crc32_cnt3_format(struct bb_info *bb, u8 usr_type_sel);
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void halbb_crc32_cnt_dbg(struct bb_info *bb, char input[][16], u32 *_used,
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char *output, u32 *_out_len);
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void halbb_cck_cnt_statistics(struct bb_info *bb);
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void halbb_ofdm_cnt_statistics(struct bb_info *bb, enum phl_phy_idx phy_idx);
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void halbb_statistics_reset(struct bb_info *bb);
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void halbb_statistics(struct bb_info *bb);
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void halbb_statistics_init(struct bb_info *bb);
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void halbb_cr_cfg_stat_init(struct bb_info *bb);
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void halbb_pmac_statistics_io_en(struct bb_info *bb);
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void halbb_pmac_statistics(struct bb_info *bb);
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#endif
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