/******************************************************************************
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*
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* Copyright(c) 2007 - 2020 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __HALBB_RUA_TBL_EX_H__
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#define __HALBB_RUA_TBL_EX_H__
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#ifdef HALBB_RUA_SUPPORT
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/*@--------------------------[Define] ---------------------------------------*/
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#define HALBB_AX4RU_STA_NUM 4
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#define HALBB_AX8RU_STA_NUM 8
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#define HALBB_MAX_RU_STA_NUM 16
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/*@--------------------------[Enum]------------------------------------------*/
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enum rtw_rua_tbl_hdr_rw {
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RUA_TBL_RW_READ = 0,
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RUA_TBL_RW_WRITE = 1
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};
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enum rtw_rua_tbl_hdr_type {
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RUA_TBL_TYPE_SW = 0,
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RUA_TBL_TYPE_HW = 1
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};
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enum rtw_rua_tbl_hdr_class {
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RUA_TBL_CL_DLRU_SW = 0x0,
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RUA_TBL_CL_ULRU_SW = 0x1,
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RUA_TBL_CL_RU_STA = 0x2,
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RUA_TBL_CL_DLRU_SW_FIX = 0x3,
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RUA_TBL_CL_ULRU_SW_FIX = 0x4,
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RUA_TBL_CL_BA_INFO = 0x5
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};
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enum rtw_ra_maksing_cmd {
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OR_RA_MASKING = 0x0,
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AND_RA_MASKING = 0x1,
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RPLC_RA_MASKING = 0x2,
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RST_RA_MASKING = 0x3,
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MAX_RA_MASKING_CMD
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};
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enum rtw_ra_type {
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RA_DLRU = 0x0,
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RA_ULRU = 0x1,
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RA_ULSU = 0x2,
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MAX_RA_TYPE_NUM
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};
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/*@--------------------------[Structure]-------------------------------------*/
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struct rtw_rua_tbl_hdr {
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u8 rw:1;
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u8 idx:7;
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u16 offset:5;
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u16 len:10;
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u16 type:1;
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u8 tbl_class:6;
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u8 band:2;
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};
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struct rtw_ru_rate_ent {
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u8 dcm:1;
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u8 ss:3;
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u8 mcs:4;
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};
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struct rtw_tf_ba_tbl {
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u32 fix_ba:1;
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u32 ru_psd:9;
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u32 tf_rate:9;
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u32 rf_gain_fix:1;
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u32 rf_gain_idx:10;
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u32 tb_ppdu_bw:2;
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struct rtw_ru_rate_ent rate;
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u8 gi_ltf:3;
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u8 doppler:1;
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u8 stbc:1;
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u8 sta_coding:1;
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u8 tb_t_pe_nom:2;
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u8 pr20_bw_en:1;
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u8 ma_type:1;
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u8 rsvd1:6;
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u8 rsvd2;
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};
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struct rtw_dl_ru_gp_tbl {
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struct rtw_rua_tbl_hdr tbl_hdr;
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u8 tx_mode: 2;
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u8 ppdu_bw: 3;
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u8 rsvd0: 3;
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u8 fix_mode_flag: 1;
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u8 txpwr_ofld_en: 1;
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u8 pwrlim_dis: 1;
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u8 rsvd1:5;
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u16 tx_pwr: 9;
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u16 pwr_boost_fac: 5;
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u16 rsvd2: 2;
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u32 rsvd3;
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struct rtw_tf_ba_tbl tf;
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};
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struct rtw_ul_ru_gp_tbl {
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struct rtw_rua_tbl_hdr tbl_hdr;
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//DWORD 1
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u8 tx_mode: 2;
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u8 ppdu_bw: 3;
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u8 rsvd0: 3;
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u8 fix_mode_flag: 1;
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u8 fix_tf_rate: 1;
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u8 rf_gain_fix: 1;
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u8 rsvd1: 5;
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u16 rsvd2;
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//DWORD 2
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u32 grp_psd_max: 9;
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u32 grp_psd_min: 9;
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u32 tf_rate: 9;
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u32 rsvd3: 5;
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//DWORD 3
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u32 rf_gain_idx: 10;
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u32 rsvd4: 22;
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};
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struct rtw_ru_sta_info {
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struct rtw_rua_tbl_hdr tbl_hdr;
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/* sta capability */
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u8 gi_ltf_48spt:1;
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u8 gi_ltf_18spt:1;
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u8 rsvd0:6;
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/* dl su */
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u8 dlsu_info_en:1;
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u8 dlsu_bw:2;
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u8 dlsu_gi_ltf:3;
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u8 dlsu_doppler_ctrl:2;
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u8 dlsu_coding:1;
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u8 dlsu_txbf:1;
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u8 dlsu_stbc:1;
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u8 dl_fwcqi_flag:1;
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u8 dlru_ratetbl_ridx:4;
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u8 csi_info_bitmap;
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u32 dl_swgrp_bitmap;
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u16 dlsu_dcm:1;
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u16 rsvd1:6;
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u16 dlsu_rate:9;
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u8 dlsu_pwr:6;
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u8 rsvd2:2;
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u8 rsvd4;
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/* ul su */
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u8 ulsu_info_en:1;
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u8 ulsu_bw:2;
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u8 ulsu_gi_ltf:3;
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u8 ulsu_doppler_ctrl:2;
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u8 ulsu_dcm:1;
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u8 ulsu_ss:3;
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u8 ulsu_mcs:4;
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u16 ul_fwcqi_flag:1;
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u16 ulru_ratetbl_ridx:4;
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u16 ulsu_stbc:1;
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u16 ulsu_coding:1;
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u16 ulsu_rssi_m:9;
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u32 ul_swgrp_bitmap;
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/* tb info */
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};
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/*
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struct rtw_dl_fix_sta_ent {
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u8 mac_id;
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u8 ru_pos[3];
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u8 fix_rate:1;
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u8 fix_coding:1;
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u8 fix_txbf:1;
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u8 fix_pwr_fac:1;
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u8 rsvd0:4;
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struct rtw_ru_rate_ent rate;
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u8 txbf:1;
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u8 coding:1;
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u8 pwr_boost_fac:5;
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u8 rsvd1: 1;
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u8 rsvd2;
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};
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struct rtw_dl_ru_fix_tbl {
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struct rtw_rua_tbl_hdr tbl_hdr;
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u8 max_sta_num:3;
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u8 min_sta_num:3;
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u8 ru_swp_flg:1;
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u8 rsvd0:1;
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u8 doppler:1;
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u8 stbc:1;
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u8 gi_ltf:3;
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u8 ma_type:1;
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u8 fixru_flag:1;
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u8 rupos_csht_flag:1;
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u8 rsvd2;
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struct rtw_dl_fix_sta_ent sta[HALBB_AX4RU_STA_NUM];
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};
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*/
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struct rtw_dlfix_sta_i_ax4ru {
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u8 mac_id;
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u8 ru_pos[3];
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u8 fix_rate:1;
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u8 fix_coding:1;
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u8 fix_txbf:1;
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u8 fix_pwr_fac:1;
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u8 rsvd0:4;
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struct rtw_ru_rate_ent rate;
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u8 txbf:1;
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u8 coding:1;
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u8 pwr_boost_fac:5;
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u8 rsvd1: 1;
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u8 rsvd2;
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};
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struct rtw_dlfix_sta_i_ax8ru {
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u8 mac_id;
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u8 ru_pos[7];
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u8 fix_rate:1;
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u8 fix_coding:1;
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u8 fix_txbf:1;
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u8 fix_pwr_fac:1;
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u8 rsvd0:4;
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struct rtw_ru_rate_ent rate;
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u8 txbf:1;
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u8 coding:1;
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u8 pwr_boost_fac:5;
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u8 rsvd1: 1;
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u8 rsvd2;
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};
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struct rtw_dlru_fixtbl_ax4ru {
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struct rtw_rua_tbl_hdr tbl_hdr;
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u8 max_sta_num:3;
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u8 min_sta_num:3;
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u8 ru_swp_flg:1;
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u8 rsvd0:1;
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u8 doppler:1;
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u8 stbc:1;
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u8 gi_ltf:3;
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u8 ma_type:1;
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u8 fixru_flag:1;
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u8 rupos_csht_flag:1;
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u8 rsvd2;
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struct rtw_dlfix_sta_i_ax4ru sta[HALBB_AX4RU_STA_NUM];
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};
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struct rtw_dlru_fixtbl_ax8ru {
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struct rtw_rua_tbl_hdr tbl_hdr;
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u8 max_sta_num:4;
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u8 min_sta_num:4;
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u8 doppler:1;
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u8 stbc:1;
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u8 gi_ltf:3;
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u8 ma_type:1;
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u8 fixru_flag:1;
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u8 rupos_csht_flag:1;
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u8 ru_swp_flg:1;
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u8 rsvd1:7;
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u8 rsvd2;
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struct rtw_dlfix_sta_i_ax8ru sta[HALBB_AX8RU_STA_NUM];
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};
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struct rtw_rupos_i {
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u8 ru_pos:8;
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u8 ps160:1;
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u8 tgt_rssi:7;
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};
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struct rtw_rupos_fixtbl{
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struct rtw_rupos_i aloc2ru[2];
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struct rtw_rupos_i aloc3ru[3];
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u16 rsvd0;
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struct rtw_rupos_i aloc4ru[4];
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struct rtw_rupos_i aloc5ru[5];
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u16 rsvd1;
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struct rtw_rupos_i aloc6ru[6];
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struct rtw_rupos_i aloc7ru[7];
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u16 rsvd2;
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struct rtw_rupos_i aloc8ru[8];
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struct rtw_rupos_i aloc9ru[9];
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u16 rsvd3;
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struct rtw_rupos_i aloc10ru[10];
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struct rtw_rupos_i aloc11ru[11];
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u16 rsvd4;
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struct rtw_rupos_i aloc12ru[12];
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struct rtw_rupos_i aloc13ru[13];
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u16 rsvd5;
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struct rtw_rupos_i aloc14ru[14];
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struct rtw_rupos_i aloc15ru[15];
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u16 rsvd6;
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struct rtw_rupos_i aloc16ru[16];
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};
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struct rtw_dlfix_sta_i_ext {
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u16 mac_id;
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u8 fix_rate: 1;
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u8 fix_coding: 1;
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u8 fix_txbf: 1;
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u8 fix_pwr_fac: 1;
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u8 macid_unspecified:1;
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u8 rsvd0: 3;
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u8 txbf: 1;
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u8 coding: 1;
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u8 pwr_boost_fac: 5;
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u8 rsvd1: 1;
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struct rtw_ru_rate_ent rate;
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u8 rsvd2[3];
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};
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struct rtw_dlru_fixtbl_univrsl {
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struct rtw_rua_tbl_hdr tbl_hdr;
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u8 max_sta_num;
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u8 min_sta_num;
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u8 doppler: 1;
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u8 stbc: 1;
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u8 gi_ltf: 3;
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u8 ma_type: 1;
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u8 fixru_flag: 1;
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u8 rupos_csht_flag: 1;
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u8 ru_swp_flg: 1;
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u8 rsvd0: 7;
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u16 ch20_with_data;
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u16 rsvd2;
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struct rtw_dlfix_sta_i_ext sta[HALBB_MAX_RU_STA_NUM];
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struct rtw_rupos_fixtbl rupos_tbl;
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};
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union rtw_dlru_fixtbl{
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struct rtw_dlru_fixtbl_ax4ru ax4ru;
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struct rtw_dlru_fixtbl_ax8ru ax8ru;
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struct rtw_dlru_fixtbl_univrsl univrsl;
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};
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/*
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struct rtw_ul_fix_sta_ent {
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u8 mac_id;
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u8 ru_pos[3];
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u8 tgt_rssi[3];
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u8 fix_tgt_rssi:1;
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u8 fix_rate:1;
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u8 fix_coding:1;
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u8 coding:1;
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u8 rsvd1:4;
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struct rtw_ru_rate_ent rate;
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};
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struct rtw_ul_ru_fix_tbl {
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struct rtw_rua_tbl_hdr tbl_hdr;
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u8 max_sta_num:3;
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u8 min_sta_num:3;
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u8 doppler:1;
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u8 ma_type:1;
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u8 gi_ltf:3;
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u8 stbc:1;
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u8 fix_tb_t_pe_nom: 1;
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u8 tb_t_pe_nom: 2;
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u8 fixru_flag: 1;
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struct rtw_ul_fix_sta_ent sta[HALBB_AX4RU_STA_NUM];
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};
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*/
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struct rtw_ulfix_sta_i_ax4ru {
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u8 mac_id;
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u8 ru_pos[3];
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u8 tgt_rssi[3];
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u8 fix_tgt_rssi:1;
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u8 fix_rate:1;
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u8 fix_coding:1;
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u8 coding:1;
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u8 rsvd1:4;
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struct rtw_ru_rate_ent rate;
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};
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struct rtw_ulfix_sta_i_ax8ru {
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u8 mac_id;
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u8 ru_pos[7];
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u8 rsvd1;
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u8 tgt_rssi[7];
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u8 fix_tgt_rssi:1;
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u8 fix_rate:1;
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u8 fix_coding:1;
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u8 coding:1;
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u8 rsvd2:4;
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struct rtw_ru_rate_ent rate;
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u8 rsvd3;
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u8 rsvd4;
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};
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struct rtw_ulru_fixtbl_ax4ru {
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struct rtw_rua_tbl_hdr tbl_hdr;
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u8 max_sta_num:3;
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u8 min_sta_num:3;
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u8 doppler:1;
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u8 ma_type:1;
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u8 gi_ltf:3;
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u8 stbc:1;
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u8 fix_tb_t_pe_nom: 1;
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u8 tb_t_pe_nom: 2;
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u8 fixru_flag: 1;
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struct rtw_ulfix_sta_i_ax4ru sta[HALBB_AX4RU_STA_NUM];
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};
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struct rtw_ulru_fixtbl_ax8ru {
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struct rtw_rua_tbl_hdr tbl_hdr;
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u8 max_sta_num:4;
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u8 min_sta_num:4;
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u8 gi_ltf:3;
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u8 stbc:1;
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u8 fix_tb_t_pe_nom: 1;
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u8 tb_t_pe_nom: 2;
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u8 fixru_flag: 1;
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u8 doppler:1;
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u8 ma_type:1;
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u8 rsvd1:6;
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u8 rsvd2;
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struct rtw_ulfix_sta_i_ax8ru sta[HALBB_AX8RU_STA_NUM];
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};
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struct rtw_ulfix_sta_i_ext {
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u16 mac_id;
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u8 fix_tgt_rssi: 1;
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u8 fix_rate: 1;
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u8 fix_coding: 1;
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u8 coding: 1;
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u8 macid_unspecified: 1;
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u8 rsvd0: 3;
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u8 rsvd1;
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struct rtw_ru_rate_ent rate;
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u8 rsvd2[3];
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};
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struct rtw_ulru_fixtbl_univrsl {
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struct rtw_rua_tbl_hdr tbl_hdr;
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u8 max_sta_num;
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u8 min_sta_num;
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u8 gi_ltf: 3;
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u8 stbc: 1;
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u8 fix_tb_t_pe_nom: 1;
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u8 tb_t_pe_nom: 2;
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u8 fixru_flag: 1;
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u8 doppler: 1;
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u8 ma_type: 1;
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u8 rsvd1: 6;
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u32 rsvd2;
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struct rtw_ulfix_sta_i_ext sta[HALBB_MAX_RU_STA_NUM];
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struct rtw_rupos_fixtbl rupos_tbl;
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};
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union rtw_ulru_fixtbl{
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struct rtw_ulru_fixtbl_ax4ru ax4ru;
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struct rtw_ulru_fixtbl_ax8ru ax8ru;
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struct rtw_ulru_fixtbl_univrsl univrsl;
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};
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struct rtw_ba_tbl_info {
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struct rtw_rua_tbl_hdr tbl_hdr;
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struct rtw_tf_ba_tbl tf_ba_t;
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};
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struct rtw_sw_grp_bitmap {
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u16 macid;
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u8 en_upd_dl_swgrp:1;
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u8 en_upd_ul_swgrp:1;
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u8 cmdend:1; // add for determine whether last user or not
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u8 rsvd1:5;
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u8 rsvd2;
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u32 dl_sw_grp_bitmap;
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u32 ul_sw_grp_bitmap;
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};
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struct rtw_sw_grp_set {
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struct rtw_sw_grp_bitmap swgrp_bitmap[8];
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};
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struct rtw_dl_macid_cfg {
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u32 macid: 16;
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u32 dl_su_rate_cfg: 1;
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u32 dl_su_rate: 9;
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u32 dl_su_bw: 2;
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u32 dl_su_pwr_cfg: 1;
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u32 rsvd0: 3;
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u32 gi_ltf_4x8_support: 1;
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u32 gi_ltf_1x8_support: 1;
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u32 dl_su_pwr: 6;
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u32 dl_su_info_en: 1;
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u32 rsvd2: 2;
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u32 dl_su_gi_ltf: 3;
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u32 dl_su_doppler_ctrl: 2;
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u32 dl_su_coding: 1;
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u32 dl_su_txbf: 1;
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u32 dl_su_stbc: 1;
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u32 dl_su_dcm: 1;
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u32 rsvd3: 12;
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//HE cap
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u32 he_cap_update_en: 1;
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u32 gi_ltf_1x0p8_cap: 1;
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u32 gi_ltf_4x0p8_cap: 1;
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u32 tx_1024_le_242ru_cap: 1;
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u32 rx_1024_le_242ru_cap: 1;
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u32 ldpc_cap: 1;
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u32 stbc_tx_leq_80_cap: 1;
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u32 stbc_rx_leq_80_cap: 1;
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u32 stbc_tx_ge_80_cap: 1;
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u32 stbc_rx_ge_80_cap: 1;
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u32 dcm_max_cst_tx_cap: 2;
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u32 dcm_max_ru_cap: 2;
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u32 nominal_pakt_padding_cap: 2;
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u32 he_20m_in_40m_2p4g_band_cap: 1;
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u32 he_20m_in_160m_cap: 1;
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u32 he_80m_in_160m_cap: 1;
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u32 rsvd4: 13;
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};
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struct rtw_hecap {
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u8 dev_cls: 1; //Device Class
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u8 ldpc: 1; //LDPC Coding In Payload
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u8 gi_ltf_1x0p8: 1; //HE SU PPDU With 1x HE-LTF And 0.8 µs GI
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u8 gi_ltf_4x0p8: 1; //HE SU PPDU And HE MU PPDU With 4x HE-LTF And 0.8 µs GI
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u8 ul_mu:1; //Full Bandwidth UL MU-MIMO
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u8 prtl_ul_mu:1; //Partial Bandwidth UL MU-MIMO
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u8 prtl_dl_mu:1; //Partial Bandwidth DL MU-MIMO
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u8 pwr_bst_fac: 1; //Power Boost Factor Support
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u8 tx_1024_le242: 1; //Tx 1024-QAM < 242-tone RU Support
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u8 rx_1024_le242: 1; //Rx 1024-QAM < 242-tone RU Support
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u8 rsvd0: 6;
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u8 rsvd1;
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u8 rsvd2;
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};
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struct rtw_ehtcap {
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u8 rx_242_20only: 1; //Support For 242-tone RU In BW Wider Than 20 MHz
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u8 gi_ltf_4x0p8: 1; //EHT MU PPDU With 4x EHT-LTF And 0.8 µs GI
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u8 tx1024_4096_le242: 1; //Tx 1024-QAM And 4096-QAM < 242-tone RU Support
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u8 rx1024_4096_le242: 1; //Rx 1024-QAM And 4096-QAM < 242-tone RU Support
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u8 prtl_ul_mu: 1; //Partial Bandwidth UL MU-MIMO
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u8 prtl_dl_mu: 1; //Partial BandwidthDL MU-MIMO
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u8 pwr_bst_fac: 1; //Power Boost Factor Support
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u8 rsvd1: 1;
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u8 rx1024_prtlbw_only: 1; //Rx 1024-QAM In Wider Bandwidth DL OFDMA Support
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u8 rx4096_prtlbw_only: 1; //Rx 4096-QAM In Wider Bandwidth DL OFDMA Support
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u8 rsvd2: 6;
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u8 mcs15:4; //Support Of MCS 15
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u8 mcs14_6g:1; //Support Of EHT DUP (MCS 14) In 6 GHz
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u8 rsvd3:3;
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u8 rsvd4;
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};
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struct rtw_macid_info {
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u16 macid;
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u8 rsvd0;
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u8 rsvd1;
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u8 sta_typ:3;
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u8 is_mlo:1;
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u8 band:2;
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u8 rsvd2:2;
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u8 ldpc:1;
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u8 nss:3;
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u8 bw:3;
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u8 rsvd3:1;
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u8 rsvd4;
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u8 rsvd5;
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struct rtw_hecap he;
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struct rtw_ehtcap eht;
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};
|
|
struct rtw_ul_macid_cfg {
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u32 macid: 16;
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u32 endcmd: 1;
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u32 rsvd0: 15;
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u32 ul_su_info_en: 1;
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u32 ul_su_gi_ltf: 3;
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u32 rsvd1: 2;
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u32 ul_su_doppler_ctrl: 2;
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u32 ul_su_dcm: 1;
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u32 ul_su_ss: 3;
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u32 ul_su_mcs: 4;
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u32 ul_su_bw: 3;
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u32 ul_su_stbc: 1;
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u32 ul_su_coding: 1;
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u32 rsvd2: 2;
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u32 ul_su_rssi_m: 9;
|
|
u32 fix_ru_pos: 1;
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u32 fix_rate: 1;
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u32 fix_dbw: 1;
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u32 fix_giltf: 1;
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u32 fix_tgt_rssi: 1;
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u32 fix_coding: 1;
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u32 rsvd3: 2;
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u32 rsvd4: 8;
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u32 tx_mode_ul: 2;
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u32 rsvd5: 2;
|
u32 rsvd6: 3;
|
u32 ps160: 1;
|
u32 ru_pos: 8;
|
};
|
|
struct rtw_ul_macid_set {
|
struct rtw_ul_macid_cfg ul_macid_cfg[8];
|
};
|
|
struct rtw_csiinfo_cfg {
|
u32 macid: 16;
|
u32 csi_info_bitmap: 16;
|
};
|
|
struct rtw_cqi_info {
|
u32 macid: 16;
|
u32 fw_cqi_flag: 1; /* UL or DL*/
|
u32 ru_rate_table_row_idx: 4; /* UL or DL*/
|
u32 ul_dl: 1; /*1'b0 means UL, 1'b1 means DL */
|
u32 endcmd: 1;
|
u32 rsvd0: 1;
|
u32 rsvd1: 8;
|
|
s8 cqi_diff_table[19]; /* UL or DL*/
|
u8 rsvd2;
|
};
|
|
struct rtw_cqi_set{
|
struct rtw_cqi_info cqi_info[8];
|
};
|
|
struct rtw_ch_bw_notif{
|
u8 band_idx;
|
u8 band_type;
|
u8 pri_ch;
|
u8 central_ch;
|
enum channel_width cbw;
|
};
|
|
struct rtw_bbinfo_cfg {
|
//ch_bw info update
|
u32 chbw_upd_en:1;
|
u32 rsvd0:7;
|
u32 band_idx:4;
|
u32 band_type:4;
|
u32 pri_ch:8;
|
u32 central_ch:8;
|
|
u32 cbw:8;
|
u32 rsvd1:24;
|
|
//trx path info update
|
u32 trxpath_upd_en:1;
|
u32 rsvd2:7;
|
u32 txpath_num:4;
|
u32 rxpath_num:4;
|
u32 rsvd3:16;
|
|
//txsc info update
|
u32 txsc_upd_en:1;
|
u32 rsvd4:31;
|
|
u32 txsc_20:8;
|
u32 txsc_40:8;
|
u32 txsc_80:8;
|
u32 txsc_160:8;
|
|
//txsb info update
|
};
|
|
|
struct rtw_txpwr_tbl{
|
s8 byrate[32];
|
|
s8 lim_bw20_1t[8];
|
s8 lim_bw40_1t[4];
|
s8 lim_bw80_1t[2];
|
s8 lim_bw160_1t[1];
|
s8 rsvd0[1];
|
|
s8 lim_bw20_2t[8];
|
s8 lim_bw40_2t[4];
|
s8 lim_bw80_2t[2];
|
s8 lim_bw160_2t[1];
|
s8 rsvd1[1];
|
|
s8 lim_bw20_bf_1t[8];
|
s8 lim_bw40_bf_1t[4];
|
s8 lim_bw80_bf_1t[2];
|
s8 lim_bw160_bf_1t[1];
|
s8 rsvd2[1];
|
|
s8 lim_bw20_bf_2t[8];
|
s8 lim_bw40_bf_2t[4];
|
s8 lim_bw80_bf_2t[2];
|
s8 lim_bw160_bf_2t[1];
|
s8 rsvd3[1];
|
};
|
|
struct rtw_pwrtbl_notif{
|
u32 txpwrtbl_ofld_en:1;
|
u32 rsvd0:7;
|
u32 band_idx:4;
|
u32 rsvd1:4;
|
u32 rsvd2:16;
|
|
struct rtw_txpwr_tbl txpwr_tbl;
|
};
|
|
struct rtw_pwr_by_rt_tbl{
|
s16 pwr_by_rt[32];
|
};
|
|
struct rtw_ra_masking{
|
u16 macid;
|
u8 ra_sel:4;
|
u8 rsvd1:4;
|
u8 op_sel:4;
|
u8 rsvd2:4;
|
|
u32 mask_1ss;
|
u32 mask_2ss;
|
u32 mask_3ss;
|
u32 mask_4ss;
|
};
|
|
|
/*@--------------------------[Prptotype]-------------------------------------*/
|
struct bb_info;
|
//u32 halbb_upd_dlru_fixtbl(struct bb_info *bb,
|
// struct rtw_dl_ru_fix_tbl *info);
|
u32 halbb_upd_dlru_fixtbl(struct bb_info *bb,
|
union rtw_dlru_fixtbl *union_info);
|
u32 halbb_upd_dlru_grptbl(struct bb_info *bb,
|
struct rtw_dl_ru_gp_tbl *info);
|
// u32 halbb_upd_ulru_fixtbl(struct bb_info *bb,
|
// struct rtw_ul_ru_fix_tbl *info);
|
u32 halbb_upd_ulru_fixtbl(struct bb_info *bb,
|
union rtw_ulru_fixtbl *union_info);
|
u32 halbb_upd_ulru_grptbl(struct bb_info *bb,
|
struct rtw_ul_ru_gp_tbl *info);
|
u32 halbb_upd_rusta_info(struct bb_info *bb,
|
struct rtw_ru_sta_info *info);
|
u32 halbb_upd_ba_infotbl(struct bb_info *bb,
|
struct rtw_ba_tbl_info *info);
|
u32 halbb_swgrp_hdl(struct bb_info *bb,
|
struct rtw_sw_grp_set *info);
|
|
u32 halbb_dlmacid_cfg(struct bb_info *bb, struct rtw_dl_macid_cfg *cfg);
|
|
u32 halbb_ulmacid_cfg(struct bb_info *bb, struct rtw_ul_macid_set *cfg);
|
|
u32 halbb_csiinfo_cfg(struct bb_info *bb, struct rtw_csiinfo_cfg *cfg);
|
|
u32 halbb_cqi_cfg(struct bb_info *bb, struct rtw_cqi_set *cfg);
|
|
u32 halbb_bbinfo_cfg(struct bb_info *bb, struct rtw_bbinfo_cfg *cfg);
|
|
u32 halbb_pbr_tbl_cfg(struct bb_info *bb, struct rtw_pwr_by_rt_tbl *cfg);
|
|
u32 halbb_trxpath_notif(struct bb_info *bb, enum rf_path tx_path,
|
enum rf_path rx_path);
|
|
u32 halbb_ch_bw_notif(struct bb_info *bb, struct rtw_ch_bw_notif *cfg);
|
|
u32 halbb_pwrtbl_notif(struct bb_info *bb, struct rtw_pwrtbl_notif *cfg);
|
|
u32 halbb_macid_init(struct bb_info *bb, struct rtw_macid_info *cfg);
|
|
u32 halbb_ra_masking(struct bb_info *bb, struct rtw_ra_masking *cfg);
|
/*u32 halbb_rua_tbl_init(struct bb_info *bb);*/
|
#endif
|
#endif
|
