/******************************************************************************
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*
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* Copyright(c) 2019 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef _HALBB_RA_L_ENDIAN_H_
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#define _HALBB_RA_L_ENDIAN_H_
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/*@--------------------------[Define] ---------------------------------------*/
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/*@--------------------------[Enum]------------------------------------------*/
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/*@--------------------------[Structure]-------------------------------------*/
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struct bb_fw_cmac_rpt_info {
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/* dword 0 */
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u32 rpt_sel: 5;
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u32 polluted: 1;
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u32 tx_state: 2;
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u32 sw_define: 4;
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u32 rsvd0: 2;
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u32 try_rate: 1;
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u32 fix_rate: 1;
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u32 macid: 7;
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u32 rsvd1: 1;
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u32 qsel: 6;
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u32 rsvd2: 1;
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u32 txop_start: 1;
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/* dword 1 */
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u32 queue_time: 16;
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u32 acc_tx_time: 8;
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u32 rsvd3: 5;
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u32 bmc: 1;
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u32 bitmap_short: 2;
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/* dword 2 */
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u32 final_rate: 9;
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u32 final_gi_ltf: 3;
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u32 data_bw: 2;
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u32 mu2su: 1;
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u32 mu_lmt: 1;
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u32 final_rts_rate: 9;
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u32 final_rts_gi_ltf: 3;
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u32 rts_tx_state: 2;
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u32 collision_head: 1;
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u32 collision_tail: 1;
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/* dword 3 */
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u32 total_pkt_num: 8;
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u32 data_tx_cnt: 6;
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u32 bpri: 1;
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u32 bbar: 1;
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u32 pkt_ok_num: 8;
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u32 rts_tx_count: 6;
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u32 rsvd4: 2;
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/* dword 4 */
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u32 init_rate: 9;
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u32 init_gi_ltf: 3;
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u32 ppdu_type: 2;
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u32 he_tb_ppdu_flag: 1;
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u32 ppdu_fst_rpt: 1;
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u32 su_txpwr: 6;
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u32 rsvd5: 2;
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u32 diff_pkt_num: 4;
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u32 user_define_ext_l: 4;
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/* dword 5 */
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u32 user_define: 8;
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u32 fw_define: 8;
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u32 txpwr_pd: 5;
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u32 bsr: 1;
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u32 rsvd6: 2;
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u32 sr_rx_count: 4;
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u32 user_define_ext_h: 4;
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};
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struct bb_h2c_ra_cfg_info {
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u8 is_dis_ra:1;
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u8 mode_ctrl:5;
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/*
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@ Bit0 : CCK
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@ Bit1 : OFDM
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@ Bit2 : HT
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@ Bit3 : VHT
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@ Bit4 : HE
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*/
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u8 bw_cap:2;
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u8 macid;
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u8 dcm_cap:1;
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u8 er_cap:1;
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u8 init_rate_lv:2;
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u8 upd_all:1;
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u8 en_sgi:1;
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u8 ldpc_cap:1;
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u8 stbc_cap:1;
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u8 ss_num:3;
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u8 giltf_cap:3;
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u8 upd_bw_nss_mask:1;
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u8 upd_mask:1;
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u8 ramask[8]; /* ramask[7] bit 7 is for indicate bfee csi rate ctrl */
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/* BFee CSI rate ctrl */
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u8 band_num;
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u8 ra_csi_rate_en:1;
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u8 fixed_csi_rate_en:1;
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u8 cr_tbl_sel:1;
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u8 fix_giltf_en:1;
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u8 fix_giltf:3;
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u8 partial_bw_su_er:1;
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u8 fixed_csi_rate_l;
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u8 is_noisy:1; /*nhm_ratio >= 1% then disable ra bw switch for 92XB, WLANBB-2227*/
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u8 rsvd0:4;
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u8 band:2;
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u8 is_new_bb_ra_dbgreg:1;
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};
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struct bb_h2c_rssi_setting {
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u8 macid;
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u8 rssi_a; /* BIT(7) : parse rssi_b*/
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u8 bcn_rssi_a; /* BIT(7) : parse bcn_rssi*/
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u8 bcn_rssi_b;
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u8 dtp_lv: 2;
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u8 rsvd1: 6;
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u8 is_fixed_rate:1;
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u8 fixed_rate:6;
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u8 fixed_is_mu:1;
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u8 fixed_rate_md:2;
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u8 fixed_giltf:3;
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u8 fixed_bw:2;
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u8 rsvd2_M:1;
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u8 rssi_b:7;
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u8 endcmd:1;
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};
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struct bb_h2c_ra_cfg_info_wifi7 {
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struct bb_h2c_ra_cfg_info bb_h2c_ra_cmn;
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u8 mode_ctrl_eht:7;
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u8 rsvd0:1;
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u8 bw_cap_eht:3;
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u8 rsvd1:5;
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u8 ramask[4];
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};
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struct bb_h2c_rssi_setting_wifi7 {
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u8 macid;
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u8 rssi_a; /* BIT(7) : parse rssi_b*/
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u8 bcn_rssi_a; /* BIT(7) : parse bcn_rssi*/
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u8 bcn_rssi_b;
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u8 fixed_rate_M:1;
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u8 fixed_bw_M:1;
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u8 fixed_rate_md_M:1;
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u8 rsvd0_M:5;
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u8 is_fixed_rate:1;
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u8 fixed_rate:7;
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u8 fixed_rate_md:2;
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u8 fixed_giltf:3;
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u8 fixed_bw:2;
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u8 fixed_is_mu:1;
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u8 rssi_b:7;
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u8 endcmd:1;
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};
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struct bb_h2c_ra_mask {
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u8 macid;
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u8 mask_or_reveal:1;
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u8 mask_rate:7;
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u8 mask_rate_md:2;
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u8 is_manual_adjust_ra_mask:1;
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u8 rsvd1:5;
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u8 rsvd2;
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};
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struct bb_h2c_ra_adjust {
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u8 macid;
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u8 drv_shift_value:7;
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u8 drv_shift_en:1;
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u8 rsvd[2];
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};
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struct bb_h2c_ra_d_o_timer {
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u8 macid;
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u8 d_o_timer_value:7;
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u8 d_o_timer_en:1;
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u8 rsvd[2];
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};
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struct bb_h2c_ra_shift_dafc_tc {
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u8 enable;
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u8 init_fb_cnt[24]; /*1ss MCS0 ~ 2ss MCS11*/
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u8 rsvd[3];
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};
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struct bb_h2c_mu_cfg {
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u8 cmd_type;
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u8 entry;
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u8 macid;
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u8 en_256q:1;
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u8 en_1024q:1;
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u8 rsvd3:6;
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};
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struct bb_h2c_ra_tx_info {
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u16 macid;
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u16 rsvd0;
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};
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struct halbb_c2h_dbg_rpt_wifi7 {
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u8 per;
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u8 rdr;
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u8 r4;
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u8 cls;
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u8 rate_up_lmt_cnt;
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u8 per_ma;
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u8 var;
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u8 d_o_n;
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u8 d_o_p;
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u8 rd_th;
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u8 ru_th;
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u8 try_per;
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u8 try_rdr;
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u8 try_r4;
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u8 txrpt_tot;
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u8 ra_timer;
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u8 tot_disra_trying_return;
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u8 r4_return;
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u8 highest_rate;
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u8 lowest_rate;
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u32 macid:16;
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u32 rsvd0:16;
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u32 cmac_tbl;
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u32 ra_mask_h;
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u32 ra_mask_l;
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u32 upd_all_h2c_0;
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u32 upd_all_h2c_1;
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u32 upd_all_h2c_2;
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u32 upd_all_h2c_3;
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};
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struct halbb_ra_rpt_info {
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u8 rpt_macid_l;
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u8 rpt_macid_m;
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u8 retry_ratio;
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u8 u0_muidx: 3;
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u8 u1_muidx: 3;
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u8 en_stbc: 1;
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u8 rpt_mcs_nss_M: 1;
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u8 rpt_mcs_nss: 7;
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u8 is_mu: 1;
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u8 rpt_md_sel: 2;
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u8 rpt_gi_ltf: 3;
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u8 rpt_bw: 2;
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u8 rpt_md_sel_M: 1;
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u8 rpt_bw_M: 1;
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u8 rsvd0: 7;
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u8 rsvd1;
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};
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struct halbb_txsts_info {
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u8 rpt_macid_l;
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u8 rpt_macid_m;
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u8 avg_agg;
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u8 rsvd0;
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u8 tx_ok_be_l;
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u8 tx_ok_be_m;
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u8 tx_ok_bk_l;
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u8 tx_ok_bk_m;
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u8 tx_ok_vi_l;
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u8 tx_ok_vi_m;
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u8 tx_ok_vo_l;
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u8 tx_ok_vo_m;
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u8 tx_retry_be_l;
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u8 tx_retry_be_m;
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u8 tx_retry_bk_l;
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u8 tx_retry_bk_m;
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u8 tx_retry_vi_l;
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u8 tx_retry_vi_m;
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u8 tx_retry_vo_l;
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u8 tx_retry_vo_m;
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u8 tx_rate_l;
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u8 tx_rate_m;
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u8 retry_ratio;
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u8 rsvd1;
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u8 tx_total_l;
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u8 tx_total_m;
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u8 rsvd2;
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u8 rsvd3;
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u8 rsvd4;
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u8 rsvd5;
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u8 rsvd6;
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u8 rsvd7;
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};
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/*@--------------------------[Prptotype]-------------------------------------*/
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#endif
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