/******************************************************************************
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*
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* Copyright(c) 2007 - 2020 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef _HALBB_PLCP_GEN_H_
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#define _HALBB_PLCP_GEN_H_
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/* ============================================================
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define
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============================================================
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*/
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#define N_USER 4
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/* ============================================================
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structure
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============================================================
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*/
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struct plcp_mcs_table_in_t {
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u8 spec_idx : 3;
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u8 mcs : 5;
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u8 nss : 4;
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u8 bw : 3;//0:BW20, 1:BW40, 2:BW80, 3:BW160 4:BW320 /*enum channel_width*/
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u8 rsvd0 : 1;
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u8 ru_size : 5; //0:RU26, 1:RU52, 2:RU106, 3:RU242, 4:RU484, 5:RU996, 6:RU996x2, 7:hesigb, 8:RU996x4, 9:RU52_26, 10:RU106_26, 11:RU484_242, 12:RU996_484, ..., 16:RU996X3_484
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u8 rsvd1 : 3;
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bool dcm;
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bool fec;
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};
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struct plcp_mcs_table_out_t {
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u32 n_dbps : 19;
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u32 rsvd0 : 13;
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u32 he_n_dbps_short : 17;
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u32 rsvd1 : 15;
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u32 n_cbps : 19;
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u32 rsvd2 : 13;
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u32 n_es : 4;
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u32 valid : 1;
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u32 code_rate : 2;
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u32 nss : 3;
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u32 he_n_cbps_short : 17;
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u32 rsvd3 : 4;
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bool dcm;
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bool fec;
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};
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//========== [Par] ==========//
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struct com_pre_fec_par {
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u16 n_sym_init : 11;
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u16 spec_idx : 3;
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u16 pre_fec_padding_factor_init : 3;
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u16 ndp_en : 1;
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u16 preamble_0p4us : 16;
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u8 m_stbc : 2;
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u8 stbc : 1;
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u8 doppler_mode : 2;
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u8 gi : 2;
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u32 t_sym_0p4us : 6;
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u32 t_ltf_sym_0p4us : 6;
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u32 n_ltf_sym : 4;
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u32 n_sts_max : 4;
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u32 n_ma : 6;
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u32 m_ma : 5;
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u32 tb_trig : 1;
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u32 n_hesigb_sym : 8;
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u32 n_usr_refine : 8;
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u32 tb_trig_t_pe : 3;
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u32 tb_ldpc_extra : 1;
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u32 rsvd1 : 12;
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};
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struct usr_pre_fec_par {
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u32 n_excess : 15;
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u32 pre_fec_padding_factor_init : 3;
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u32 n_sym_init : 11;
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u32 rsvd0 : 3;
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u32 n_dbps_last_init : 17;
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u32 n_mpdu_refine : 10;
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u32 rsvd1 : 5;
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u32 n_cbps_last_init : 18;
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u32 mpdu_length_byte_refine : 14;
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u32 apep_refine : 22;
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u32 ru_size_refine : 5;
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u32 rsvd3 : 5;
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};
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struct plcp_tx_pre_fec_padding_setting_par_t {
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struct com_pre_fec_par com;
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struct plcp_mcs_table_out_t usr_mcs_out[4];
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struct usr_pre_fec_par usr[N_USER];
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};
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//========== [Input] ==========//
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struct usr_pre_fec_in {
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u8 ru_size_idx : 5;
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u8 rsvd0 : 3;
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u8 nss : 4;
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u8 rsvd1 : 4;
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u8 mcs : 6;
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u8 rsvd2 : 2;
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u32 apep : 22;
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u32 n_mpdu : 10;
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u16 mpdu_length_byte : 14;
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u16 rsvd4 : 2;
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bool dcm;
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bool fec;
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};
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struct plcp_tx_pre_fec_padding_setting_in_t {
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u8 format_idx : 4;
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u8 stbc : 1;
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u8 he_dcm_sigb : 1;
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u8 doppler_mode : 2; //0: diable ,1:MA10, 2:MA20
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u16 n_hesigb_sym : 11; // Shared para. with n_ehtsig_sym
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u16 he_mcs_sigb : 3;
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u16 nominal_t_pe : 2;
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u8 dbw : 3; //0:BW20, 1:BW40, 2:BW80, 3:BW160 4:BW320 /*enum channel_width*/
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u8 rsvd0 : 5;
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u16 gi : 2; //0.4,0.8,1.6,3.2
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u16 ltf_type : 2; //1x, 2x, 4x
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u16 ness : 2;
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u16 rsvd1 : 10;
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u32 mode_idx : 2; //0:apep, 1:max_tx_time, 2:n_mpdu,mpdu_len, 3:tb_trigger_mode
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u32 max_tx_time_0p4us : 14;
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u32 n_user : 8;
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u32 ndp : 1;
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u32 he_er_u106ru_en : 1; //done
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u32 rsvd2 : 6;
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u32 tb_l_len : 12;
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u32 tb_ru_tot_sts_max : 3;
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u32 tb_disam : 1;
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u32 tb_ldpc_extra : 1;
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u32 tb_pre_fec_padding_factor : 2;
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u32 ht_l_len : 12;
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u32 rsvd3 : 10;
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struct usr_pre_fec_in usr[N_USER];
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};
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//========== [Output] ==========//
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struct usr_pre_fec_out {
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u32 nss : 4;
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u32 nsts : 4;
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u32 mpdu_length_byte : 14;
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u32 n_mpdu : 10;
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u32 eof_padding_length : 32;
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u32 apep_len : 22;
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u32 ru_size : 8;
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u32 mcs_valid : 1;
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u32 rsvd1 : 1;
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u32 ru_idx : 8;
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u32 fec : 1;
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u32 dcm : 1;
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u32 rsvd2 : 22;
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};
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struct plcp_tx_pre_fec_padding_setting_out_t {
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u32 pre_fec_padding_factor : 2; // 0:4, 1:1, 2:2, 3:3
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u32 n_sym : 11;
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u32 ldpc_extra : 1;
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u32 n_sym_ehtsig : 5;
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u32 punc_ch_info : 5;
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u32 ppdu_type_comp_mode : 2;
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u32 rsvd : 2;
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u32 t_pe : 3; //0: 0us, 1:4us, 2:8us, 3:12us, 4:16us, 5:20us
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u32 valid : 1;
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u16 l_len : 12;
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u16 disamb : 1;
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u16 n_ltf : 3;
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u32 tx_time_0p4us;
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u32 stbc : 1;
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u32 doppler_en : 1;
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u32 midamble : 2;
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u32 n_usr : 8;
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u32 ndp : 1;
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u32 gi : 2;
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u32 n_sym_hesigb : 6;
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u32 plcp_valid : 8;
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u32 rvsd0 : 3;
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struct usr_pre_fec_out usr[N_USER];
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};
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/* ============================================================
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Enumeration
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============================================================
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*/
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enum spec_list {
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SPEC_B_MODE = 0,
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SPEC_LEGACY = 1,
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SPEC_HT = 2,
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SPEC_VHT = 3,
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SPEC_HE = 4,
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SPEC_EHT = 5
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};
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enum fec_t {
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BCC = 0,
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LDPC
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};
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enum coding_rate_t{
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R12 = 0,
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R23,
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R34,
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R56
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};
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/* ============================================================
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Function Prototype
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============================================================
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*/
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struct bb_info;
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u32 halbb_ceil(u32 numerator, u32 denominator);
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u32 halbb_mod(u32 numerator, u32 denominator);
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u32 halbb_min(u32 val_1, u32 val_2);
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u32 halbb_max(u32 val_1, u32 val_2);
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void halbb_set_bit(u8 strt, u8 len, u32 in, u32* out);
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enum plcp_sts halbb_tx_plcp_cal(struct bb_info *bb,
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const struct plcp_tx_pre_fec_padding_setting_in_t *in,
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struct plcp_tx_pre_fec_padding_setting_out_t *out);
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#endif
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