/******************************************************************************
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*
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* Copyright(c) 2007 - 2020 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __HALBB_LA_MODE_H__
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#define __HALBB_LA_MODE_H__
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/*@--------------------------[Define] ---------------------------------------*/
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#define LA_CHK_PTRN_NUM 4
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/*@--------------------------[Enum]------------------------------------------*/
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enum la_mac_src_t {
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LA_TRIG_SRC_T_MAC = 0,
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LA_TRIG_SRC_P_MAC = 1
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};
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enum la_run_mode_t {
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LA_RUN_HERITAGE = 0,
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LA_RUN_FAST = 1,
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LA_RUN_MANUAL = 2,
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LA_RUN_RTL_TEST = 3,
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LA_RUN_GET_MORE = 4,
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};
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enum la_state_trig_t {
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LA_AND_DISABLE = 0,
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LA_CCK_CCA = 1,
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LA_OFDM_CCA = 2,
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LA_OFDM_VBON = 3,
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LA_RX_TD_STATE = 4,
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LA_RX_STATE_FEQ = 5,
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LA_NO_USE = 6,
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LA_MUX_STATE = 7,
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LA_PHYTXON = 8,
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LA_BFMX_NDP_STANDBY = 9,
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LA_BFMX_CSI_STANDBY = 10,
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LA_CCA_SPOOF = 11,
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LA_RXPKT_OK_MX = 12,
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LA_RXPKT_FAIL_MX = 13,
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LA_BRK = 14,
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LA_BRK_SEL = 15,
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LA_HE_TB_STANDBY = 16,
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};
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enum la_hdr_sel_t {
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LA_HDR_ORI = 0,
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LA_HDR_CCA = 1,
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LA_HDR_CCA_OFDM = 2,
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LA_HDR_CCA_CCK = 3,
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LA_HDR_AGC_RDY = 4,
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LA_HDR_AGC_RDY_HT_OR_AMPDU_MISS = 5, /*AX: AGC_RDY_HT, BE: ampdu_miss*/
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LA_HDR_RXHT = 6,
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LA_HDR_RXVHT = 7,
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LA_HDR_RXHE_FULLBAND = 8,
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LA_HDR_RXHE_OFDMA = 9,
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LA_HDR_OFDM_VBON = 10,
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LA_HDR_RXPKT_OK_SYNC = 11,
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LA_HDR_RDRDY = 12,
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LA_HDR_CRC_OK = 13,
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LA_HDR_CRC_ERR = 14,
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#ifdef HALBB_COMPILE_LA_MODE_GEN2
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LA_HDR_RXEHT = 15,
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LA_HDR_GRANT_BT_RX = 16,
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LA_HDR_GRANT_BT_TX = 17,
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LA_HDR_GRANT_WL = 18,
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LA_HDR_PHYTXON = 19,
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LA_HDR_IS_POP = 20,
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LA_HDR_IS_SU = 21,
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LA_HDR_IS_MU_MINO = 22,
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LA_HDR_IS_BF = 23,
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LA_HDR_IS_STBC = 24,
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LA_HDR_IS_LDPC = 25,
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LA_HDR_IS_AWGN = 26,
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LA_HDR_IS_NDP = 27,
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LA_HDR_PHY_BB_IDX_TYPE_A = 28,
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LA_HDR_PHY_BB_IDX_TYPE_B = 29,
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LA_HDR_PHY_BB_IDX_TYPE_C = 30,
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LA_HDR_PHY_BB_IDX_TYPE_D = 31
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#endif
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};
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enum la_bb_trig_edge {
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LA_P_EDGE = 0,
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LA_N_EDGE = 1,
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};
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enum la_mac_polling_state {
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LA_HW_IDLE = 0,
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LA_HW_START = 1,
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LA_HW_FINISH_STOP = 2,
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LA_HW_FINISH_TIMEOUT = 3,
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LA_HW_RE_START = 4
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};
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enum la_mode_state_t {
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LA_STATE_IDLE = 0,
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LA_STATE_MAIN = 1,
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LA_STATE_GET_DLE_BUF = 2,
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LA_STATE_WAIT_RESTART = 3
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};
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enum la_buff_mode_t {
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LA_BUFF_64K = 0,
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LA_BUFF_128K = 1,
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LA_BUFF_192K = 2,
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LA_BUFF_256K = 3,
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LA_BUFF_320K = 4,
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LA_BUF_DISABLE = 0xff
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};
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enum la_bb_smp_clk {
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LA_SMP_CLK_80 = 0,
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LA_SMP_CLK_40 = 1,
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LA_SMP_CLK_20 = 2,
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LA_SMP_CLK_10 = 3,
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LA_SMP_CLK_5 = 4,
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LA_SMP_CLK_2_5 = 5,
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LA_SMP_CLK_1_25 = 6,
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LA_SMP_CLK_160 = 7,
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LA_SMP_CLK_320 = 8,
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LA_SMP_DEFAULT,
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LA_SMP_MAX
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};
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enum la_dma_data_type_t {
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DMA00_NRML_1s_14b = 0,
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DMA01_NRML_2s_12b = 1, /*Dbgport 16-bit: dbg[N, N-15]*/
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DMA02_NRML_2s_13b = 2, /*Dbgport 12-bit: dbg[N, N-11]*/
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DMA03_NRML_2s_14b = 3, /*Dbgport 08-bit: dbg[N, N-07]*/
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DMA04_NRML_3s_08b = 4,
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DMA05_NRML_3s_09b = 5,
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DMA06_NRML_3s_10b = 6,
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DMA07_NRML_4s_07b = 7,
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DMA08_NRML_4s_08b = 8,
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DMA09_DUAL_4s_12b = 9,
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DMA10_DUAL_4s_13b = 10,
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DMA11_DUAL_4s_14b = 11,
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DMA12_MPHS_1s_2p_12b = 12,
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DMA13_MPHS_1s_3p_10b = 13,
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DMA14_MPHS_1s_4p_08b = 14,
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DMA15_MPHS_2s_2p_08b = 15,
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DMA16_DBG_BB_MNTR = 16,
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DMA17_DUAL_WB_1s_14b = 17,
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DMA18_DUAL_WB_2s_14b = 18,
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DMA19_DUAL_WB_3s_14b = 19,
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DMA20_DUAL_WB_4s_14b = 20,
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DMA30_DBG_LA_SEL = 30
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};
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enum la_trig_sign_t {
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LA_UNSIGNED = 0,
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LA_SIGNED = 1,
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LA_NORM = 2,
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};
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enum la_input_src_sel_t {
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LA_SRC_DCCL_OUT = 0,
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LA_SRC_IQK = 1,
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LA_SRC_DFIR = 2,
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LA_SRC_ADC = 3,
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LA_SRC_TX_DAC = 4,
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LA_SRC_WB_ADC = 5,
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#ifdef HALBB_COMPILE_LA_MODE_GEN2
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LA_SRC_SAR_ADC = 6
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#endif
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};
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/*@--------------------------[Structure]-------------------------------------*/
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struct la_ptrn_chk_info {
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u32 smp_point;
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u32 la_ptrn_chk_mask; /*if mask=0: disable pattern chk, for MSB 32bit only*/
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u32 la_ptrn_chk_val;
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};
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struct la_print_info {
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bool is_la_print;
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u8 print_mode; /*0: hex, 1:unsign, 2:sign*/
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u8 print_lsb;
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u8 print_msb;
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u8 print_buff_opt; /*print to 0:Debug Log, 1: CNSL Buff*/
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};
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struct la_dma_info {
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u8 dma_dbgport_base_n;
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u8 dma_a_path_sel;
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u8 dma_b_path_sel;
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u8 dma_c_path_sel;
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u8 dma_d_path_sel;
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enum la_input_src_sel_t dma_a_src_sel;
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enum la_input_src_sel_t dma_b_src_sel;
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enum la_input_src_sel_t dma_c_src_sel;
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enum la_input_src_sel_t dma_d_src_sel;
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enum la_hdr_sel_t dma_hdr_sel_63;
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enum la_hdr_sel_t dma_hdr_sel_62;
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enum la_hdr_sel_t dma_hdr_sel_61;
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enum la_hdr_sel_t dma_hdr_sel_60;
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bool dma_a_ck160_dly_en;
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bool dma_b_ck160_dly_en;
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bool dma_c_ck160_dly_en;
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bool dma_d_ck160_dly_en;
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enum phl_phy_idx dma_dbcc_phy_sel;
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enum la_dma_data_type_t dma_data_type;
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#ifdef HALBB_COMPILE_LA_MODE_GEN2
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u8 dma_dbgport_ext_base_n;
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enum la_hdr_sel_t dma_hdr_sel_59;
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enum la_hdr_sel_t dma_hdr_sel_58;
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enum la_hdr_sel_t dma_hdr_sel_57;
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enum la_hdr_sel_t dma_hdr_sel_56;
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#endif
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};
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struct la_string_info {
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u32 *octet;
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u32 length;
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u32 buffer_size; /*Byte*/
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u32 start_pos;
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u32 end_pos; /*buf addr*/
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u32 smp_number_max; /*number of LA sample*/
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};
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struct la_re_trig_info {
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bool re_trig_en;
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u16 re_trig_wait_cnt;
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/*Re-trig*/
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bool la_re_trig_edge;
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u8 la_re_and0_sel;
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u8 la_re_and0_val;
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bool la_re_and0_inv;
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#ifdef HALBB_COMPILE_LA_MODE_GEN2
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u16 la_re_and0_mask;
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#endif
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};
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struct la_adv_trig_info { /*AND0~AND7*/
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bool adv_trig_en; /*SW ctrl value*/
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/*AND1*/
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u32 la_and1_mask; /*sel all 0 = disable*/
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u32 la_and1_val;
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bool la_and1_inv;
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/*AND2*/
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bool la_and2_en;
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bool la_and2_inv;
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u32 la_and2_val;
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u32 la_and2_mask;
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enum la_trig_sign_t la_and2_sign; /*0: unsigned, 1:signed, 2:norm*/
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/*AND3*/
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bool la_and3_en;
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bool la_and3_inv;
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u32 la_and3_val;
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u32 la_and3_mask;
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enum la_trig_sign_t la_and3_sign; /*0: unsigned, 1:signed, 2:norm*/
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/*AND4*/
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bool la_and4_en;
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u16 la_and4_rate; /*rate_idx*/
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bool la_and4_inv;
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/*AND5*/
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enum la_state_trig_t la_and5_sel;
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bool la_and5_inv;
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u8 la_and5_val;
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/*AND6*/
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enum la_state_trig_t la_and6_sel;
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bool la_and6_inv;
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u8 la_and6_val;
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/*AND7*/
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enum la_state_trig_t la_and7_sel;
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bool la_and7_inv;
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u8 la_and7_val;
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#ifdef HALBB_COMPILE_LA_MODE_GEN2
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bool la_and0_inv;
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u16 la_and5_mask;
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u16 la_and6_mask;
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u16 la_and7_mask;
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/*AND8*/
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u8 la_and8_base_n;
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bool la_and8_inv;
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u32 la_and8_mask;
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u32 la_and8_val;
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#endif
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};
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struct la_trig_mac_info {
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bool la_mac_trig_en; /*sw tag*/
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bool la_mac_and0_en;
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u8 la_mac_and0_sel; /*0:cca, 1:1st_crc_OK, 2:1st_crc_err, 3:OK, 4:err*/
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u8 la_mac_and0_tmac_pmac_sel; /*0: true mac, 1: pmac*/
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bool la_mac_and1_en;
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u8 la_mac_and1_addr; /*LSB 8 Bits of target MAC ADDRESS*/
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bool la_mac_and2_en;
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u8 la_mac_and2_frame_sel; /*6-bit mac hdr*/
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u8 la_mac_uid;
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#ifdef HALBB_COMPILE_LA_MODE_GEN2
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u8 la_mac_crc_pmac_pkt_sel; /*1: CCK 2: Legacy 3: HT 4: VHT 5: HE 6: EHT 7: A-MPDU default: all type crc*/
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#endif
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};
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struct la_mac_cfg_info {
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enum la_buff_mode_t mac_la_buf_sel;
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bool mac_alloc_success;
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u32 la_trigger_time; /*mu sec*/
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u8 mac_la_en;
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u8 mac_la_restart_en;
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u8 mac_la_timeout_en;
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u8 mac_la_data_loss_imr;/*Error flag mask bit for LA data loss due to pktbuffer busy */
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u8 mac_la_timeout_val; /*0:1s, 1:2s, 2:4s, 3:8s*/
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};
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struct bb_la_cr_info {
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u32 la_clk_en;
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u32 la_clk_en_m;
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u32 la_en;
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u32 la_en_m;
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u32 dma_dbgport_base_n;
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u32 dma_dbgport_base_n_m;
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u32 dma_a_path_sel;
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u32 dma_a_path_sel_m;
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u32 dma_b_path_sel;
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u32 dma_b_path_sel_m;
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u32 dma_c_path_sel;
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u32 dma_c_path_sel_m;
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u32 dma_d_path_sel;
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u32 dma_d_path_sel_m;
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u32 dma_a_src_sel;
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u32 dma_a_src_sel_m;
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u32 dma_b_src_sel;
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u32 dma_b_src_sel_m;
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u32 dma_c_src_sel;
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u32 dma_c_src_sel_m;
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u32 dma_d_src_sel;
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u32 dma_d_src_sel_m;
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u32 la_smp_rt_sel;
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u32 la_smp_rt_sel_m;
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u32 rdrdy_3_phase_en;
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u32 rdrdy_3_phase_en_m;
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u32 la_trigger_edge;
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u32 la_trigger_edge_m;
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u32 dma_hdr_sel_63;
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u32 dma_hdr_sel_63_m;
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u32 dma_hdr_sel_62;
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u32 dma_hdr_sel_62_m;
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u32 dma_hdr_sel_61;
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u32 dma_hdr_sel_61_m;
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u32 dma_hdr_sel_60;
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u32 dma_hdr_sel_60_m;
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u32 dma_a_ck160_dly_en;
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u32 dma_a_ck160_dly_en_m;
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u32 dma_b_ck160_dly_en;
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u32 dma_b_ck160_dly_en_m;
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u32 dma_dbgport_phy_sel;
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u32 dma_dbgport_phy_sel_m;
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u32 dma_la_phy_sel;
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u32 dma_la_phy_sel_m;
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u32 dma_data_type;
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u32 dma_data_type_m;
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u32 r_dma_rdrdy;
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u32 r_dma_rdrdy_m;
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u32 la_and0_bit_sel;
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u32 la_and0_bit_sel_m;
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u32 la_trigger_cnt;
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u32 la_trigger_cnt_m;
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u32 and0_trig_disable;
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u32 and0_trig_disable_m;
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u32 la_and1_inv;
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u32 la_and1_inv_m;
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u32 la_and2_en;
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u32 la_and2_en_m;
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u32 la_and2_inv;
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u32 la_and2_inv_m;
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u32 la_and3_en;
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u32 la_and3_en_m;
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u32 la_and3_inv;
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u32 la_and3_inv_m;
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u32 la_and4_en;
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u32 la_and4_en_m;
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u32 la_and4_rate;
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u32 la_and4_rate_m;
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u32 la_and4_inv;
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u32 la_and4_inv_m;
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u32 la_and1_mask;
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u32 la_and1_mask_m;
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u32 la_and1_val;
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u32 la_and1_val_m;
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u32 la_and2_mask;
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u32 la_and2_mask_m;
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u32 la_and2_val;
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u32 la_and2_val_m;
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u32 la_and3_mask;
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u32 la_and3_mask_m;
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u32 la_and3_val;
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u32 la_and3_val_m;
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u32 la_and5_sel;
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u32 la_and5_sel_m;
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u32 la_and5_val;
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u32 la_and5_val_m;
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u32 la_and5_inv;
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u32 la_and5_inv_m;
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u32 la_and6_sel;
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u32 la_and6_sel_m;
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u32 la_and6_val;
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u32 la_and6_val_m;
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u32 la_and6_inv;
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u32 la_and6_inv_m;
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u32 la_and7_sel;
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u32 la_and7_sel_m;
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u32 la_and7_val;
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u32 la_and7_val_m;
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u32 la_and7_inv;
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u32 la_and7_inv_m;
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u32 la_brk_sel;
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u32 la_brk_sel_m;
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u32 la_mac_and1_en;
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u32 la_mac_and1_en_m;
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u32 la_mac_and2_en;
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u32 la_mac_and2_en_m;
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u32 la_target_frame_type_en;
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u32 la_target_frame_type_en_m;
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u32 la_mac_addr_en;
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u32 la_mac_addr_en_m;
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u32 la_mac_addr;
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u32 la_mac_addr_m;
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u32 la_mac_multi_user_uid;
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u32 la_mac_multi_user_uid_m;
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u32 la_mac_and2_frame_sel;
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u32 la_mac_and2_frame_sel_m;
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u32 la_mac_and0_sel;
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u32 la_mac_and0_sel_m;
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u32 la_mac_and0_en;
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u32 la_mac_and0_en_m;
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u32 la_mac_and0_mac_sel;
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u32 la_mac_and0_mac_sel_m;
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u32 la_mac_and0_crc_src_sel;
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u32 la_mac_and0_crc_src_sel_m;
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u32 la_and2_sign;
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u32 la_and2_sign_m;
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u32 la_and3_sign;
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u32 la_and3_sign_m;
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u32 la_re_trig_edge;
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u32 la_re_trig_edge_m;
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u32 la_re_and1_sel;
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u32 la_re_and1_sel_m;
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u32 la_re_and1_val;
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u32 la_re_and1_val_m;
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u32 la_re_and1_inv;
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u32 la_re_and1_inv_m;
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u32 la_adc_320up;
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u32 la_adc_320up_m;
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u32 la_scope_mode_en;
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u32 la_scope_mode_en_m;
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u32 la_scope_mode_auto_fix_la;
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u32 la_scope_mode_auto_fix_la_m;
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#ifdef HALBB_COMPILE_LA_MODE_GEN2
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u32 la_dbg_port_ip_ext;
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u32 la_dbg_port_ip_ext_m;
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u32 la_dbg_port_ext;
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u32 la_dbg_port_ext_m;
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u32 dma_dbgport_ext_base_n;
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u32 dma_dbgport_ext_base_n_m;
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u32 dma_hdr_sel_59;
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u32 dma_hdr_sel_59_m;
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u32 dma_hdr_sel_58;
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u32 dma_hdr_sel_58_m;
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u32 dma_hdr_sel_57;
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u32 dma_hdr_sel_57_m;
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u32 dma_hdr_sel_56;
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u32 dma_hdr_sel_56_m;
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u32 la_and0_inv;
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u32 la_and0_inv_m;
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u32 la_and5_mask;
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u32 la_and5_mask_m;
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u32 la_and6_mask;
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u32 la_and6_mask_m;
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u32 la_and7_mask;
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u32 la_and7_mask_m;
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u32 la_and8_base_n;
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u32 la_and8_base_n_m;
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u32 la_and8_inv;
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u32 la_and8_inv_m;
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u32 la_and8_mask;
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u32 la_and8_mask_m;
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u32 la_and8_val;
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u32 la_and8_val_m;
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u32 la_re_and1_mask;
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u32 la_re_and1_mask_m;
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u32 la_mac_crc_pmac_pkt_sel;
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u32 la_mac_crc_pmac_pkt_sel_m;
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#endif
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};
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struct bb_la_mode_info {
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struct bb_la_cr_info bb_la_cr_i;
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struct la_string_info la_string_i;
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enum la_mode_state_t la_mode_state;
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u32 la_dbg_port; /*[31:16]:DBG_IP, [15:0]:DBG_PORT*/
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u32 la_count; /*curr value*/
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u32 la_count_max;
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u32 smp_number;
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u32 txff_page;
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bool not_stop_trig; /*set impossible trigger condition*/
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u8 la_basic_mode_sel; /*0:bb_mode, mac mode*/
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/*[General setting]*/
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u8 la_polling_cnt;
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u8 la_trigger_cnt;
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enum la_bb_trig_edge la_trigger_edge;
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enum la_bb_smp_clk la_smp_rate; /*CR Setting*/
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u16 la_smp_rate_log; /*20/40/80/160/320M, for debug log only*/
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#ifdef HALBB_LA_320M_PATCH
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bool la_1115_320up_clk_en;
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#endif
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/*[AND-0 sel]*/
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bool la_and0_disable;
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u32 la_and0_bit_sel; /*And0 trigger bit sel*/
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struct la_dma_info la_dma_i;
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struct la_re_trig_info la_re_trig_i;
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struct la_adv_trig_info adv_trig_i;
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struct la_trig_mac_info la_trig_mac_i;
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struct la_mac_cfg_info la_mac_cfg_i; /*MAC CR Control*/
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struct la_print_info la_print_i;
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bool la_ptrn_chk_en;
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struct la_ptrn_chk_info la_ptrn_chk_i[LA_CHK_PTRN_NUM];
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enum la_run_mode_t la_run_mode;
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struct halbb_timer_info la_timer_i;
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#ifdef HALBB_COMPILE_LA_MODE_GEN2
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u32 la_dbg_port_ext; /*[31:16]:DBG_IP, [15:0]:DBG_PORT*/
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#endif
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};
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struct bb_info;
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/*@--------------------------[Prptotype]-------------------------------------*/
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void halbb_la_re_trig_watchdog(struct bb_info *bb);
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void halbb_la_run(struct bb_info *bb);
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void halbb_la_deinit(struct bb_info *bb);
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void halbb_la_init(struct bb_info *bb);
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void halbb_cr_cfg_la_init(struct bb_info *bb);
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void halbb_la_io_en(struct bb_info *bb);
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void halbb_la_timer_init(struct bb_info *bb);
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void halbb_la_callback(void *context);
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void halbb_la_cmd_dbg(struct bb_info *bb, char input[][16], u32 *_used, char *output,
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u32 *_out_len);
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#endif
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