/*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright (c) 2021, Realtek Semiconductor Corp. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* * Neither the name of the Realtek nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __HALBB_IC_HW_INFO_H__
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#define __HALBB_IC_HW_INFO_H__
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#include "halbb_cfg_ic.h"
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enum bb_ic_t {
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/*AC IC*/
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BB_RTL8852A = BIT(1), /*8852A > Bcut*/
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BB_RTL8852B = BIT(2),
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BB_RTL8852C = BIT(3),
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BB_RTL8834A = BIT(4),
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BB_RTL8192XB = BIT(5),
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BB_RTL8851B = BIT(6),
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/*BE IC*/
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BB_RLE1115 = BIT(16),
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BB_RTL8922A = BIT(17),
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BB_RTL8934A = BIT(18),
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BB_RTL8952A = BIT(19)
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};
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enum bb_ic_sub_t {
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BB_IC_SUB_TYPE_8852B_8852B = 20,
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BB_IC_SUB_TYPE_8852B_8852BP,
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BB_IC_SUB_TYPE_8852B_8852BT,
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BB_IC_SUB_TYPE_8852C_8852C = 30,
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BB_IC_SUB_TYPE_8852C_8852D,
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BB_IC_SUB_TYPE_8192XB_8192XB = 50,
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BB_IC_SUB_TYPE_8192XB_8832BR,
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BB_IC_SUB_TYPE_8192XB_8832BR_VT
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};
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enum bb_cr_t {
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BB_AP = 1,
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BB_AP2 = 2,
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BB_CLIENT = 3,
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BB_BE0 = 4,
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BB_BE1 = 5,
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BB_BE2 = 6
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};
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enum bb_80211spec_t {
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BB_AX_IC = 1,
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BB_BE_IC = 2
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};
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#define BB_IC_N_1SS 0
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#define BB_IC_N_2SS 0
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#define BB_IC_N_3SS 0
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#define BB_IC_N_4SS 0
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#define BB_IC_AC_1SS 0
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#define BB_IC_AC_2SS 0
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#define BB_IC_AC_3SS 0
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#define BB_IC_AC_4SS 0
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#define BB_IC_AX_1SS BB_RTL8851B
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#define BB_IC_AX_2SS (BB_RTL8852A | BB_RTL8852B | BB_RTL8852C |\
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BB_RTL8192XB)
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#define BB_IC_AX_3SS 0
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#define BB_IC_AX_4SS (BB_RTL8834A)
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#define BB_IC_BE_1SS 0
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#define BB_IC_BE_2SS (BB_RLE1115 | BB_RTL8922A)
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#define BB_IC_BE_3SS 0
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#define BB_IC_BE_4SS (BB_RTL8934A)
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/*@====the following macro DO NOT need to update when adding a new IC======= */
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#define BB_IC_1SS (BB_IC_N_1SS | BB_IC_AC_1SS | BB_IC_AX_1SS | BB_IC_BE_1SS)
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#define BB_IC_2SS (BB_IC_N_2SS | BB_IC_AC_2SS | BB_IC_AX_2SS | BB_IC_BE_2SS)
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#define BB_IC_3SS (BB_IC_N_3SS | BB_IC_AC_3SS | BB_IC_AX_3SS | BB_IC_BE_3SS)
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#define BB_IC_4SS (BB_IC_N_4SS | BB_IC_AC_4SS | BB_IC_AX_4SS | BB_IC_BE_4SS)
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#define BB_IC_ABOVE_1SS (BB_IC_1SS | BB_IC_2SS | BB_IC_3SS |\
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BB_IC_4SS)
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#define BB_IC_ABOVE_2SS (BB_IC_2SS | BB_IC_3SS | BB_IC_4SS)
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#define BB_IC_ABOVE_3SS (BB_IC_3SS | BB_IC_4SS)
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#define BB_IC_ABOVE_4SS BB_IC_4SS
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#define BB_IC_N_SERIES (BB_IC_N_1SS | BB_IC_N_2SS | BB_IC_N_3SS |\
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BB_IC_N_4SS)
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#define BB_IC_AC_SERIES (BB_IC_AC_1SS | BB_IC_AC_2SS |\
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BB_IC_AC_3SS | BB_IC_AC_4SS)
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#define BB_IC_AX_SERIES (BB_IC_AX_1SS | BB_IC_AX_2SS |\
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BB_IC_AX_3SS | BB_IC_AX_4SS)
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#define BB_IC_BE_SERIES (BB_IC_BE_1SS | BB_IC_BE_2SS |\
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BB_IC_BE_3SS | BB_IC_BE_4SS)
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/*@==========================================================================*/
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#define BB_IC_AX_AP (BB_RTL8852A | BB_RTL8834A)
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#define BB_IC_AX_AP2 (BB_RTL8852C | BB_RTL8192XB)
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#define BB_IC_AX_CLIENT (BB_RTL8852B | BB_RTL8851B)
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#define BB_IC_BE_0 (BB_RLE1115)
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#define BB_IC_BE_1 (BB_RTL8922A)
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#define BB_IC_BE_2 (BB_RTL8934A)
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/*@==========================================================================*/
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#define BB_IC_FW_CONTROL_STBC (BB_RTL8852A | BB_RTL8852B | BB_RTL8851B)
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/*@==========================================================================*/
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#define BB_IC_MAX_BW_80 (BB_RTL8852A | BB_RTL8852B | BB_RTL8192XB |\
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BB_RTL8851B)
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#define BB_IC_MAX_BW_160 (BB_RTL8852C | BB_RTL8834A)
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/*@==========================================================================*/
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#define BB_IC_DBCC_LEGACY (BB_RTL8852A | BB_RTL8852C)
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#define BB_IC_DBCC_MLO (BB_RLE1115)
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#define BB_IC_DBCC_LITTLE_R (BB_RTL8922A)
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/*@==========================================================================*/
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#if defined(BB_8852A_2_SUPPORT) || defined(BB_8852C_SUPPORT)
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#define HALBB_COMPILE_IC_DBCC_LEGACY
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#endif
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#if defined(BB_8922A_SUPPORT) || defined(BB_1115_SUPPORT)
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#define HALBB_COMPILE_IC_DBCC_MLO
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#endif
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#if defined(HALBB_COMPILE_IC_DBCC_LEGACY) || defined(HALBB_COMPILE_IC_DBCC_MLO)
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#define HALBB_COMPILE_IC_DBCC
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#endif
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#if defined(BB_8922A_SUPPORT)
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#define HALBB_COMPILE_IC_DBCC_LITTLE_R
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#endif
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/*@==========================================================================*/
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#if defined(BB_8852A_2_SUPPORT) || defined(BB_8852B_SUPPORT) || defined(BB_8852C_SUPPORT) || defined(BB_8851B_SUPPORT)
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/* FW OFFLOAD will be used in non-AP-only ICs*/
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#define HALBB_COMPILE_IC_FWOFLD
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#endif
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#if defined(BB_8851B_SUPPORT)
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#define HALBB_COMPILE_IC_1SS
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#endif
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#if (defined(BB_8852A_2_SUPPORT) || defined(BB_8852B_SUPPORT) ||\
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defined(BB_8852C_SUPPORT) || defined(BB_8192XB_SUPPORT) || defined(BB_1115_SUPPORT) || defined(BB_8922A_SUPPORT))
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#define HALBB_COMPILE_IC_2SS
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#endif
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#if defined(RTL8853A_SUPPORT)
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#define HALBB_COMPILE_IC_3SS
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#endif
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#if defined(RTL8834A_SUPPORT)
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#define HALBB_COMPILE_IC_4SS
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#endif
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/*@==========================================================================*/
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#if (defined(HALBB_COMPILE_IC_4SS))
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#define HALBB_COMPILE_ABOVE_4SS
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#endif
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#if (defined(HALBB_COMPILE_IC_3SS) || defined(HALBB_COMPILE_ABOVE_4SS))
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#define HALBB_COMPILE_ABOVE_3SS
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#endif
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#if (defined(HALBB_COMPILE_IC_2SS) || defined(HALBB_COMPILE_ABOVE_3SS) || defined(HALBB_COMPILE_ABOVE_4SS))
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#define HALBB_COMPILE_ABOVE_2SS
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#endif
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#if (defined(HALBB_COMPILE_IC_1SS) || defined(HALBB_COMPILE_ABOVE_2SS) || defined(HALBB_COMPILE_ABOVE_3SS) || defined(HALBB_COMPILE_ABOVE_4SS))
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#define HALBB_COMPILE_ABOVE_1SS
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#endif
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#if (defined(HALBB_COMPILE_ABOVE_4SS))
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#define HALBB_MAX_PATH 4
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#elif (defined(HALBB_COMPILE_ABOVE_3SS))
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#define HALBB_MAX_PATH 3
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#elif (defined(HALBB_COMPILE_ABOVE_2SS))
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#define HALBB_MAX_PATH 2
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#else
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#define HALBB_MAX_PATH 2
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#endif
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/*@==========================================================================*/
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#if (defined(BB_8852A_2_SUPPORT))
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#define HALBB_COMPILE_AP_SERIES
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#endif
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#if (defined(BB_8852C_SUPPORT) || defined(BB_8192XB_SUPPORT))
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#define HALBB_COMPILE_AP2_SERIES
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#endif
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#if (defined(BB_8852B_SUPPORT) || defined(BB_8851B_SUPPORT))
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#define HALBB_COMPILE_CLIENT_SERIES
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#endif
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#if (defined(BB_1115_SUPPORT))
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#define HALBB_COMPILE_BE0_SERIES
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#endif
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#if (defined(BB_8922A_SUPPORT))
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#define HALBB_COMPILE_BE1_SERIES
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#endif
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/*@==========================================================================*/
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#if (defined(HALBB_COMPILE_AP_SERIES)||defined(HALBB_COMPILE_AP2_SERIES)||defined(HALBB_COMPILE_CLIENT_SERIES))
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#define HALBB_COMPILE_AX_SERIOUS
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#endif
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#if (defined(HALBB_COMPILE_BE0_SERIES)||defined(HALBB_COMPILE_BE1_SERIES))
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#define HALBB_COMPILE_BE_SERIES
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#endif
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/*@==========================================================================*/
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#if (defined(BB_8852C_SUPPORT))
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#define HALBB_TW_DFS_SERIES
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#endif
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/*@==========================================================================*/
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enum bb_bw_type {
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BB_BW_05M = 5,
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BB_BW_10M = 10,
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BB_BW_20M = 20,
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BB_BW_40M = 40,
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BB_BW_80M = 80,
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BB_BW_160M = 160,
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BB_BW_80M_80M,
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BB_BW_320M = 320,
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};
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enum halbb_cmac_table_bw {
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BB_CMAC_BW_20M = 0,
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BB_CMAC_BW_40M = 1,
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BB_CMAC_BW_80M = 2,
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BB_CMAC_BW_160M = 3,
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BB_CMAC_BW_320M = 4
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};
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enum halbb_rate_type {
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BB_1SS = 1, /*HE/VHT/HT 1SS*/
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BB_2SS = 2, /*HE/VHT/HT 2SS*/
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BB_3SS = 3, /*HE/VHT/HT 3SS*/
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BB_4SS = 4, /*HE/VHT/HT 4SS*/
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BB_CCK = 11, /*B mode*/
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BB_OFDM = 12 /*G mode*/
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};
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enum halbb_rate_table {
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BB_01M = 0,
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BB_02M = 1,
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BB_05M = 2,
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BB_11M = 3,
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BB_06M = 4,
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BB_09M = 5,
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BB_12M = 6,
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BB_18M = 7,
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BB_24M = 8,
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BB_36M = 9,
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BB_48M = 10,
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BB_54M = 11,
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BB_HT_MCS0 = 128, /*0x1000000*/
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BB_VHT_1SS_MCS0 = 256, /*0x2000000*/
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BB_VHT_2SS_MCS0 = 272,
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BB_VHT_3SS_MCS0 = 288,
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BB_VHT_4SS_MCS0 = 304,
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BB_VHT_5SS_MCS0 = 320,
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BB_VHT_6SS_MCS0 = 336,
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BB_VHT_7SS_MCS0 = 352,
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BB_VHT_8SS_MCS0 = 368,
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BB_HE_1SS_MCS0 = 384, /*0x3000000*/
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BB_HE_2SS_MCS0 = 400,
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BB_HE_3SS_MCS0 = 416,
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BB_HE_4SS_MCS0 = 432,
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BB_HE_5SS_MCS0 = 448,
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BB_HE_6SS_MCS0 = 464,
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BB_HE_7SS_MCS0 = 480,
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BB_HE_8SS_MCS0 = 496
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};
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enum halbb_rate_table_be {
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BE_BB_01M = 0,
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BE_BB_02M = 1,
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BE_BB_05M = 2,
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BE_BB_11M = 3,
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BE_BB_06M = 4,
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BE_BB_09M = 5,
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BE_BB_12M = 6,
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BE_BB_18M = 7,
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BE_BB_24M = 8,
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BE_BB_36M = 9,
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BE_BB_48M = 10,
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BE_BB_54M = 11,
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BE_BB_HT_MCS0 = 256, /*0x100*/
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BE_BB_VHT_1SS_MCS0 = 512, /*0x200*/
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BE_BB_VHT_2SS_MCS0 = 544,
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BE_BB_VHT_3SS_MCS0 = 576,
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BE_BB_VHT_4SS_MCS0 = 608,
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BE_BB_VHT_5SS_MCS0 = 640,
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BE_BB_VHT_6SS_MCS0 = 672,
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BE_BB_VHT_7SS_MCS0 = 704,
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BE_BB_VHT_8SS_MCS0 = 736,
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BE_BB_HE_1SS_MCS0 = 768, /*0x300*/
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BE_BB_HE_2SS_MCS0 = 800,
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BE_BB_HE_3SS_MCS0 = 832,
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BE_BB_HE_4SS_MCS0 = 864,
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BE_BB_HE_5SS_MCS0 = 896,
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BE_BB_HE_6SS_MCS0 = 928,
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BE_BB_HE_7SS_MCS0 = 950,
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BE_BB_HE_8SS_MCS0 = 982,
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BE_BB_EHT_1SS_MCS0 = 1024, /*0x400*/
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BE_BB_EHT_2SS_MCS0 = 1056,
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BE_BB_EHT_3SS_MCS0 = 1088,
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BE_BB_EHT_4SS_MCS0 = 1120,
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BE_BB_EHT_5SS_MCS0 = 1152,
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BE_BB_EHT_6SS_MCS0 = 1184,
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BE_BB_EHT_7SS_MCS0 = 1216,
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BE_BB_EHT_8SS_MCS0 = 1248
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};
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enum halbb_legacy_spec_rate {
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BB_SPEC_RATE_6M = 0xb,
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BB_SPEC_RATE_9M = 0xf,
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BB_SPEC_RATE_12M = 0xa,
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BB_SPEC_RATE_18M = 0xe,
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BB_SPEC_RATE_24M = 0x9,
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BB_SPEC_RATE_36M = 0xd,
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BB_SPEC_RATE_48M = 0x8,
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BB_SPEC_RATE_54M = 0xc
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};
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#define GEN_HT_RATE_IDX(MCS) (0x80 | ((MCS) & 0x1f))
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#define GEN_VHT_RATE_IDX(SS, MCS) (0x100 | (((SS) & 0x3) << 4) | ((MCS) & 0xf))
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#define GEN_HE_RATE_IDX(SS, MCS) (0x180 | (((SS) & 0x3) << 4) | ((MCS) & 0xf))
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#define BB_HT_MCS(x) (BB_HT_MCS0 + x)
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#define BB_VHT_1SS_MCS(x) (BB_VHT_1SS_MCS0 + x)
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#define BB_VHT_2SS_MCS(x) (BB_VHT_2SS_MCS0 + x)
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#define BB_VHT_3SS_MCS(x) (BB_VHT_3SS_MCS0 + x)
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#define BB_VHT_4SS_MCS(x) (BB_VHT_4SS_MCS0 + x)
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#define BB_VHT_5SS_MCS(x) (BB_VHT_5SS_MCS0 + x)
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#define BB_VHT_6SS_MCS(x) (BB_VHT_6SS_MCS0 + x)
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#define BB_VHT_7SS_MCS(x) (BB_VHT_7SS_MCS0 + x)
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#define BB_VHT_8SS_MCS(x) (BB_VHT_8SS_MCS0 + x)
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#define BB_HE_1SS_MCS(x) (BB_HE_1SS_MCS0 + x)
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#define BB_HE_2SS_MCS(x) (BB_HE_2SS_MCS0 + x)
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#define BB_HE_3SS_MCS(x) (BB_HE_3SS_MCS0 + x)
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#define BB_HE_4SS_MCS(x) (BB_HE_4SS_MCS0 + x)
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#define BB_HE_5SS_MCS(x) (BB_HE_5SS_MCS0 + x)
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#define BB_HE_6SS_MCS(x) (BB_HE_6SS_MCS0 + x)
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#define BB_HE_7SS_MCS(x) (BB_HE_7SS_MCS0 + x)
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#define BB_HE_8SS_MCS(x) (BB_HE_8SS_MCS0 + x)
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#define BB_EHT_1SS_MCS(x) (BE_BB_EHT_1SS_MCS0 + x)
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#define BB_EHT_2SS_MCS(x) (BE_BB_EHT_2SS_MCS0 + x)
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#define BB_EHT_3SS_MCS(x) (BE_BB_EHT_3SS_MCS0 + x)
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#define BB_EHT_4SS_MCS(x) (BE_BB_EHT_4SS_MCS0 + x)
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#define BB_EHT_5SS_MCS(x) (BE_BB_EHT_5SS_MCS0 + x)
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#define BB_EHT_6SS_MCS(x) (BE_BB_EHT_6SS_MCS0 + x)
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#define BB_EHT_7SS_MCS(x) (BE_BB_EHT_7SS_MCS0 + x)
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#define BB_EHT_8SS_MCS(x) (BE_BB_EHT_8SS_MCS0 + x)
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/*For RTK AX ICs*/
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#define BB_HT_MCS(x) (BB_HT_MCS0 + x)
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#define BB_VHT_MCS(SS, x) (BB_VHT_1SS_MCS0 + ((SS - 1) * 16 ) + x)
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#define BB_HE_MCS(SS, x) (BB_HE_1SS_MCS0 + ((SS - 1) * 16 ) + x)
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/*For RTK > BE ICs*/
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#define BB_BE_HT_MCS(x) (BE_BB_HT_MCS0 + x)
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#define BB_BE_VHT_MCS(SS, x) (BE_BB_VHT_1SS_MCS0 + ((SS - 1) << 5) + x)
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#define BB_BE_HE_MCS(SS, x) (BE_BB_HE_1SS_MCS0 + ((SS - 1) << 5) + x)
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#define BB_BE_EHT_MCS(SS, x) (BE_BB_EHT_1SS_MCS0 + ((SS - 1) << 5) + x)
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/*[Rate Number]*/
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#define HT_NUM_MCS 8
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#define HE_VHT_NUM_MCS 12
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#define EHT_NUM_MCS 16
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#define LEGACY_RATE_NUM 12
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#define HT_RATE_NUM_4SS (HT_NUM_MCS * 4)
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#define VHT_RATE_NUM_4SS (HE_VHT_NUM_MCS * 4)
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#define HE_RATE_NUM_4SS (HE_VHT_NUM_MCS * 4)
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#define EHT_RATE_NUM_4SS (EHT_NUM_MCS * 4)
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#define HT_RATE_NUM_3SS (HT_NUM_MCS * 3)
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#define VHT_RATE_NUM_3SS (HE_VHT_NUM_MCS * 3)
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#define HE_RATE_NUM_3SS (HE_VHT_NUM_MCS * 3)
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#define EHT_RATE_NUM_3SS (EHT_NUM_MCS * 3)
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#define HT_RATE_NUM_2SS (HT_NUM_MCS * 2)
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#define VHT_RATE_NUM_2SS (HE_VHT_NUM_MCS * 2)
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#define HE_RATE_NUM_2SS (HE_VHT_NUM_MCS * 2)
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#define EHT_RATE_NUM_2SS (EHT_NUM_MCS * 2)
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#define HT_RATE_NUM_1SS HT_NUM_MCS
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#define VHT_RATE_NUM_1SS HE_VHT_NUM_MCS
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#define HE_RATE_NUM_1SS HE_VHT_NUM_MCS
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#define EHT_RATE_NUM_1SS EHT_NUM_MCS
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#if (defined(HALBB_COMPILE_ABOVE_4SS))
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#define HT_RATE_NUM HT_RATE_NUM_4SS
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#define VHT_RATE_NUM VHT_RATE_NUM_4SS
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#define HE_RATE_NUM HE_RATE_NUM_4SS
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#define EHT_RATE_NUM EHT_RATE_NUM_4SS
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#elif (defined(HALBB_COMPILE_ABOVE_3SS))
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#define HT_RATE_NUM HT_RATE_NUM_3SS
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#define VHT_RATE_NUM VHT_RATE_NUM_3SS
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#define HE_RATE_NUM HE_RATE_NUM_3SS
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#define EHT_RATE_NUM EHT_RATE_NUM_3SS
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#elif (defined(HALBB_COMPILE_ABOVE_2SS))
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#define HT_RATE_NUM HT_RATE_NUM_2SS
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#define VHT_RATE_NUM VHT_RATE_NUM_2SS
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#define HE_RATE_NUM HE_RATE_NUM_2SS
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#define EHT_RATE_NUM EHT_RATE_NUM_2SS
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#else
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#define HT_RATE_NUM HT_RATE_NUM_1SS
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#define VHT_RATE_NUM VHT_RATE_NUM_1SS
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#define HE_RATE_NUM HE_RATE_NUM_1SS
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#define EHT_RATE_NUM EHT_RATE_NUM_1SS
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#endif
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#ifdef HALBB_COMPILE_BE_SERIES
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#define LOW_BW_RATE_NUM EHT_RATE_NUM
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#else
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#define LOW_BW_RATE_NUM HE_RATE_NUM
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#endif
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/*@==========================================================================*/
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/****************************************************************
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* 1 ============================================================
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* 1 enumeration
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* 1 ============================================================
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***************************************************************/
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enum bb_qam_type {
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BB_QAM_CCK = 0,
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BB_QAM_BPSK = 1,
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BB_QAM_QPSK = 2,
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BB_QAM_16QAM = 3,
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BB_QAM_64QAM = 4,
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BB_QAM_256QAM = 5,
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BB_QAM_1024QAM = 6
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};
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enum bb_mode_type {
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BB_LEGACY_MODE = 0,
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BB_HT_MODE = 1,
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BB_VHT_MODE = 2,
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BB_HE_MODE = 3,
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BB_EHT_MODE = 4
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};
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/* BB_CMNINFO_CART_VER */
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enum halbb_cart_ver {
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BB_CART_A = 0,
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BB_CART_B = 1,
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BB_CART_C = 2,
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BB_CART_D = 3,
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BB_CART_E = 4,
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BB_CART_F = 5,
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BB_CART_G = 6,
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BB_CART_H = 7,
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BB_CART_I = 8,
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BB_CART_J = 9,
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BB_CART_K = 10,
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BB_CART_L = 11,
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BB_CART_M = 12,
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BB_CART_N = 13,
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BB_CART_O = 14,
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BB_CART_TEST = 15,
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};
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enum bb_path {
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BB_PATH_NON = 0,
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BB_PATH_A = 0x00000001,
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BB_PATH_B = 0x00000002,
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BB_PATH_C = 0x00000004,
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BB_PATH_D = 0x00000008,
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BB_PATH_E = 0x00000010,
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BB_PATH_AB = (BB_PATH_A | BB_PATH_B),
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BB_PATH_AC = (BB_PATH_A | BB_PATH_C),
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BB_PATH_AD = (BB_PATH_A | BB_PATH_D),
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BB_PATH_AE = (BB_PATH_A | BB_PATH_E),
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BB_PATH_BC = (BB_PATH_B | BB_PATH_C),
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BB_PATH_BD = (BB_PATH_B | BB_PATH_D),
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BB_PATH_BE = (BB_PATH_B | BB_PATH_E),
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BB_PATH_CD = (BB_PATH_C | BB_PATH_D),
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BB_PATH_CE = (BB_PATH_C | BB_PATH_E),
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BB_PATH_DE = (BB_PATH_D | BB_PATH_E),
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BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C),
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BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D),
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BB_PATH_ABE = (BB_PATH_A | BB_PATH_B | BB_PATH_E),
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BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D),
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BB_PATH_ACE = (BB_PATH_A | BB_PATH_C | BB_PATH_E),
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BB_PATH_ADE = (BB_PATH_A | BB_PATH_D | BB_PATH_E),
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BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D),
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BB_PATH_BCE = (BB_PATH_B | BB_PATH_C | BB_PATH_E),
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BB_PATH_BDE = (BB_PATH_B | BB_PATH_D | BB_PATH_E),
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BB_PATH_CDE = (BB_PATH_C | BB_PATH_D | BB_PATH_E),
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BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D),
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BB_PATH_ABCE = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_E),
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BB_PATH_ABDE = (BB_PATH_A | BB_PATH_B | BB_PATH_D | BB_PATH_E),
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BB_PATH_ACDE = (BB_PATH_A | BB_PATH_C | BB_PATH_D | BB_PATH_E),
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BB_PATH_BCDE = (BB_PATH_B | BB_PATH_C | BB_PATH_D | BB_PATH_E),
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BB_PATH_ABCDE = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D | BB_PATH_E),
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BB_PATH_AUTO = 0xff /*for auto path selection*/
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};
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enum rf_syn {
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RF_SYN0 = 0,
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RF_SYN1 = 1,
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};
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#define CVRT_PATH_NUM 13
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static const u8 bb_path_cvrt_t[CVRT_PATH_NUM][2] = {
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{RF_PATH_A, BB_PATH_A},
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{RF_PATH_B, BB_PATH_B},
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{RF_PATH_C, BB_PATH_C},
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{RF_PATH_D, BB_PATH_D},
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{RF_PATH_AB, BB_PATH_AB},
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{RF_PATH_AC, BB_PATH_AC},
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{RF_PATH_AD, BB_PATH_AD},
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{RF_PATH_BC, BB_PATH_BC},
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{RF_PATH_BD, BB_PATH_BD},
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{RF_PATH_ABC, BB_PATH_ABC},
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{RF_PATH_ACD, BB_PATH_ACD},
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{RF_PATH_BCD, BB_PATH_BCD},
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{RF_PATH_ABCD, BB_PATH_ABCD}
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};
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#endif
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