/******************************************************************************
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*
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* Copyright(c) 2007 - 2020 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __HALBB_FEATURES_H__
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#define __HALBB_FEATURES_H__
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#include "../../hal_headers_le.h"
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#include "halbb_cfg_ic.h"
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#include "halbb_ic_hw_info.h"
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/*[Control by Outer Driver]--------------------------------------------------*/
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#ifndef DRV_BB_TIMER_SUPPORT_DISABLE
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#define HALBB_TIMER_SUPPORT
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#endif
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#ifndef DRV_BB_DBG_TRACE_DISABLE
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#define HALBB_DBG_TRACE_SUPPORT
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#endif
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#ifndef DRV_BB_PHYSTS_PARSING_DISABLE
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#define HALBB_PHYSTS_PARSING_SUPPORT
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#endif
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#ifndef DRV_BB_ENV_MNTR_DISABLE
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#define HALBB_ENV_MNTR_SUPPORT
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#define CLM_SUPPORT
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#define NHM_SUPPORT
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#define IFS_CLM_SUPPORT
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#define FAHM_SUPPORT
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#define EDCCA_CLM_SUPPORT
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#endif
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#ifndef DRV_BB_STATISTICS_DISABLE
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#define HALBB_STATISTICS_SUPPORT
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#endif
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#ifndef DRV_BB_RA_DISABLE
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#define HALBB_RA_SUPPORT
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#endif
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#ifndef DRV_BB_ADPTVTY_DISABLE
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#define HALBB_EDCCA_SUPPORT
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#endif
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#ifndef DRV_BB_DFS_DISABLE
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#define HALBB_DFS_SUPPORT
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#endif
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#ifndef DRV_BB_CFO_TRK_DISABLE
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#define HALBB_CFO_TRK_SUPPORT
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#define HALBB_CFO_DAMPING_CHK
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//#define BB_DYN_CFO_TRK_LOP
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#endif
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#ifndef DRV_BB_DIG_DISABLE
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#define HALBB_DIG_SUPPORT
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#ifndef DRV_BB_TDMADIG_DISABLE
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#if (HLABB_CODE_BASE_NUM >= 34) || (HLABB_CODE_BASE_NUM == 29) || (HLABB_CODE_BASE_NUM == 27) || (HLABB_CODE_BASE_NUM == 25)
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#define HALBB_DIG_TDMA_SUPPORT
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#endif
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#endif
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#ifndef DRV_BB_DIG_MCC_DISABLE
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#define HALBB_DIG_MCC_SUPPORT
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#define HALBB_DIG_MCC_SUPPORT_IC (BB_RTL8852A | BB_RTL8852B | BB_RTL8851B)
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#endif
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#define HALBB_DIG_DAMPING_CHK
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#endif
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#ifndef DRV_BB_LA_MODE_DISABLE
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#define HALBB_LA_MODE_SUPPORT
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#ifdef BB_1115_SUPPORT
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#define HALBB_LA_320M_PATCH /*for RTL1115 320M 3-phase case only*/
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#endif
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#define BB_IC_LA_MODE_GEN2 (BB_IC_BE_1 | BB_IC_BE_2)
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#if (defined(HALBB_COMPILE_BE1_SERIES)||defined(HALBB_COMPILE_BE2_SERIES))
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#define HALBB_COMPILE_LA_MODE_GEN2
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#endif
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#endif
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#ifndef DRV_BB_PSD_DISABLE
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#define HALBB_PSD_SUPPORT
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#endif
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#ifndef DRV_BB_PWR_CTRL_DISABLE
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#define HALBB_PWR_CTRL_SUPPORT
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#endif
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#ifndef DRV_BB_WRAP_DISABLE
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#ifdef HALBB_COMPILE_BE_SERIES
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#define HALBB_BB_WRAP_SUPPORT
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#endif
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#endif
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#ifndef DRV_BB_SR_DISABLE
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#if (HLABB_CODE_BASE_NUM == 29)
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#define HALBB_SR_SUPPORT
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#endif
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#endif
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#ifndef DRV_BB_RUA_DISABLE
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#define HALBB_RUA_SUPPORT
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#endif
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#ifndef DRV_BB_PMAC_TX_DISABLE
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#define HALBB_PMAC_TX_SUPPORT
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#endif
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#ifndef DRV_BB_CH_INFO_DISABLE
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#define HALBB_CH_INFO_SUPPORT
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#ifndef DRV_BB_DYN_CSI_RSP_DISABLE
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#define HALBB_DYN_CSI_RSP_SUPPORT
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#endif
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#endif
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#ifndef DRV_BB_AUTO_DBG_DISABLE
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#define HALBB_AUTO_DBG_SUPPORT
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#endif
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#ifndef DRV_BB_ANT_DIV_DISABLE
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#define HALBB_ANT_DIV_SUPPORT
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#endif
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#ifndef DRV_BB_PATH_DIV_DISABLE
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#define HALBB_PATH_DIV_SUPPORT
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#endif
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#ifndef DRV_BB_DYN_L2H_DISABLE
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#define HALBB_DYN_L2H_SUPPORT
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#endif
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#ifndef DRV_BB_PMAC_TX_SETTING_DISABLE
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#define HALBB_PMAC_TX_SETTING_SUPPORT
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#endif
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/*[FW OFFLOAD]*/
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#if ((defined(CONFIG_PHL_IO_OFLD) ||defined(CONFIG_FW_DBCC_OFLD_SUPPORT)) && defined(HALBB_COMPILE_IC_FWOFLD))
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#define HALBB_FW_OFLD_SUPPORT
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#if (defined(CONFIG_PHL_IO_OFLD))
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#define HALBB_FW_NORMAL_OFLD_SUPPORT
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#endif
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#if (defined(CONFIG_FW_DBCC_OFLD_SUPPORT))
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#define HALBB_FW_DBCC_OFLD_SUPPORT
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#endif
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#endif
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/*[DBCC]*/
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#if (defined(CONFIG_DBCC_SUPPORT) && defined(HALBB_COMPILE_IC_DBCC))
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#define HALBB_DBCC_SUPPORT
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#define HALBB_DBCC_DVLP_FLAG
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#endif
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#define HALBB_TDMA_CR_SUPPORT
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/*[POP resolved hang]*/
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#ifdef DRV_RESOLVED_POP_BY_BB
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#define HALBB_RESOLVED_POP_BY_BB
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#endif
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#ifndef DRV_BB_ULOFDMA_CTRL_DISABLE
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#define HALBB_UL_TB_CTRL_SUPPORT
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#endif
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/*[Shared crystal]*/
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#ifdef DRV_BB_CFO_TRK_DISABLE_BY_SHARE_XTAL
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#define HALBB_SHARE_XSTAL_SUPPORT
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#endif
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#define HALBB_DYN_1R_CCA_SUPPORT
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#if 1//(defined(DRV_BB_CNSL_CMN_INFO) || !defined(HALBB_DBG_TRACE_SUPPORT))
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#define HALBB_CNSL_CMN_INFO_SUPPORT
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#endif
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#ifndef DRV_BB_SNIF_SUPPORT
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#define HALBB_SNIF_SUPPORT
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#endif
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/*[DTR]*/
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#ifndef DRV_BB_DYN_DTR_DISABLE
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#define HALBB_DYN_DTR_SUPPORT
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//#define BB_DYN_DTR
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#endif
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#ifdef DRV_BB_DCRA_EN
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#define HALBB_DCRA_EN
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#endif
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#ifdef DRV_BB_INIT_FW_NHM_EN
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#define HALBB_INIT_FW_NHM_EN
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#endif
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#ifdef CONFIG_24G_256QAM
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#define HALBB_CONFIG_HT2VHT_SUPPORT
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#endif
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#endif
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