/******************************************************************************
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*
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* Copyright(c) 2007 - 2020 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __HALBB_H__
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#define __HALBB_H__
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/*@--------------------------[Define] ---------------------------------------*/
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#define ACTIVE_TP_THRESHOLD 1
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#define BB_WATCH_DOG_PERIOD 2 /*sec*/
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#define is_sta_active(sta) ((sta) && (sta->active))
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#define HALBB_SNPRINT_SIZE 200
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#define HALBB_SNPRINT_SIZE_S 20
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#define BB_EFUSE_BAND_NUM 5
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#define IC_LNA_NUM 7
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#define IC_TIA_NUM 2
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#define IC_LNA_OP1DB_NUM 7
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#define IC_TIA_LNA_OP1DB_NUM 8
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#define EFUSE_OFST_NUM 1
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#define WB_GIDX_ELNA_NUM 16
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#define GS_IDX_NUM 2
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#define G_ELNA_NUM 2
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/*@--------------------------[Enum]------------------------------------------*/
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enum bb_trx_state_t {
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BB_TX_STATE = 0,
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BB_RX_STATE = 1,
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BB_BI_DIR_STATE = 2
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};
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enum bb_trafic_t {
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TRAFFIC_NO_TP = 0,
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TRAFFIC_ULTRA_LOW = 1,
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TRAFFIC_LOW = 2,
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TRAFFIC_MID = 3,
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TRAFFIC_HIGH = 4
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};
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enum efuse_bit_mask {
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LOW_MASK = 0,
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HIGH_MASK = 1
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};
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/*@--------------------------[Structure]-------------------------------------*/
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struct halbb_pause_lv {
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s8 lv_fa_cnt;
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s8 lv_dig;
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s8 lv_cfo;
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s8 lv_edcca;
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s8 lv_path_div;
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s8 lv_ant_div;
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};
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struct bb_func_hooker_info {
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void (*pause_bb_dm_handler)(struct bb_info *bb, u32 *val_buf, u8 val_len);
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};
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struct bb_iot_info {
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u8 is_linked_cmw500:1;
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u8 patch_id_00000000:1;
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u8 rsvd:6;
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};
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struct bb_path_info {
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/*[Path info]*/
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u8 tx_path_en; /*TX path enable*/
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u8 rx_path_en; /*RX path enable*/
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#ifdef HALBB_COMPILE_ABOVE_4SS
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enum bb_path tx_4ss_path_map; /*@Use N-X for 4STS rate*/
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#endif
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#ifdef HALBB_COMPILE_ABOVE_3SS
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enum bb_path tx_3ss_path_map; /*@Use N-X for 3STS rate*/
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#endif
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#ifdef HALBB_COMPILE_ABOVE_2SS
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enum bb_path tx_2ss_path_map; /*@Use N-X for 2STS rate*/
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#endif
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enum bb_path tx_1ss_path_map; /*@Use N-X for 1STS rate*/
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};
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struct bb_link_info {
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/*[Link Info]*/
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bool is_linked;
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bool is_linked_pre;
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bool first_connect;
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bool first_disconnect;
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enum bb_trx_state_t txrx_state_all;
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enum bb_bw_type bb_bw;
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/*[One Entry TP Info]*/
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bool is_one_entry_only;
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u32 one_entry_macid;
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u32 one_entry_tp;
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u32 one_entry_tp_pre;
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u16 tp_active_th;
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bool one_entry_tp_active_occur;
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bool is_match_bssid;
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/*[Client Number]*/
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u8 num_linked_client;
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u8 num_linked_client_pre;
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u8 num_active_client;
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u8 num_active_client_pre;
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/*[TP & Traffic]*/
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u8 traffic_load;
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u8 traffic_load_pre;
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u16 tx_rate;
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u16 rx_rate_plurality;
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u16 rx_rate_plurality_mu;
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u16 rx_utility;
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u16 avg_phy_rate;
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u32 tx_tp; /*@Mbps*/
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u32 rx_tp; /*@Mbps*/
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u32 total_tp; /*@Mbps*/
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u16 consecutive_idle_time; /*@unit: second*/
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u16 wlan_mode_bitmap; /*enum wlan_mode*/
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/*[at least one macid BFer & BFee chk]*/
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bool at_least_one_bfer; /*at least one macid Tx BFer*/
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bool at_least_one_bfee; /*at least one macid Rx BFee*/
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};
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struct bb_ch_info {
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u8 fc_ch_idx;
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bool is_2g;
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u8 rssi_min; /*U(8.1), external rssi (from antenna)*/
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u16 rssi_min_macid;
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u8 pre_rssi_min;
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u8 rssi_max; /*U(8.1), external rssi (from antenna)*/
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u16 rssi_max_macid;
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u8 rxsc_160;
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u8 rxsc_80;
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u8 rxsc_40;
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u8 rxsc_20;
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u8 rxsc_l;
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u8 is_noisy;
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u8 rf_central_ch_cfg; /*report in phy-sts*/
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s8 ext_loss[HALBB_MAX_PATH]; /*S(8.2), update when switching ch*/
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s8 ext_loss_avg; /*S(8.2), update when switching ch*/
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u8 int_rssi_min; /*U(8.1), internal rssi (from ADC output) = external rssi - ext_loss*/
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u8 int_rssi_max; /*U(8.1), internal rssi (from ADC output) = external rssi - ext_loss*/
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};
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struct bb_cmn_backup_info {
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u8 cur_tx_path;
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u8 cur_rx_path;
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s16 cur_tx_pwr;
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u8 cur_pd_lower_bound;
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u8 last_rpl;
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u32 last_rssi;
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u16 last_cfo;
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s32 cck_ps_th_bk;
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s32 cck_rssi_ofst_bk;
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s32 cck_sbd_th_bk;
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u32 cur_rfmode_a_12ac;
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u32 cur_rfmode_a_12b0;
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u32 cur_rfmode_b_32ac;
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u32 cur_rfmode_b_32b0;
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struct rssi_physts last_rssi_rpt;
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struct rxevm_physts last_rxevm_rpt;
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};
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struct bb_gain_info {
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s8 lna_gain[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][IC_LNA_NUM];
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s8 tia_gain[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][IC_TIA_NUM];
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s8 lna_gain_bypass[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][IC_LNA_NUM];
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s8 lna_op1db[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][IC_LNA_NUM];
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s8 tia_lna_op1db[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][IC_LNA_NUM + 1]; // TIA0_LNA0~6 + TIA1_LNA6
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s8 efuse_ofst[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][EFUSE_OFST_NUM];
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s8 rpl_ofst_20[BB_GAIN_BAND_NUM][HALBB_MAX_PATH];
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s8 rpl_ofst_40[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][BB_RXSC_NUM_40];
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s8 rpl_ofst_80[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][BB_RXSC_NUM_80];
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s8 rpl_ofst_160[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][BB_RXSC_NUM_160];
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u32 wb_gidx_elna[BB_GAIN_BAND_NUM][HALBB_MAX_PATH]; // {bit(15) ~ bit(0)}: {wb_gidx_15_elna ~ wb_gidx_0_elna}
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u8 wb_gidx_lna_tia[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][WB_GIDX_ELNA_NUM];
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u32 gs_idx[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][GS_IDX_NUM];
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u8 g_elna[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][G_ELNA_NUM];
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};
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struct bb_efuse_info{
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bool normal_efuse_check;
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bool hidden_efuse_check;
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s8 gain_offset[HALBB_MAX_PATH][BB_BAND_NUM_MAX + 1]; // S(8,0)
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s8 gain_cs[HALBB_MAX_PATH][BB_BAND_NUM_MAX]; // S(8,0)
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s8 gain_cg[HALBB_MAX_PATH][BB_BAND_NUM_MAX]; // S(8,0)
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s8 hidden_efuse[BB_HIDE_EFUSE_SIZE];
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s8 lna_err_2g[HALBB_MAX_PATH][7]; // S(6,2)
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s8 lna_err_5g[HALBB_MAX_PATH][7]; // S(6,2)
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s8 frontend_loss[HALBB_MAX_PATH];
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s8 rpl_bias_comp[HALBB_MAX_PATH];
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s8 rssi_bias_comp[HALBB_MAX_PATH];
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s8 efuse_ofst[HW_PHY_MAX]; // 8852A:S(5,2) 8852B:S(8,4)
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s8 efuse_ofst_path[HALBB_MAX_PATH]; // 8852C: S(8,4)
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s8 efuse_ofst_tb[HW_PHY_MAX]; // 8852A:S(7,4) 8852B:S(8,4)
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s8 efuse_ofst_tb_path[HALBB_MAX_PATH]; // 8852C: S(8,4)
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s8 rpl_ofst_cck; // 8852D: S(8,0)
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u8 efuse_ft; // 8192XB: U(8,0)
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u8 efuse_adc_td; // 8192XB: U(2,0)
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};
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struct vht_mu_cr_backup_table {
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u32 muic_en_a;
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u32 lpbw_sw_symb0_a;
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u32 ch_tracking_symb0_a;
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u32 lpbw_sel_d1_a;
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u32 ch_tracking_symb1_a;
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u32 ch_tracking_a1_a;
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u32 lpbw_sel_p1_a;
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u32 noise_tracking_en_a;
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};
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struct bb_cmn_dbg_info {
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bool cmn_log_2_cnsl_en;
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bool cmn_log_2_drv_statistic_en;
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};
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struct bb_cmn_info {
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u8 bb_dm_number;
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bool cck_blk_en;
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enum phl_phy_idx cck_phy_map;
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bool bb_dbcc_en;
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bool ic_dual_phy_support;
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bool ic_dbcc_support;
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enum halbb_drv_type bb_drv_type;
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#ifdef HALBB_COMPILE_IC_DBCC_MLO
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enum mlo_dbcc_mode_type bb_mlo_dbcc_mode_t;
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#endif
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#ifdef HALBB_RA_SUPPORT
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struct bb_ra_info bb_ra_i[PHL_MAX_STA_NUM];
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struct bb_ra_drv_info bb_ra_drv_i;
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#endif
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#ifdef HALBB_PSD_SUPPORT
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struct bb_psd_info bb_psd_i;
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#endif
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#ifdef HALBB_LA_MODE_SUPPORT
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struct bb_la_mode_info bb_la_mode_i;
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#endif
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#ifdef HALBB_SNIF_SUPPORT
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struct bb_snif_info bb_snif_i;
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#endif
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#ifdef HALBB_DYN_CSI_RSP_SUPPORT
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struct bf_ch_raw_info bf_ch_raw_i;
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#endif
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struct bb_spur_info bb_spur_i;
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struct bb_echo_cmd_info bb_echo_cmd_i;
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struct bb_func_hooker_info bb_func_hooker_i;
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struct bb_cmn_dbg_info bb_cmn_dbg_i;
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#ifdef HALBB_FW_OFLD_SUPPORT
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u8 bbcr_fwofld_state;
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bool skip_io_init_en;
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bool is_io_ofld_success;
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#endif
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bool bb_fwofld_in_progress;
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u32 bb_fwofld_sup_bitmap; /*enum fw_ofld_type.For HALBB to control DBCC-OFLD manully*/
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u32 bb_fwofld_start_time;
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};
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#ifdef HALBB_DIG_MCC_SUPPORT
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#define PD_IDX_MIN 0
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#define NUM_MAX_IGI_CNT 7
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#define INVALID_INIT_VAL 0xff
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/*For 2G/5G/6G*/
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enum mcc_band {
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MCC_BAND_1 = 0,
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MCC_BAND_2,
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MCC_BAND_NUM
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};
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struct halbb_mcc_dm {
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bool mcc_pre_status_en;
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u8 mcc_reg_id[NUM_MAX_IGI_CNT];
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u8 sta_cnt[MCC_BAND_NUM];
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u16 mcc_dm_reg[NUM_MAX_IGI_CNT];
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u16 mcc_dm_mask[NUM_MAX_IGI_CNT];
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u16 mcc_dm_val[NUM_MAX_IGI_CNT][MCC_BAND_NUM];
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/*mcc DIG*/
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u8 rssi_min[MCC_BAND_NUM];
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/* need to be config by driver*/
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bool mcc_status_en;
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u8 softap_macid;
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struct rtw_chan_def mcc_rf_ch[MCC_BAND_NUM];
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};
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/**
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* @struct _mcc_h2c_
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* @brief _mcc_h2c_
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*
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*/
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struct mcc_h2c_reg_content {
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// MCCDM
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u8 addr_lsb;
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u8 addr_msb;
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u8 bmask_lsb;
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u8 bmask_msb;
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u8 val_lsb;
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u8 val_msb;
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};
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struct mcc_h2c {
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// MCCDM
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u8 reg_cnt;
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u8 mcc_dm_en: 1;
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u8 mcc_ch_idx: 1;
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u8 mcc_set: 1;
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u8 phy0_en: 1;
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u8 phy1_en: 1;
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u8 rsvd0: 3;
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u8 ch_lsb;
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u8 ch_msb;
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struct mcc_h2c_reg_content mcc_reg_content[NUM_MAX_IGI_CNT];
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};
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#endif
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struct bb_info {
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struct rtw_phl_com_t *phl_com;
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struct rtw_hal_com_t *hal_com;
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struct rtw_phl_stainfo_t *phl_sta_info[PHL_MAX_STA_NUM];
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u16 phl2bb_macid_table[PHL_MAX_STA_NUM];
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bool sta_exist[PHL_MAX_STA_NUM];
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/*[DBCC]*/
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#ifdef HALBB_DBCC_SUPPORT
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struct bb_info *bb_phy_hooker;
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#endif
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enum phl_phy_idx bb_phy_idx;
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struct bb_cmn_info *bb_cmn_hooker;
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/*[Common Info]*/
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u32 bb0_cr_offset;
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u32 bb0_mcu_cr_offset;
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struct bb_gain_info bb_gain_i;
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struct bb_gain_gen2_info bb_gain_gen2_i;
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struct bb_efuse_info bb_efuse_i;
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enum bb_ic_t ic_type;
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enum bb_ic_sub_t ic_sub_type;
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enum bb_cr_t cr_type;
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enum bb_80211spec_t bb_80211spec;
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u8 num_rf_path;
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u16 bb_sta_cnt;
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/*[System Info]*/
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bool is_mp_mode_pre;
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enum bb_watchdog_mode_t bb_watchdog_mode;
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bool bb_cmn_info_init_ready;
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bool bb_dm_init_ready;
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u32 bb_sys_up_time;
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bool bb_watchdog_en;
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u8 bb_watchdog_period; /*2s, 4s, 8s...,254s*/
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bool bb_ic_api_en;
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u8 pre_dbg_priority;
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char dbg_buf[HALBB_SNPRINT_SIZE];
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/*[DM Info]*/
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bool is_noisy;
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bool adv_bb_dm_en;
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u64 support_ability; /*HALBB function Supportability*/
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u64 manual_support_ability;
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u32 pause_ability; /*HALBB function pause Supportability*/
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struct halbb_pause_lv pause_lv_table;
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/*[FW Info]*/
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u8 fwofld_last_cmd;
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u64 fw_dbg_component;
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/*[Drv Dbg Info]*/
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u64 dbg_component;
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u64 mcu_dbg_component;
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u8 cmn_dbg_msg_period;
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u16 cmn_dbg_msg_component;
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u8 cmn_dbg_msg_cnt;
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bool is_disable_phy_api;
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/*[Dummy]*/
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bool bool_dummy;
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u8 u8_dummy;
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u16 u16_dummy;
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u32 u32_dummy;
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/*[Link Info]*/
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enum rf_path tx_path; /*PMAC Tx Path*/
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enum rf_path rx_path;
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/*[pmac]*/
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bool dyn_pmac_tri_en;
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bool pmac_tri_en;
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bool pwr_comp_en;
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u32 pmac_tri_idx;
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u32 pmac_pwr_ofst;
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/*[btc]*/
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bool bt_en; /*bt_en=1 when is_share_ant=0 and is_2g, backup for ch_bw switch*/
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/*[Ch_Trk WR]*/
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bool pre_ch_trk_state;
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/*[npath enable]*/
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bool npath_en;
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/*@=== [HALBB Structure] ============================================*/
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struct bb_hw_cfg_info bb_hw_cfg_i;
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#ifdef BB_8852A_2_SUPPORT
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struct bb_8852a_2_info bb_8852a_2_i;
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struct bb_h2c_fw_cmw bb_fw_cmw_i;
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struct vht_mu_cr_backup_table vht_mu_backup_val;
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#endif
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#ifdef HALBB_DBCC_SUPPORT
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struct bb_dbcc_info bb_dbcc_i;
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#endif
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#ifdef HALBB_ENV_MNTR_SUPPORT
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struct bb_env_mntr_info bb_env_mntr_i;
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#endif
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#ifdef HALBB_EDCCA_SUPPORT
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struct bb_edcca_info bb_edcca_i;
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#endif
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#ifdef HALBB_DFS_SUPPORT
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struct bb_dfs_info bb_dfs_i;
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#endif
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#ifdef HALBB_STATISTICS_SUPPORT
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struct bb_stat_info bb_stat_i;
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#endif
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#ifdef HALBB_DIG_SUPPORT
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struct bb_dig_info bb_dig_i;
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#endif
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#ifdef HALBB_CFO_TRK_SUPPORT
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struct bb_cfo_trk_info bb_cfo_trk_i;
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#endif
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#ifdef HALBB_UL_TB_CTRL_SUPPORT
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struct bb_ul_tb_info bb_ul_tb_i;
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#endif
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#ifdef HALBB_PHYSTS_PARSING_SUPPORT
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struct bb_physts_info bb_physts_i;
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#endif
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#ifdef HALBB_LA_MODE_SUPPORT
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struct bb_la_mode_info bb_la_mode_i;
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#endif
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#ifdef HALBB_PWR_CTRL_SUPPORT
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struct bb_pwr_ctrl_info bb_pwr_ctrl_i;
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struct bb_dyncca_info bb_dyncca_i;
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#endif
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#ifdef HALBB_PMAC_TX_SUPPORT
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struct bb_plcp_info bb_plcp_i;
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#endif
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struct bb_link_info bb_link_i;
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struct bb_path_info bb_path_i;
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struct bb_ch_info bb_ch_i;
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struct bb_api_info bb_api_i;
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struct bb_iot_info bb_iot_i;
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struct bb_dbg_info bb_dbg_i;
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struct bb_c2h_fw_tx_rpt bb_fwtx_c2h_i;
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struct bb_h2c_fw_tx_setting bb_fwtx_h2c_i;
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struct bb_h2c_fw_edcca bb_fw_edcca_i;
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struct bb_h2c_ehtsig_sigb bb_h2c_ehtsig_sigb_i;
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struct bb_fw_dbg_cmn_info bb_fwdbg_i;
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struct bb_cmn_rpt_info bb_cmn_rpt_i;
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struct bb_rpt_info bb_rpt_i;
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struct rxevm_physts rxevm;
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struct bb_cmn_backup_info bb_cmn_backup_i;
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struct bb_spur_info bb_spur_i;
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#ifdef HALBB_CH_INFO_SUPPORT
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struct bb_ch_rpt_info bb_ch_rpt_i;
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#endif
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#ifdef HALBB_AUTO_DBG_SUPPORT
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struct bb_auto_dbg_info bb_auto_dbg_i;
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#endif
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#ifdef HALBB_ANT_DIV_SUPPORT
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struct bb_antdiv_info bb_ant_div_i;
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#endif
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#ifdef HALBB_DYN_L2H_SUPPORT
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struct bb_dyn_l2h_info bb_dyn_l2h_i;
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#endif
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#ifdef HALBB_PATH_DIV_SUPPORT
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struct bb_pathdiv_info bb_path_div_i;
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#endif
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#ifdef HALBB_SR_SUPPORT
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struct bb_spatial_reuse_info bb_sr_i;
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#endif
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/*@=== [HALBB Timer] ================================================*/
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#ifdef HALBB_RUA_SUPPORT
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/*struct rtw_rua_tbl rtw_rua_t;*/
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#endif
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#ifdef HALBB_DIG_MCC_SUPPORT
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struct halbb_mcc_dm mcc_dm;
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#endif
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#ifdef HALBB_DYN_1R_CCA_SUPPORT
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struct bb_dyn_1r_cca_info bb_dyn_1r_cca_i;
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#endif
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#ifdef HALBB_DYN_DTR_SUPPORT
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struct bb_dyn_dtr_info bb_dyn_dtr_i;
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#endif
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#ifdef HALBB_FW_OFLD_SUPPORT
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enum phl_msg_evt_id bb_phl_evt;
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#endif
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};
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/*@--------------------------[Prptotype]-------------------------------------*/
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u8 halbb_get_rssi_min(struct bb_info *bb);
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void halbb_cmn_info_self_reset(struct bb_info *bb);
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void halbb_sta_info_dbg(struct bb_info *bb, char input[][16], u32 *_used,
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char *output, u32 *_out_len);
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void halbb_supportability_dbg(struct bb_info *bb, char input[][16], u32 *_used,
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char *output, u32 *_out_len);
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void halbb_pause_func_dbg(struct bb_info *bb, char input[][16], u32 *_used,
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char *output, u32 *_out_len);
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void halbb_store_data(struct bb_info *bb);
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#endif
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