/******************************************************************************
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*
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* Copyright(c) 2019 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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******************************************************************************/
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#include "ser.h"
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#include "mac_priv.h"
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#define DBG_SENARIO_SH 28
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#define L0_TO_L1_EVENT_SH 28
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#define L0_TO_L1_EVENT_MSK 0xF
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enum mac_ax_l0_to_l1_event {
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MAC_AX_L0_TO_L1_CHIF_IDLE = 0,
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MAC_AX_L0_TO_L1_CMAC_DMA_IDLE = 1,
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MAC_AX_L0_TO_L1_RLS_PKID = 2,
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MAC_AX_L0_TO_L1_PTCL_IDLE = 3,
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MAC_AX_L0_TO_L1_RX_QTA_LOST = 4,
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MAC_AX_L0_TO_L1_DLE_STAT_HANG = 5,
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MAC_AX_L0_TO_L1_PCIE_STUCK = 6,
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MAC_AX_L0_TO_L1_EVENT_MAX = 15,
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};
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enum mac_ax_halt_h2c_info {
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MAC_AX_L0_DBG_MODE = 0x10,
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MAC_AX_L1_DBG_MODE = 0x17,
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MAC_AX_RST_DBG_MODE = 0xff
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};
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static void dump_err_status_dispatcher(struct mac_ax_adapter *adapter);
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static void dump_err_status_dmac(struct mac_ax_adapter *adapter);
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static void dump_err_status_cmac(struct mac_ax_adapter *adapter, u8 band);
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static void dump_cmac_cr(struct mac_ax_adapter *adapter, u8 band);
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static void dump_dmac_cr(struct mac_ax_adapter *adapter);
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u32 mac_dbg_log_dump(struct mac_ax_adapter *adapter)
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{
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struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
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struct mac_ax_dbgpkg dbg_val;
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struct mac_ax_dbgpkg_en dbg_en;
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u32 error = 0, dbg_port_dump_en = 0, val32, mem_size;
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error = (enum mac_ax_err_info)MAC_REG_R32(R_AX_HALT_C2H);
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switch (error) {
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case MAC_AX_ERR_L1_ERR_DMAC:
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case MAC_AX_ERR_L0_PROMOTE_TO_L1:
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PLTFM_MEMSET(&dbg_en, 0, sizeof(struct mac_ax_dbgpkg_en));
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if (adapter->ser_info.dbg_lvl.dmac_dbg_dump) {
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dbg_en.dmac_dbg = 1;
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dbg_port_dump_en = 1;
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}
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if (adapter->ser_info.dbg_lvl.cmac_dbg_dump) {
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dbg_en.cmac_dbg = 1;
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dbg_port_dump_en = 1;
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}
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if (adapter->ser_info.dbg_lvl.txflow_dbg_dump) {
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dbg_en.tx_flow_dbg = 1;
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dbg_port_dump_en = 1;
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}
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if (adapter->ser_info.dbg_lvl.dbgprt_dump) {
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dbg_en.mac_dbg_port = 1;
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dbg_en.dle_dbg = 1;
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dbg_port_dump_en = 1;
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}
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if (dbg_port_dump_en) {
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// for debug port log would cause fw wdt
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val32 = MAC_REG_R32(R_AX_HIMR0);
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val32 &= ~B_AX_WDT_TIMEOUT_INT_EN;
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MAC_REG_W32(R_AX_HIMR0, val32);
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mac_dbg_status_dump(adapter, &dbg_val, &dbg_en);
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val32 = MAC_REG_R32(R_AX_HIMR0);
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val32 |= B_AX_WDT_TIMEOUT_INT_EN;
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MAC_REG_W32(R_AX_HIMR0, val32);
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}
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if (adapter->ser_info.dbg_lvl.share_mem_dump) {
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mem_size = mac_get_mem_size(adapter, MAC_AX_MEM_SHARED_BUF);
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val32 = MAC_REG_R32(R_AX_HIMR0);
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val32 &= ~B_AX_WDT_TIMEOUT_INT_EN;
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MAC_REG_W32(R_AX_HIMR0, val32);
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mac_mem_dump(adapter, MAC_AX_MEM_SHARED_BUF, 0x0, NULL, mem_size, 0);
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val32 = MAC_REG_R32(R_AX_HIMR0);
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val32 |= B_AX_WDT_TIMEOUT_INT_EN;
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MAC_REG_W32(R_AX_HIMR0, val32);
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}
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if (adapter->ser_info.dbg_lvl.mac_reg_dump)
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mac_reg_dump(adapter, MAC_AX_REG_MAC);
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break;
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case MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE:
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break;
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case MAC_AX_ERR_L1_RESET_RECOVERY_DONE:
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break;
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default:
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break;
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}
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return MACSUCCESS;
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}
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u32 mac_dbg_log_lvl_adjust(struct mac_ax_adapter *adapter, struct mac_debug_log_lvl *lvl)
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{
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adapter->ser_info.dbg_lvl.dbgprt_dump = lvl->dbgprt_dump;
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adapter->ser_info.dbg_lvl.share_mem_dump = lvl->share_mem_dump;
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adapter->ser_info.dbg_lvl.cmac_dbg_dump = lvl->cmac_dbg_dump;
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adapter->ser_info.dbg_lvl.dmac_dbg_dump = lvl->dmac_dbg_dump;
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adapter->ser_info.dbg_lvl.txflow_dbg_dump = lvl->txflow_dbg_dump;
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adapter->ser_info.dbg_lvl.mac_reg_dump = lvl->mac_reg_dump;
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return MACSUCCESS;
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}
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u32 mac_trigger_cmac_err(struct mac_ax_adapter *adapter)
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{
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struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
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u8 val8;
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u16 val16;
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u32 ret;
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ret = check_mac_en(adapter, MAC_AX_BAND_0, MAC_AX_CMAC_SEL);
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if (ret != MACSUCCESS)
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return ret;
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val8 = MAC_REG_R8(R_AX_CMAC_FUNC_EN);
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MAC_REG_W8(R_AX_CMAC_FUNC_EN, val8 & (~B_AX_TMAC_EN));
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PLTFM_DELAY_MS(1);
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MAC_REG_W8(R_AX_CMAC_FUNC_EN, val8);
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val16 = MAC_REG_R16(R_AX_PTCL_IMR0) | B_AX_F2PCMD_EMPTY_ERR_INT_EN;
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MAC_REG_W16(R_AX_PTCL_IMR0, val16);
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MAC_REG_W16(R_AX_PTCL_IMR0, val16 & ~B_AX_F2PCMD_EMPTY_ERR_INT_EN);
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return MACSUCCESS;
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}
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u32 mac_trigger_cmac1_err(struct mac_ax_adapter *adapter)
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{
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struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
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u8 val8;
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u16 val16;
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u32 ret;
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ret = check_mac_en(adapter, MAC_AX_BAND_1, MAC_AX_CMAC_SEL);
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if (ret != MACSUCCESS)
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return ret;
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val8 = MAC_REG_R8(R_AX_CMAC_FUNC_EN_C1);
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MAC_REG_W8(R_AX_CMAC_FUNC_EN_C1, val8 & (~B_AX_TMAC_EN));
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PLTFM_DELAY_MS(1);
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MAC_REG_W8(R_AX_CMAC_FUNC_EN_C1, val8);
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val16 = MAC_REG_R16(R_AX_PTCL_IMR0_C1) | B_AX_F2PCMD_EMPTY_ERR_INT_EN;
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MAC_REG_W16(R_AX_PTCL_IMR0_C1, val16);
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MAC_REG_W16(R_AX_PTCL_IMR0_C1, val16 & ~B_AX_F2PCMD_EMPTY_ERR_INT_EN);
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return MACSUCCESS;
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}
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u32 mac_trigger_dmac_err(struct mac_ax_adapter *adapter)
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{
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struct cpuio_buf_req_t buf_req;
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struct cpuio_ctrl_t ctrl_para;
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u32 ret;
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// Use CPUIO to enqueue packet.
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//WD
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buf_req.len = 0x20;
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ret = mac_dle_buf_req_wd(adapter, &buf_req);
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if (ret != MACSUCCESS) {
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PLTFM_MSG_ERR("[ERR]WDE DLE buf req\n");
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return ret;
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}
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// Enqueue two pkt_id, but only has one pkt_id.
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PLTFM_MEMSET((void *)&ctrl_para, 0, sizeof(ctrl_para));
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ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD;
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ctrl_para.start_pktid = buf_req.pktid;
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ctrl_para.end_pktid = buf_req.pktid;
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ctrl_para.pkt_num = 1;
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ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS;
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ctrl_para.dst_qid = 4;
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ret = mac_set_cpuio_wd(adapter, &ctrl_para);
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if (ret != MACSUCCESS) {
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PLTFM_MSG_ERR("[ERR]WDE DLE enqueue to head\n");
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return ret;
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}
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return MACSUCCESS;
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}
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u32 mac_dump_qta_lost(struct mac_ax_adapter *adapter)
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{
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struct dle_dfi_qempty_t qempty;
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struct dle_dfi_quota_t quota;
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struct dle_dfi_ctrl_t ctrl;
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struct mac_ax_priv_ops *p_ops = adapter_to_priv_ops(adapter);
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struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
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u32 ret, val, not_empty, i;
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qempty.dle_type = DLE_CTRL_TYPE_PLE;
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qempty.grpsel = 0;
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ret = dle_dfi_qempty(adapter, &qempty);
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if (ret == MACSUCCESS)
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PLTFM_MSG_ALWAYS("DLE group0 empty: 0x%x\n", qempty.qempty);
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else
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PLTFM_MSG_ERR("%s: query DLE fail\n", __func__);
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for (not_empty = ~qempty.qempty, i = 0;
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not_empty != 0; not_empty = not_empty >> 1, i++) {
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if (!(not_empty & BIT(0)))
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continue;
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ctrl.type = DLE_CTRL_TYPE_PLE;
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ctrl.target = DLE_DFI_TYPE_QLNKTBL;
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ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ?
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QLNKTBL_ADDR_INFO_SEL : 0) |
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SET_WORD(i, QLNKTBL_ADDR_TBL_IDX);
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ret = p_ops->dle_dfi_ctrl(adapter, &ctrl);
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if (ret == MACSUCCESS)
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PLTFM_MSG_ALWAYS("qidx%d pktcnt = %d\n", i,
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GET_FIELD(ctrl.out_data,
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QLNKTBL_DATA_SEL1_PKT_CNT));
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else
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PLTFM_MSG_ERR("%s: query DLE fail\n", __func__);
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}
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/* cmac0 */
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quota.dle_type = DLE_CTRL_TYPE_PLE;
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quota.qtaid = 6;
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ret = dle_dfi_quota(adapter, "a);
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if (ret == MACSUCCESS)
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PLTFM_MSG_ALWAYS("quota6 rsv/use: 0x%x/0x%x\n",
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quota.rsv_pgnum, quota.use_pgnum);
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else
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PLTFM_MSG_ERR("%s: query DLE fail\n", __func__);
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val = MAC_REG_R32(R_AX_PLE_QTA6_CFG);
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PLTFM_MSG_ALWAYS("[PLE][CMAC0_RX]min_pgnum=0x%x\n",
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GET_FIELD(val, B_AX_PLE_Q6_MIN_SIZE));
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PLTFM_MSG_ALWAYS("[PLE][CMAC0_RX]max_pgnum=0x%x\n",
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GET_FIELD(val, B_AX_PLE_Q6_MAX_SIZE));
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val = MAC_REG_R32(R_AX_RX_FLTR_OPT);
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PLTFM_MSG_ALWAYS("[CMAC0_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n",
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GET_FIELD(val, B_AX_RX_MPDU_MAX_LEN));
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val = MAC_REG_R32(R_AX_RSP_CHK_SIG);
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PLTFM_MSG_ALWAYS("R_AX_RSP_CHK_SIG=0x%x\n",
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val);
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val = MAC_REG_R32(R_AX_TRXPTCL_RESP_0);
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PLTFM_MSG_ALWAYS("R_AX_TRXPTCL_RESP_0=0x%x\n",
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val);
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val = MAC_REG_R32(R_AX_CCA_CONTROL);
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PLTFM_MSG_ALWAYS("R_AX_CCA_CONTROL=0x%x\n",
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val);
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/* cmac1 */
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ret = check_mac_en(adapter, 1, MAC_AX_CMAC_SEL);
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if (ret == MACSUCCESS) {
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quota.dle_type = DLE_CTRL_TYPE_PLE;
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quota.qtaid = 7;
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ret = dle_dfi_quota(adapter, "a);
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if (ret == MACSUCCESS)
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PLTFM_MSG_ALWAYS("quota7 rsv/use: 0x%x/0x%x\n",
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quota.rsv_pgnum, quota.use_pgnum);
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else
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PLTFM_MSG_ERR("%s: query DLE fail\n", __func__);
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val = MAC_REG_R32(R_AX_PLE_QTA7_CFG);
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PLTFM_MSG_ALWAYS("[PLE][CMAC1_RX]min_pgnum=0x%x\n",
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GET_FIELD(val, B_AX_PLE_Q7_MIN_SIZE));
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PLTFM_MSG_ALWAYS("[PLE][CMAC1_RX]max_pgnum=0x%x\n",
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GET_FIELD(val, B_AX_PLE_Q7_MAX_SIZE));
|
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val = MAC_REG_R32(R_AX_RX_FLTR_OPT_C1);
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PLTFM_MSG_ALWAYS("[CMAC1_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n",
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GET_FIELD(val, B_AX_RX_MPDU_MAX_LEN));
|
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val = MAC_REG_R32(R_AX_RSP_CHK_SIG_C1);
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PLTFM_MSG_ALWAYS("R_AX_RSP_CHK_SIG_C1=0x%x\n",
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val);
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val = MAC_REG_R32(R_AX_TRXPTCL_RESP_0_C1);
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PLTFM_MSG_ALWAYS("R_AX_TRXPTCL_RESP_0_C1=0x%x\n",
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val);
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val = MAC_REG_R32(R_AX_CCA_CONTROL_C1);
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PLTFM_MSG_ALWAYS("R_AX_CCA_CONTROL_C1=0x%x\n",
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val);
|
}
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val = MAC_REG_R32(R_AX_DLE_EMPTY0);
|
PLTFM_MSG_ALWAYS("R_AX_DLE_EMPTY0=0x%x\n",
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val);
|
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val = MAC_REG_R32(R_AX_DLE_EMPTY1);
|
PLTFM_MSG_ALWAYS("R_AX_DLE_EMPTY1=0x%x\n",
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val);
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dump_err_status_dispatcher(adapter);
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return MACSUCCESS;
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}
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u32 mac_dump_l0_to_l1(struct mac_ax_adapter *adapter,
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enum mac_ax_err_info err)
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{
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u32 dbg, event;
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struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
|
|
PLTFM_MSG_ALWAYS("%s\n", __func__);
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dbg = MAC_REG_R32(R_AX_SER_DBG_INFO);
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event = GET_FIELD(dbg, L0_TO_L1_EVENT);
|
|
switch (event) {
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case MAC_AX_L0_TO_L1_RX_QTA_LOST:
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PLTFM_MSG_ALWAYS("quota lost!\n");
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mac_dump_qta_lost(adapter);
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break;
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default:
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break;
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}
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|
return MACSUCCESS;
|
}
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|
u32 mac_dump_err_status(struct mac_ax_adapter *adapter,
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enum mac_ax_err_info err)
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{
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struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
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struct mac_ax_dbgpkg dbg_val;
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struct mac_ax_dbgpkg_en dbg_en;
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u32 cmac_err, dmac_err;
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u8 val8;
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u32 ret, i, mem_size;
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struct mac_ax_priv_ops *p_ops = adapter_to_priv_ops(adapter);
|
|
PLTFM_MSG_ERR("--->\n err=0x%x\n", err);
|
if (err == MAC_AX_ERR_L1_ERR_DMAC ||
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err == MAC_AX_ERR_L0_PROMOTE_TO_L1 ||
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err == MAC_AX_ERR_L0_ERR_CMAC0 ||
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err == MAC_AX_ERR_L0_ERR_CMAC1 ||
|
err == HALT_C2H_L1_DBG_MODE ||
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err == MAC_AX_ERR_L0_PROMOTE_TO_L1_DBG) {
|
PLTFM_MSG_ERR("R_AX_SER_DBG_INFO =0x%08x\n",
|
MAC_REG_R32(R_AX_SER_DBG_INFO));
|
PLTFM_MSG_ERR("DBG Counter 1 (0x1C0)=0x%08x\n",
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MAC_REG_R32(0x1C0));
|
PLTFM_MSG_ERR("DBG Counter 2 (0x1C4)=0x%08x\n",
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MAC_REG_R32(0x1C4));
|
|
dump_err_status_dmac(adapter);
|
dump_err_status_cmac(adapter, MAC_AX_BAND_0);
|
dump_err_status_cmac(adapter, MAC_AX_BAND_1);
|
|
if (adapter->hw_info->intf == MAC_AX_INTF_PCIE) {
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#if MAC_AX_8852A_SUPPORT || MAC_AX_8852B_SUPPORT || MAC_AX_8851B_SUPPORT || MAC_AX_8852BT_SUPPORT
|
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
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is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) ||
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is_chip_id(adapter, MAC_AX_CHIP_ID_8851B) ||
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is_chip_id(adapter, MAC_AX_CHIP_ID_8852BT)) {
|
PLTFM_MSG_ERR("R_AX_DBG_ERR_FLAG=0x%08x\n",
|
MAC_REG_R32(R_AX_DBG_ERR_FLAG));
|
PLTFM_MSG_ERR("R_AX_LBC_WATCHDOG=0x%08x\n",
|
MAC_REG_R32(R_AX_LBC_WATCHDOG));
|
}
|
#endif
|
#if MAC_AX_8852C_SUPPORT || MAC_AX_8192XB_SUPPORT || MAC_AX_8851E_SUPPORT || MAC_AX_8852D_SUPPORT
|
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8851E) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8852D)) {
|
PLTFM_MSG_ERR("R_AX_DBG_ERR_FLAG=0x%08x\n",
|
MAC_REG_R32(R_AX_DBG_ERR_FLAG_V1));
|
PLTFM_MSG_ERR("R_AX_LBC_WATCHDOG=0x%08x\n",
|
MAC_REG_R32(R_AX_LBC_WATCHDOG_V1));
|
}
|
#endif
|
}
|
if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1 ||
|
err == MAC_AX_ERR_L0_PROMOTE_TO_L1_DBG)
|
mac_dump_l0_to_l1(adapter, err);
|
}
|
if (err == MAC_AX_ERR_L0_ERR_CMAC0 ||
|
err == MAC_AX_ERR_L0_ERR_CMAC1 ||
|
err == HALT_C2H_L1_DBG_MODE ||
|
err == MAC_AX_ERR_L0_PROMOTE_TO_L1_DBG) {
|
cmac_err = MAC_REG_R32(R_AX_CMAC_ERR_ISR);
|
dmac_err = MAC_REG_R32(R_AX_DMAC_ERR_ISR);
|
dump_dmac_cr(adapter);
|
dump_cmac_cr(adapter, MAC_AX_BAND_0);
|
dump_cmac_cr(adapter, MAC_AX_BAND_1);
|
// dump DLE TBL & STA SCH
|
PLTFM_MEMSET(&dbg_en, 0, sizeof(struct mac_ax_dbgpkg_en));
|
dbg_en.ss_dbg = 1;
|
dbg_en.dle_dbg = 1;
|
mac_dbg_status_dump(adapter, &dbg_val, &dbg_en);
|
// dump debug port
|
for (i = MAC_AX_DBG_PORT_SEL_PTCL_C0; i < MAC_AX_DBG_PORT_SEL_LAST; i++) {
|
if (p_ops->is_dbg_port_not_valid(adapter, i))
|
continue;
|
ret = dbg_port_dump(adapter, i);
|
if (ret == MACDBGPORTSEL) {
|
PLTFM_MSG_WARN("no dbg port sel %d\n", i);
|
continue;
|
} else if (ret != MACSUCCESS) {
|
PLTFM_MSG_ERR("dbg port %d dump %d\n", i, ret);
|
break;
|
}
|
}
|
|
mem_size = mac_get_mem_size(adapter, MAC_AX_MEM_SHARED_BUF);
|
mac_mem_dump(adapter, MAC_AX_MEM_SHARED_BUF, 0x0, NULL, mem_size, 0);
|
val8 = MAC_REG_R8(0x1FC) | BIT0;
|
MAC_REG_W8(0x1FC, val8);
|
}
|
PLTFM_MSG_ERR("<---\n");
|
|
return MACSUCCESS;
|
}
|
|
u32 mac_set_err_status(struct mac_ax_adapter *adapter,
|
enum mac_ax_err_info err)
|
{
|
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
|
u32 cnt = MAC_SET_ERR_DLY_CNT;
|
u32 ret = MACSUCCESS;
|
|
if (err > MAC_AX_SET_ERR_MAX) {
|
PLTFM_MSG_ERR("Bad set-err-status value\n");
|
return MACFUNCINPUT;
|
}
|
|
PLTFM_MUTEX_LOCK(&adapter->hw_info->err_set_lock);
|
|
while (--cnt) {
|
if (!MAC_REG_R32(R_AX_HALT_H2C_CTRL))
|
break;
|
PLTFM_DELAY_US(MAC_SET_ERR_DLY_US);
|
}
|
if (!cnt) {
|
PLTFM_MSG_ERR("FW does not receive previous msg\n");
|
ret = MACPOLLTO;
|
goto end;
|
}
|
|
if (err == MAC_AX_ERR_L1_DISABLE_EN)
|
adapter->sm.fw_rst = MAC_AX_FW_RESET_RECV_DONE;
|
|
MAC_REG_W32(R_AX_HALT_H2C, err);
|
MAC_REG_W32(R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER);
|
|
end:
|
PLTFM_MUTEX_UNLOCK(&adapter->hw_info->err_set_lock);
|
return ret;
|
}
|
|
u32 mac_get_err_status(struct mac_ax_adapter *adapter,
|
enum mac_ax_err_info *err)
|
{
|
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
|
u32 cnt = MAC_SET_ERR_DLY_CNT;
|
u32 ret = MACSUCCESS;
|
u32 error_scenario = 0;
|
|
PLTFM_MUTEX_LOCK(&adapter->hw_info->err_get_lock);
|
adapter->sm.l2_st = MAC_AX_L2_DIS;
|
|
while (--cnt) {
|
if (MAC_REG_R32(R_AX_HALT_C2H_CTRL))
|
break;
|
PLTFM_DELAY_US(MAC_SET_ERR_DLY_US);
|
}
|
if (!cnt) {
|
PLTFM_MSG_ERR("Polling FW err status fail\n");
|
ret = MACPOLLTO;
|
goto end;
|
}
|
|
*err = (enum mac_ax_err_info)MAC_REG_R32(R_AX_HALT_C2H);
|
MAC_REG_W32(R_AX_HALT_C2H_CTRL, 0);
|
switch (*err) {
|
case MAC_AX_ERR_L1_ERR_DMAC:
|
case MAC_AX_ERR_L0_PROMOTE_TO_L1:
|
case HALT_C2H_L1_DBG_MODE:
|
adapter->sm.fw_rst = MAC_AX_FW_RESET_RECV;
|
break;
|
case MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE:
|
adapter->sm.fw_rst = MAC_AX_FW_RESET_PROCESS;
|
break;
|
case MAC_AX_ERR_L1_RESET_RECOVERY_DONE:
|
adapter->sm.fw_rst = MAC_AX_FW_RESET_IDLE;
|
break;
|
default:
|
break;
|
}
|
|
/* Decode the error status from halc2h */
|
error_scenario = (*err) >> DBG_SENARIO_SH;
|
if (!(MAC_REG_R32(R_AX_UDM0) & B_AX_UDM0_DBG_MODE_CTRL)) {
|
if (error_scenario == CPU_EXCEPTION)
|
*err = MAC_AX_ERR_CPU_EXCEPTION;
|
else if (error_scenario == ASSERTION)
|
*err = MAC_AX_ERR_ASSERTION;
|
else if (error_scenario == RXI300_ERROR)
|
*err = MAC_AX_ERR_RXI300;
|
}
|
|
//3 3. Execute Recode Normal Debug Register
|
fw_st_dbg_dump(adapter);
|
mac_dump_err_status(adapter, *err);
|
if (*err == MAC_AX_ERR_L0_ERR_CMAC0 ||
|
*err == MAC_AX_ERR_L0_ERR_CMAC1) {
|
pltfm_dbg_dump(adapter);
|
}
|
|
//3 4. Execute Recode Share memory debug information
|
if (MAC_REG_R32(R_AX_UDM0) & B_AX_UDM0_DBG_MODE_CTRL) {
|
/* if debug mode =1 , dump share buffer */
|
if (error_scenario) {
|
*err = (enum mac_ax_err_info)MAC_AX_DUMP_SHAREBUFF_INDICATOR;
|
//notify phl to print share buffer
|
}
|
}
|
|
//3 5. dump detailed log for further debug usage.
|
mac_dbg_log_dump(adapter);
|
end:
|
adapter->sm.l2_st = MAC_AX_L2_EN;
|
PLTFM_MUTEX_UNLOCK(&adapter->hw_info->err_get_lock);
|
return ret;
|
}
|
|
u32 mac_lv1_rcvy(struct mac_ax_adapter *adapter, enum mac_ax_lv1_rcvy_step step)
|
{
|
u32 ret = MACSUCCESS;
|
#if MAC_AX_PCIE_SUPPORT
|
u8 val8;
|
#endif
|
|
switch (step) {
|
case MAC_AX_LV1_RCVY_STEP_1:
|
if (adapter->sm.fw_rst != MAC_AX_FW_RESET_RECV) {
|
PLTFM_MSG_ERR("The rst-flow state is wrong\n");
|
return MACPROCERR;
|
}
|
#if MAC_AX_PCIE_SUPPORT
|
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8851B) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8852BT)) {
|
if (adapter->hw_info->intf == MAC_AX_INTF_PCIE) {
|
val8 = 0;
|
ret = lv1rst_stop_dma_pcie(adapter, val8);
|
if (ret) {
|
PLTFM_MSG_ERR("lv1 rcvy pcie stop dma fail\n");
|
return ret;
|
}
|
}
|
} else {
|
// 52C PCIE Stop flow made in FW
|
}
|
#endif
|
|
#if MAC_AX_USB_SUPPORT
|
if (adapter->hw_info->intf == MAC_AX_INTF_USB) {
|
ret = usb_flush_mode(adapter, MAC_AX_FUNC_EN);
|
if (ret) {
|
PLTFM_MSG_ERR("lv1 rcvy USB flush mode fail\n");
|
return ret;
|
}
|
PLTFM_DELAY_MS(30);
|
}
|
#endif
|
break;
|
|
case MAC_AX_LV1_RCVY_STEP_2:
|
if (adapter->sm.fw_rst != MAC_AX_FW_RESET_PROCESS) {
|
PLTFM_MSG_ERR("The rst-flow state is wrong\n");
|
return MACPROCERR;
|
}
|
#if MAC_AX_PCIE_SUPPORT
|
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8851B) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8852BT)) {
|
if (adapter->hw_info->intf == MAC_AX_INTF_PCIE) {
|
val8 = 0;
|
ret = lv1rst_start_dma_pcie(adapter, val8);
|
if (ret) {
|
PLTFM_MSG_ERR("lv1 rcvy pcie start dma fail\n");
|
return ret;
|
}
|
}
|
} else {
|
// 52C PCIE Stop flow made in FW
|
}
|
#endif
|
|
#if MAC_AX_USB_SUPPORT
|
if (adapter->hw_info->intf == MAC_AX_INTF_USB) {
|
ret = 0;
|
ret = usb_flush_mode(adapter, MAC_AX_FUNC_DIS);
|
if (ret) {
|
PLTFM_MSG_ERR("lv1 rcvy USB norm mode fail\n");
|
return ret;
|
}
|
}
|
#endif
|
break;
|
|
default:
|
return MACLV1STEPERR;
|
}
|
|
return ret;
|
}
|
|
u32 mac_err_imr_ctrl(struct mac_ax_adapter *adapter, enum mac_ax_func_sw sw)
|
{
|
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
|
u32 v32_dmac, v32_cmac0, v32_cmac1;
|
u32 ret = MACSUCCESS;
|
u8 is_dbcc;
|
|
v32_dmac = sw != MAC_AX_FUNC_DIS ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS;
|
v32_cmac0 = sw != MAC_AX_FUNC_DIS ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS;
|
v32_cmac1 = sw != MAC_AX_FUNC_DIS ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS;
|
is_dbcc = is_curr_dbcc(adapter);
|
|
#if MAC_AX_FW_REG_OFLD
|
if (adapter->sm.fwdl == MAC_AX_FWDL_INIT_RDY) {
|
ret = MAC_REG_W_OFLD((u16)R_AX_DMAC_ERR_IMR, DMAC_ERR_IMR_MASK,
|
v32_dmac, 0);
|
if (ret != MACSUCCESS) {
|
PLTFM_MSG_ERR("dmac err imr w ofld fail\n");
|
return ret;
|
}
|
|
ret = MAC_REG_W_OFLD((u16)R_AX_CMAC_ERR_IMR, CMAC0_ERR_IMR_MASK,
|
v32_cmac0, (is_dbcc ? 0 : 1));
|
if (ret != MACSUCCESS) {
|
PLTFM_MSG_ERR("cmac0 err imr w ofld fail\n");
|
return ret;
|
}
|
|
if (is_dbcc) {
|
ret = MAC_REG_W_OFLD((u16)R_AX_CMAC_ERR_IMR_C1,
|
CMAC1_ERR_IMR_MASK,
|
v32_cmac1, 1);
|
if (ret != MACSUCCESS) {
|
PLTFM_MSG_ERR("cmac1 err imr w ofld fail\n");
|
return ret;
|
}
|
}
|
|
return ret;
|
}
|
#endif
|
|
MAC_REG_W32(R_AX_DMAC_ERR_IMR, v32_dmac);
|
MAC_REG_W32(R_AX_CMAC_ERR_IMR, v32_cmac0);
|
|
if (is_dbcc)
|
MAC_REG_W32(R_AX_CMAC_ERR_IMR_C1, v32_cmac1);
|
|
return ret;
|
}
|
|
static void dump_err_status_dispatcher(struct mac_ax_adapter *adapter)
|
{
|
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
|
|
PLTFM_MSG_ERR("R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n",
|
MAC_REG_R32(R_AX_HOST_DISPATCHER_ERR_IMR));
|
PLTFM_MSG_ERR("R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n",
|
MAC_REG_R32(R_AX_HOST_DISPATCHER_ERR_ISR));
|
|
PLTFM_MSG_ERR("R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n",
|
MAC_REG_R32(R_AX_CPU_DISPATCHER_ERR_IMR));
|
PLTFM_MSG_ERR("R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n",
|
MAC_REG_R32(R_AX_CPU_DISPATCHER_ERR_ISR));
|
PLTFM_MSG_ERR("R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x ",
|
MAC_REG_R32(R_AX_OTHER_DISPATCHER_ERR_IMR));
|
PLTFM_MSG_ERR("R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n",
|
MAC_REG_R32(R_AX_OTHER_DISPATCHER_ERR_ISR));
|
}
|
|
static void dump_err_status_dmac(struct mac_ax_adapter *adapter)
|
{
|
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
|
u32 dmac_err;
|
|
dmac_err = MAC_REG_R32(R_AX_DMAC_ERR_ISR);
|
PLTFM_MSG_ERR("R_AX_DMAC_ERR_ISR =0x%08x\n", dmac_err);
|
PLTFM_MSG_ALWAYS("R_AX_DMAC_ERR_IMR=0x%x\n",
|
MAC_REG_R32(R_AX_DMAC_ERR_IMR));
|
|
PLTFM_MSG_ERR("R_AX_DMAC_FUNC_EN =0x%08x\n",
|
MAC_REG_R32(R_AX_DMAC_FUNC_EN));
|
PLTFM_MSG_ERR("R_AX_DMAC_CLK_EN =0x%08x\n",
|
MAC_REG_R32(R_AX_DMAC_CLK_EN));
|
|
if (dmac_err) {
|
PLTFM_MSG_ERR("R_AX_WDE_ERR_FLAG_CFG =0x%08x\n",
|
MAC_REG_R32(R_AX_WDE_ERR_FLAG_CFG_NUM1));
|
PLTFM_MSG_ERR("R_AX_PLE_ERR_FLAG_CFG =0x%08x\n",
|
MAC_REG_R32(R_AX_PLE_ERR_FLAG_CFG_NUM1));
|
#if MAC_AX_8852C_SUPPORT || MAC_AX_8192XB_SUPPORT || MAC_AX_8851E_SUPPORT || MAC_AX_8852D_SUPPORT
|
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8851E) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8852D)) {
|
PLTFM_MSG_ERR("R_AX_PLE_ERRFLAG_MSG =0x%08x\n",
|
MAC_REG_R32(R_AX_PLE_ERRFLAG_MSG));
|
PLTFM_MSG_ERR("R_AX_PLE_ERRFLAG_MSG 0x9030 Reg dump =0x%08x\n",
|
MAC_REG_R32(R_AX_PLE_ERRFLAG_MSG));
|
PLTFM_MSG_ERR("R_AX_WDE_ERRFLAG_MSG 0x8C30 Reg dump =0x%08x\n",
|
MAC_REG_R32(R_AX_WDE_ERRFLAG_MSG));
|
PLTFM_MSG_ERR("R_AX_PLE_DBGERR_LOCKEN 0x9020 Reg dump =0x%08x\n",
|
MAC_REG_R32(R_AX_PLE_DBGERR_LOCKEN));
|
PLTFM_MSG_ERR("R_AX_PLE_DBGERR_STS 0x9024 Reg dump =0x%08x\n",
|
MAC_REG_R32(R_AX_PLE_DBGERR_STS));
|
}
|
#endif
|
}
|
|
if (dmac_err & B_AX_WDRLS_ERR_FLAG) {
|
PLTFM_MSG_ERR("R_AX_WDRLS_ERR_IMR =0x%08x\n",
|
MAC_REG_R32(R_AX_WDRLS_ERR_IMR));
|
PLTFM_MSG_ERR("R_AX_WDRLS_ERR_ISR =0x%08x\n",
|
MAC_REG_R32(R_AX_WDRLS_ERR_ISR));
|
#if MAC_AX_8852A_SUPPORT || MAC_AX_8852B_SUPPORT || MAC_AX_8851B_SUPPORT || MAC_AX_8852BT_SUPPORT
|
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8851B) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8852BT)) {
|
PLTFM_MSG_ERR("R_AX_RPQ_RXBD_IDX =0x%08x\n",
|
MAC_REG_R32(R_AX_RPQ_RXBD_IDX));
|
}
|
#endif
|
#if MAC_AX_8852C_SUPPORT || MAC_AX_8192XB_SUPPORT || MAC_AX_8851E_SUPPORT || MAC_AX_8852D_SUPPORT
|
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8851E) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8852D)) {
|
PLTFM_MSG_ERR("R_AX_RPQ_RXBD_IDX =0x%08x\n",
|
MAC_REG_R32(R_AX_RPQ_RXBD_IDX_V1));
|
}
|
#endif
|
}
|
|
if (dmac_err & B_AX_WSEC_ERR_FLAG) {
|
#if MAC_AX_8852A_SUPPORT || MAC_AX_8852B_SUPPORT || MAC_AX_8851B_SUPPORT || MAC_AX_8852BT_SUPPORT
|
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8851B) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8852BT)) {
|
PLTFM_MSG_ERR("R_AX_SEC_ERR_IMR_ISR =0x%08x\n",
|
MAC_REG_R32(R_AX_SEC_DEBUG));
|
PLTFM_MSG_ERR("SEC_local_Register 0x9D00 =0x%08x\n",
|
MAC_REG_R32(R_AX_SEC_ENG_CTRL));
|
PLTFM_MSG_ERR("SEC_local_Register 0x9D04 =0x%08x\n",
|
MAC_REG_R32(R_AX_SEC_MPDU_PROC));
|
PLTFM_MSG_ERR("SEC_local_Register 0x9D10 =0x%08x\n",
|
MAC_REG_R32(R_AX_SEC_CAM_ACCESS));
|
PLTFM_MSG_ERR("SEC_local_Register 0x9D14 =0x%08x\n",
|
MAC_REG_R32(R_AX_SEC_CAM_RDATA));
|
PLTFM_MSG_ERR("SEC_local_Register 0x9D18 =0x%08x\n",
|
MAC_REG_R32(R_AX_SEC_CAM_WDATA));
|
PLTFM_MSG_ERR("SEC_local_Register 0x9D20 =0x%08x\n",
|
MAC_REG_R32(R_AX_SEC_TX_DEBUG));
|
PLTFM_MSG_ERR("SEC_local_Register 0x9D24 =0x%08x\n",
|
MAC_REG_R32(R_AX_SEC_RX_DEBUG));
|
PLTFM_MSG_ERR("SEC_local_Register 0x9D28 =0x%08x\n",
|
MAC_REG_R32(R_AX_SEC_TRX_PKT_CNT));
|
PLTFM_MSG_ERR("SEC_local_Register 0x9D2C =0x%08x\n",
|
MAC_REG_R32(R_AX_SEC_TRX_BLK_CNT));
|
}
|
#endif
|
#if MAC_AX_8852C_SUPPORT || MAC_AX_8192XB_SUPPORT || MAC_AX_8851E_SUPPORT || MAC_AX_8852D_SUPPORT
|
u32 val32 = 0, i = 0;
|
|
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8851E) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8852D)) {
|
PLTFM_MSG_ERR("R_AX_SEC_ERR_IMR =0x%08x\n",
|
MAC_REG_R32(R_AX_SEC_ERROR_FLAG_IMR));
|
PLTFM_MSG_ERR("R_AX_SEC_ERR_ISR =0x%08x\n",
|
MAC_REG_R32(R_AX_SEC_ERROR_FLAG));
|
PLTFM_MSG_ERR("SEC_local_Register 0x9D00 =0x%08x\n",
|
MAC_REG_R32(R_AX_SEC_ENG_CTRL));
|
PLTFM_MSG_ERR("SEC_local_Register 0x9D04 =0x%08x\n",
|
MAC_REG_R32(R_AX_SEC_MPDU_PROC));
|
PLTFM_MSG_ERR("SEC_local_Register 0x9D10 =0x%08x\n",
|
MAC_REG_R32(R_AX_SEC_CAM_ACCESS));
|
PLTFM_MSG_ERR("SEC_local_Register 0x9D14 =0x%08x\n",
|
MAC_REG_R32(R_AX_SEC_CAM_RDATA));
|
PLTFM_MSG_ERR("SEC_local_Register 0x9D1C =0x%08x\n",
|
MAC_REG_R32(R_AX_SEC_DEBUG1));
|
PLTFM_MSG_ERR("SEC_local_Register 0x9D20 =0x%08x\n",
|
MAC_REG_R32(R_AX_SEC_TX_DEBUG));
|
PLTFM_MSG_ERR("SEC_local_Register 0x9D24 =0x%08x\n",
|
MAC_REG_R32(R_AX_SEC_RX_DEBUG));
|
PLTFM_MSG_ERR("SEC_local_Register 0x9D28 =0x%08x\n",
|
MAC_REG_R32(R_AX_SEC_DEBUG2));
|
|
val32 = MAC_REG_R32(R_AX_DBG_CTRL);
|
val32 = SET_CLR_WORD(val32, SEC_DBG_SEL, B_AX_DBG_SEL0);
|
val32 = SET_CLR_WORD(val32, SEC_DBG_SEL, B_AX_DBG_SEL1);
|
MAC_REG_W32(R_AX_DBG_CTRL, val32);
|
|
val32 = MAC_REG_R32(R_AX_SYS_STATUS1);
|
val32 = SET_CLR_WORD(val32, MAC_DBG_SEL, B_AX_SEL_0XC0);
|
MAC_REG_W32(R_AX_SYS_STATUS1, val32);
|
PLTFM_MSG_ALWAYS("SECURITY ENGINE DEBUG PORT DUMP\n");
|
for (i = 0; i < SEC_DBG_PORT_NUM; i++) {
|
val32 = MAC_REG_R32(R_AX_SEC_ENG_CTRL);
|
val32 = SET_CLR_WORD(val32, i, SEC_DBG_PORT_FIELD);
|
MAC_REG_W32(R_AX_SEC_ENG_CTRL, val32);
|
PLTFM_MSG_ERR("debug sel = %x, 0x9D28 =0x%08x\n",
|
i, MAC_REG_R32(R_AX_SEC_DEBUG2));
|
}
|
}
|
#endif
|
}
|
|
if (dmac_err & B_AX_MPDU_ERR_FLAG) {
|
PLTFM_MSG_ERR("R_AX_MPDU_TX_ERR_IMR =0x%08x\n",
|
MAC_REG_R32(R_AX_MPDU_TX_ERR_IMR));
|
PLTFM_MSG_ERR("R_AX_MPDU_TX_ERR_ISR =0x%08x\n",
|
MAC_REG_R32(R_AX_MPDU_TX_ERR_ISR));
|
PLTFM_MSG_ERR("R_AX_MPDU_RX_ERR_IMR =0x%08x\n",
|
MAC_REG_R32(R_AX_MPDU_RX_ERR_IMR));
|
PLTFM_MSG_ERR("R_AX_MPDU_RX_ERR_ISR =0x%08x\n",
|
MAC_REG_R32(R_AX_MPDU_RX_ERR_ISR));
|
}
|
|
if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) {
|
PLTFM_MSG_ERR("R_AX_STA_SCHEDULER_ERR_IMR =0x%08x\n",
|
MAC_REG_R32(R_AX_STA_SCHEDULER_ERR_IMR));
|
PLTFM_MSG_ERR("R_AX_STA_SCHEDULER_ERR_ISR= 0x%08x\n",
|
MAC_REG_R32(R_AX_STA_SCHEDULER_ERR_ISR));
|
}
|
|
if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) {
|
PLTFM_MSG_ERR("R_AX_WDE_ERR_IMR=0x%08x\n",
|
MAC_REG_R32(R_AX_WDE_ERR_IMR));
|
PLTFM_MSG_ERR("R_AX_WDE_ERR_ISR=0x%08x\n",
|
MAC_REG_R32(R_AX_WDE_ERR_ISR));
|
PLTFM_MSG_ERR("R_AX_PLE_ERR_IMR=0x%08x\n",
|
MAC_REG_R32(R_AX_PLE_ERR_IMR));
|
PLTFM_MSG_ERR("R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
|
MAC_REG_R32(R_AX_PLE_ERR_FLAG_ISR));
|
}
|
|
if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) {
|
#if MAC_AX_8852A_SUPPORT || MAC_AX_8852B_SUPPORT || MAC_AX_8851B_SUPPORT || MAC_AX_8852BT_SUPPORT
|
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8851B) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8852BT)) {
|
PLTFM_MSG_ERR("R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n",
|
MAC_REG_R32(R_AX_TXPKTCTL_ERR_IMR_ISR));
|
PLTFM_MSG_ERR("R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n",
|
MAC_REG_R32(R_AX_TXPKTCTL_ERR_IMR_ISR_B1));
|
}
|
#endif
|
#if MAC_AX_8852C_SUPPORT || MAC_AX_8192XB_SUPPORT || MAC_AX_8851E_SUPPORT || MAC_AX_8852D_SUPPORT
|
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8851E) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8852D)) {
|
PLTFM_MSG_ERR("R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n",
|
MAC_REG_R32(R_AX_TXPKTCTL_B0_ERRFLAG_IMR));
|
PLTFM_MSG_ERR("R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n",
|
MAC_REG_R32(R_AX_TXPKTCTL_B0_ERRFLAG_ISR));
|
PLTFM_MSG_ERR("R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n",
|
MAC_REG_R32(R_AX_TXPKTCTL_B1_ERRFLAG_IMR));
|
PLTFM_MSG_ERR("R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n",
|
MAC_REG_R32(R_AX_TXPKTCTL_B1_ERRFLAG_ISR));
|
}
|
#endif
|
}
|
|
if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) {
|
PLTFM_MSG_ERR("R_AX_WDE_ERR_IMR=0x%08x\n",
|
MAC_REG_R32(R_AX_WDE_ERR_IMR));
|
PLTFM_MSG_ERR("R_AX_WDE_ERR_ISR=0x%08x\n",
|
MAC_REG_R32(R_AX_WDE_ERR_ISR));
|
PLTFM_MSG_ERR("R_AX_PLE_ERR_IMR=0x%08x\n",
|
MAC_REG_R32(R_AX_PLE_ERR_IMR));
|
PLTFM_MSG_ERR("R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
|
MAC_REG_R32(R_AX_PLE_ERR_FLAG_ISR));
|
PLTFM_MSG_ERR("R_AX_WD_CPUQ_OP_0=0x%08x\n",
|
MAC_REG_R32(R_AX_WD_CPUQ_OP_0));
|
PLTFM_MSG_ERR("R_AX_WD_CPUQ_OP_1=0x%08x\n",
|
MAC_REG_R32(R_AX_WD_CPUQ_OP_1));
|
PLTFM_MSG_ERR("R_AX_WD_CPUQ_OP_2=0x%08x\n",
|
MAC_REG_R32(R_AX_WD_CPUQ_OP_2));
|
PLTFM_MSG_ERR("R_AX_WD_CPUQ_OP_STATUS=0x%08x\n",
|
MAC_REG_R32(R_AX_WD_CPUQ_OP_STATUS));
|
PLTFM_MSG_ERR("R_AX_PL_CPUQ_OP_0=0x%08x\n",
|
MAC_REG_R32(R_AX_PL_CPUQ_OP_0));
|
PLTFM_MSG_ERR("R_AX_PL_CPUQ_OP_1=0x%08x\n",
|
MAC_REG_R32(R_AX_PL_CPUQ_OP_1));
|
PLTFM_MSG_ERR("R_AX_PL_CPUQ_OP_2=0x%08x\n",
|
MAC_REG_R32(R_AX_PL_CPUQ_OP_2));
|
PLTFM_MSG_ERR("R_AX_PL_CPUQ_OP_STATUS=0x%08x\n",
|
MAC_REG_R32(R_AX_PL_CPUQ_OP_STATUS));
|
#if MAC_AX_8852A_SUPPORT || MAC_AX_8852B_SUPPORT || MAC_AX_8851B_SUPPORT || MAC_AX_8852BT_SUPPORT
|
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8851B) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8852BT)) {
|
PLTFM_MSG_ERR("R_AX_RXDMA_PKT_INFO_0=0x%08x\n",
|
MAC_REG_R32(R_AX_RXDMA_PKT_INFO_0));
|
PLTFM_MSG_ERR("R_AX_RXDMA_PKT_INFO_1=0x%08x\n",
|
MAC_REG_R32(R_AX_RXDMA_PKT_INFO_1));
|
PLTFM_MSG_ERR("R_AX_RXDMA_PKT_INFO_2=0x%08x\n",
|
MAC_REG_R32(R_AX_RXDMA_PKT_INFO_2));
|
}
|
#endif
|
#if MAC_AX_8852C_SUPPORT || MAC_AX_8192XB_SUPPORT || MAC_AX_8851E_SUPPORT || MAC_AX_8852D_SUPPORT
|
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8851E) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8852D)) {
|
PLTFM_MSG_ERR("R_AX_RX_CTRL0=0x%08x\n",
|
MAC_REG_R32(R_AX_RX_CTRL0));
|
PLTFM_MSG_ERR("R_AX_RX_CTRL1=0x%08x\n",
|
MAC_REG_R32(R_AX_RX_CTRL1));
|
PLTFM_MSG_ERR("R_AX_RX_CTRL2=0x%08x\n",
|
MAC_REG_R32(R_AX_RX_CTRL2));
|
}
|
#endif
|
dump_err_status_dispatcher(adapter);
|
}
|
|
if (dmac_err & B_AX_PKTIN_ERR_FLAG) {
|
PLTFM_MSG_ERR("R_AX_PKTIN_ERR_IMR =0x%08x\n",
|
MAC_REG_R32(R_AX_PKTIN_ERR_IMR));
|
PLTFM_MSG_ERR("R_AX_PKTIN_ERR_ISR =0x%08x\n",
|
MAC_REG_R32(R_AX_PKTIN_ERR_ISR));
|
PLTFM_MSG_ERR("R_AX_PKTIN_ERR_IMR =0x%08x ",
|
MAC_REG_R32(R_AX_PKTIN_ERR_IMR));
|
PLTFM_MSG_ERR("R_AX_PKTIN_ERR_ISR =0x%08x\n",
|
MAC_REG_R32(R_AX_PKTIN_ERR_ISR));
|
}
|
|
if (dmac_err & B_AX_DISPATCH_ERR_FLAG)
|
dump_err_status_dispatcher(adapter);
|
|
if (dmac_err & B_AX_DLE_CPUIO_ERR_FLAG) {
|
PLTFM_MSG_ERR("R_AX_CPUIO_ERR_IMR=0x%08x\n",
|
MAC_REG_R32(R_AX_CPUIO_ERR_IMR));
|
PLTFM_MSG_ERR("R_AX_CPUIO_ERR_ISR=0x%08x\n",
|
MAC_REG_R32(R_AX_CPUIO_ERR_ISR));
|
}
|
|
if (dmac_err & B_AX_BBRPT_ERR_FLAG) {
|
#if MAC_AX_8852A_SUPPORT || MAC_AX_8852B_SUPPORT || MAC_AX_8851B_SUPPORT || MAC_AX_8852BT_SUPPORT
|
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8851B) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8852BT)) {
|
PLTFM_MSG_ERR("R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n",
|
MAC_REG_R32(R_AX_BBRPT_COM_ERR_IMR_ISR));
|
PLTFM_MSG_ERR("R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n",
|
MAC_REG_R32(R_AX_BBRPT_CHINFO_ERR_ISR));
|
PLTFM_MSG_ERR("R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n",
|
MAC_REG_R32(R_AX_BBRPT_CHINFO_ERR_IMR));
|
PLTFM_MSG_ERR("R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n",
|
MAC_REG_R32(R_AX_BBRPT_DFS_ERR_IMR));
|
PLTFM_MSG_ERR("R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n",
|
MAC_REG_R32(R_AX_BBRPT_DFS_ERR_ISR));
|
}
|
#endif
|
#if MAC_AX_8852C_SUPPORT || MAC_AX_8192XB_SUPPORT || MAC_AX_8851E_SUPPORT || MAC_AX_8852D_SUPPORT
|
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8851E) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8852D)) {
|
PLTFM_MSG_ERR("R_AX_BBRPT_COM_ERR_IMR=0x%08x\n",
|
MAC_REG_R32(R_AX_BBRPT_COM_ERR_IMR));
|
PLTFM_MSG_ERR("R_AX_BBRPT_COM_ERR_ISR=0x%08x\n",
|
MAC_REG_R32(R_AX_BBRPT_COM_ERR_ISR));
|
PLTFM_MSG_ERR("R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n",
|
MAC_REG_R32(R_AX_BBRPT_CHINFO_ERR_ISR));
|
PLTFM_MSG_ERR("R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n",
|
MAC_REG_R32(R_AX_BBRPT_CHINFO_ERR_IMR));
|
PLTFM_MSG_ERR("R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n",
|
MAC_REG_R32(R_AX_BBRPT_DFS_ERR_IMR));
|
PLTFM_MSG_ERR("R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n",
|
MAC_REG_R32(R_AX_BBRPT_DFS_ERR_ISR));
|
}
|
#endif
|
}
|
|
if (dmac_err & B_AX_HAXIDMA_ERR_FLAG) {
|
#if MAC_AX_8852C_SUPPORT || MAC_AX_8192XB_SUPPORT || MAC_AX_8851E_SUPPORT || MAC_AX_8852D_SUPPORT
|
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8851E) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8852D)) {
|
PLTFM_MSG_ERR("R_AX_HAXIDMA_ERR_IMR=0x%08x\n",
|
MAC_REG_R32(R_AX_HAXI_IDCT_MSK));
|
PLTFM_MSG_ERR("R_AX_HAXIDMA_ERR_ISR=0x%08x\n",
|
MAC_REG_R32(R_AX_HAXI_IDCT));
|
}
|
#endif
|
}
|
}
|
|
static void dump_err_status_cmac(struct mac_ax_adapter *adapter, u8 band)
|
{
|
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
|
u32 cmac_err;
|
u32 ret;
|
|
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
|
if (ret != MACSUCCESS)
|
return;
|
|
PLTFM_MSG_ERR("CMAC Band =0x%02x\n", band);
|
|
cmac_err = MAC_REG_R32(band == MAC_AX_BAND_0 ? R_AX_CMAC_ERR_ISR :
|
R_AX_CMAC_ERR_ISR_C1);
|
PLTFM_MSG_ERR("R_AX_CMAC_ERR_ISR =0x%08x\n", cmac_err);
|
|
PLTFM_MSG_ERR("R_AX_CMAC_FUNC_EN =0x%08x\n",
|
MAC_REG_R32(band == MAC_AX_BAND_0 ? R_AX_CMAC_FUNC_EN :
|
R_AX_CMAC_FUNC_EN_C1));
|
PLTFM_MSG_ERR("R_AX_CK_EN =0x%08x\n",
|
MAC_REG_R32(band == MAC_AX_BAND_0 ? R_AX_CK_EN :
|
R_AX_CK_EN_C1));
|
|
if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) {
|
PLTFM_MSG_ERR("R_AX_SCHEDULE_ERR_IMR=0x%08x\n",
|
MAC_REG_R32(band == MAC_AX_BAND_0 ?
|
R_AX_SCHEDULE_ERR_IMR : R_AX_SCHEDULE_ERR_IMR_C1));
|
PLTFM_MSG_ERR("R_AX_SCHEDULE_ERR_ISR=0x%04x\n",
|
MAC_REG_R16(band == MAC_AX_BAND_0 ?
|
R_AX_SCHEDULE_ERR_ISR : R_AX_SCHEDULE_ERR_ISR_C1));
|
}
|
|
if (cmac_err & B_AX_PTCL_TOP_ERR_IND) {
|
PLTFM_MSG_ERR("R_AX_PTCL_IMR0=0x%08x\n",
|
MAC_REG_R32(band == MAC_AX_BAND_0 ?
|
R_AX_PTCL_IMR0 : R_AX_PTCL_IMR0_C1));
|
PLTFM_MSG_ERR("R_AX_PTCL_ISR0=0x%08x\n",
|
MAC_REG_R32(band == MAC_AX_BAND_0 ?
|
R_AX_PTCL_ISR0 : R_AX_PTCL_ISR0_C1));
|
}
|
|
if (cmac_err & B_AX_DMA_TOP_ERR_IND) {
|
#if MAC_AX_8852A_SUPPORT || MAC_AX_8852B_SUPPORT || MAC_AX_8851B_SUPPORT || MAC_AX_8852BT_SUPPORT
|
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8851B) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8852BT)) {
|
PLTFM_MSG_ERR("R_AX_DLE_CTRL (0xC800)=0x%08x\n",
|
MAC_REG_R32(band == MAC_AX_BAND_0 ?
|
R_AX_DLE_CTRL : R_AX_DLE_CTRL_C1));
|
PLTFM_MSG_ERR("0xC828=0x%08x\n",
|
MAC_REG_R32(band == MAC_AX_BAND_0 ?
|
R_AX_RX_INFO_RXSTS : R_AX_RX_INFO_RXSTS_C1));
|
}
|
#endif
|
#if MAC_AX_8852C_SUPPORT || MAC_AX_8192XB_SUPPORT || MAC_AX_8851E_SUPPORT || MAC_AX_8852D_SUPPORT
|
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8851E) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8852D)) {
|
PLTFM_MSG_ERR("R_AX_RX_ERR_FLAG (0xC800)=0x%08x\n",
|
MAC_REG_R32(band == MAC_AX_BAND_0 ?
|
R_AX_RX_ERR_FLAG : R_AX_RX_ERR_FLAG_C1));
|
PLTFM_MSG_ERR("R_AX_RX_ERR_FLAG_IMR (0xC804)=0x%08x\n",
|
MAC_REG_R32(band == MAC_AX_BAND_0 ?
|
R_AX_RX_ERR_FLAG_IMR : R_AX_RX_ERR_FLAG_IMR_C1));
|
PLTFM_MSG_ERR("R_AX_RX_ERR_FLAG (0xC86C)=0x%08x\n",
|
MAC_REG_R32(band == MAC_AX_BAND_0 ?
|
R_AX_TX_ERR_FLAG : R_AX_TX_ERR_FLAG_C1));
|
PLTFM_MSG_ERR("R_AX_RX_ERR_FLAG_IMR (0xC870)=0x%08x\n",
|
MAC_REG_R32(band == MAC_AX_BAND_0 ?
|
R_AX_TX_ERR_FLAG_IMR : R_AX_TX_ERR_FLAG_IMR_C1));
|
}
|
#endif
|
}
|
|
if (cmac_err & B_AX_PHYINTF_ERR_IND) {
|
#if MAC_AX_8852A_SUPPORT || MAC_AX_8852B_SUPPORT || MAC_AX_8851B_SUPPORT || MAC_AX_8852BT_SUPPORT
|
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8851B) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8852BT)) {
|
PLTFM_MSG_ERR("R_AX_PHYINFO_ERR_IMR=0x%04x\n",
|
MAC_REG_R32(band == MAC_AX_BAND_0 ?
|
R_AX_PHYINFO_ERR_IMR :
|
R_AX_PHYINFO_ERR_IMR_C1));
|
}
|
#endif
|
#if MAC_AX_8852C_SUPPORT || MAC_AX_8192XB_SUPPORT || MAC_AX_8851E_SUPPORT || MAC_AX_8852D_SUPPORT
|
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8851E) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8852D)) {
|
PLTFM_MSG_ERR("R_AX_PHYINFO_ERR_ISR=0x%04x\n",
|
MAC_REG_R32(band == MAC_AX_BAND_0 ?
|
R_AX_PHYINFO_ERR_ISR :
|
R_AX_PHYINFO_ERR_ISR_C1));
|
PLTFM_MSG_ERR("R_AX_PHYINFO_ERR_IMR=0x%04x\n",
|
MAC_REG_R32(band == MAC_AX_BAND_0 ?
|
R_AX_PHYINFO_ERR_IMR_V1 :
|
R_AX_PHYINFO_ERR_IMR_V1_C1));
|
}
|
#endif
|
}
|
|
if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) {
|
PLTFM_MSG_ERR("R_AX_TXPWR_IMR=0x%08x\n",
|
MAC_REG_R32(band == MAC_AX_BAND_0 ?
|
R_AX_TXPWR_IMR : R_AX_TXPWR_IMR_C1));
|
PLTFM_MSG_ERR("R_AX_TXPWR_ISR=0x%08x\n",
|
MAC_REG_R32(band == MAC_AX_BAND_0 ?
|
R_AX_TXPWR_ISR : R_AX_TXPWR_ISR_C1));
|
}
|
|
if (cmac_err & B_AX_WMAC_RX_ERR_IND) {
|
PLTFM_MSG_ERR("R_AX_DBGSEL_TRXPTCL=0x%08x\n",
|
MAC_REG_R32(band == MAC_AX_BAND_0 ?
|
R_AX_DBGSEL_TRXPTCL : R_AX_DBGSEL_TRXPTCL_C1));
|
#if MAC_AX_8852A_SUPPORT || MAC_AX_8852B_SUPPORT || MAC_AX_8851B_SUPPORT || MAC_AX_8852BT_SUPPORT
|
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8851B) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8852BT)) {
|
PLTFM_MSG_ERR("R_AX_PHYINFO_ERR_IMR=0x%04x\n",
|
MAC_REG_R32(band == MAC_AX_BAND_0 ?
|
R_AX_PHYINFO_ERR_IMR :
|
R_AX_PHYINFO_ERR_IMR_C1));
|
PLTFM_MSG_ERR("R_AX_RMAC_ERR_ISR=0x%04x\n",
|
MAC_REG_R32(band == MAC_AX_BAND_0 ?
|
R_AX_RMAC_ERR_ISR :
|
R_AX_RMAC_ERR_ISR_C1));
|
}
|
#endif
|
#if MAC_AX_8852C_SUPPORT || MAC_AX_8192XB_SUPPORT || MAC_AX_8851E_SUPPORT || MAC_AX_8852D_SUPPORT
|
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8851E) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8852D)) {
|
PLTFM_MSG_ERR("R_AX_PHYINFO_ERR_ISR=0x%04x\n",
|
MAC_REG_R32(band == MAC_AX_BAND_0 ?
|
R_AX_PHYINFO_ERR_ISR :
|
R_AX_PHYINFO_ERR_ISR_C1));
|
PLTFM_MSG_ERR("R_AX_PHYINFO_ERR_IMR=0x%04x\n",
|
MAC_REG_R32(band == MAC_AX_BAND_0 ?
|
R_AX_PHYINFO_ERR_IMR_V1 :
|
R_AX_PHYINFO_ERR_IMR_V1_C1));
|
PLTFM_MSG_ERR("R_AX_RX_ERR_ISR=0x%04x\n",
|
MAC_REG_R32(band == MAC_AX_BAND_0 ?
|
R_AX_RX_ERR_ISR :
|
R_AX_RX_ERR_ISR_C1));
|
PLTFM_MSG_ERR("R_AX_RX_ERR_IMR=0x%04x\n",
|
MAC_REG_R32(band == MAC_AX_BAND_0 ?
|
R_AX_RX_ERR_IMR :
|
R_AX_RX_ERR_IMR_C1));
|
}
|
#endif
|
}
|
|
if (cmac_err & B_AX_WMAC_TX_ERR_IND) {
|
#if MAC_AX_8852A_SUPPORT || MAC_AX_8852B_SUPPORT || MAC_AX_8851B_SUPPORT || MAC_AX_8852BT_SUPPORT
|
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852A) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8852B) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8851B) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8852BT)) {
|
PLTFM_MSG_ERR("R_AX_TMAC_ERR_IMR_ISR=0x%08x\n",
|
MAC_REG_R32(band == MAC_AX_BAND_0 ?
|
R_AX_TMAC_ERR_IMR_ISR :
|
R_AX_TMAC_ERR_IMR_ISR_C1));
|
}
|
#endif
|
#if MAC_AX_8852C_SUPPORT || MAC_AX_8192XB_SUPPORT || MAC_AX_8851E_SUPPORT || MAC_AX_8852D_SUPPORT
|
if (is_chip_id(adapter, MAC_AX_CHIP_ID_8852C) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8192XB) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8851E) ||
|
is_chip_id(adapter, MAC_AX_CHIP_ID_8852D)) {
|
PLTFM_MSG_ERR("R_AX_TRXPTCL_ERROR_INDICA=0x%08x\n",
|
MAC_REG_R32(band == MAC_AX_BAND_0 ?
|
R_AX_TRXPTCL_ERROR_INDICA :
|
R_AX_TRXPTCL_ERROR_INDICA_C1));
|
PLTFM_MSG_ERR("R_AX_TRXPTCL_ERROR_INDICA_MASK=0x%08x\n",
|
MAC_REG_R32(band == MAC_AX_BAND_0 ?
|
R_AX_TRXPTCL_ERROR_INDICA_MASK :
|
R_AX_TRXPTCL_ERROR_INDICA_MASK_C1));
|
}
|
#endif
|
PLTFM_MSG_ERR("R_AX_DBGSEL_TRXPTCL=0x%08x\n",
|
MAC_REG_R32(band == MAC_AX_BAND_0 ?
|
R_AX_DBGSEL_TRXPTCL : R_AX_DBGSEL_TRXPTCL_C1));
|
}
|
|
cmac_err = MAC_REG_R32(band == MAC_AX_BAND_1 ? R_AX_CMAC_ERR_IMR_C1 :
|
R_AX_CMAC_ERR_IMR);
|
PLTFM_MSG_ALWAYS("B%d R_AX_CMAC_ERR_IMR=0x%x\n", band, cmac_err);
|
}
|
|
u32 mac_ser_ctrl(struct mac_ax_adapter *adapter, enum mac_ax_func_sw sw)
|
{
|
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
|
enum mac_ax_err_info err_info;
|
u32 val32, ret, cnt;
|
|
if (sw == MAC_AX_FUNC_EN) {
|
err_info = MAC_AX_ERR_L1_RCVY_START_REQ;
|
adapter->sm.ser_ctrl_st = MAC_AX_SER_CTRL_SRT;
|
} else if (sw == MAC_AX_FUNC_DIS) {
|
err_info = MAC_AX_ERR_L1_RCVY_STOP_REQ;
|
adapter->sm.ser_ctrl_st = MAC_AX_SER_CTRL_STOP;
|
} else if (sw == MAC_AX_FUNC_WO_RECVY_DIS) {
|
err_info = MAC_AX_ERR_L1_RCVY_STOP_WO_RECVY_REQ;
|
adapter->sm.ser_ctrl_st = MAC_AX_SER_CTRL_SRT;
|
} else if (sw == MAC_AX_FUNC_WO_RECVY_EN) {
|
err_info = MAC_AX_ERR_L1_RCVY_START_WO_RECVY_REQ;
|
adapter->sm.ser_ctrl_st = MAC_AX_SER_CTRL_STOP;
|
} else {
|
adapter->sm.ser_ctrl_st = MAC_AX_SER_CTRL_ERR;
|
PLTFM_MSG_ERR("[ERR]SER ctrl input err %d\n", sw);
|
return MACFUNCINPUT;
|
}
|
|
ret = mac_set_err_status(adapter, err_info);
|
if (ret != MACSUCCESS) {
|
adapter->sm.ser_ctrl_st = MAC_AX_SER_CTRL_ERR;
|
PLTFM_MSG_ERR("[ERR]set err for stop ser %d\n", ret);
|
return ret;
|
}
|
|
cnt = MAC_SET_ERR_DLY_CNT;
|
while (cnt) {
|
val32 = MAC_REG_R32(R_AX_HALT_H2C_CTRL);
|
if (!(val32 & B_AX_HALT_H2C_TRIGGER))
|
break;
|
PLTFM_DELAY_US(MAC_SET_ERR_DLY_US);
|
cnt--;
|
}
|
|
if (!cnt) {
|
adapter->sm.ser_ctrl_st = MAC_AX_SER_CTRL_ERR;
|
PLTFM_MSG_ERR("[ERR]FW not handle haltH2C req\n");
|
ret = MACPOLLTO;
|
return ret;
|
}
|
|
if (sw == MAC_AX_FUNC_EN || sw == MAC_AX_FUNC_WO_RECVY_DIS ||
|
sw == MAC_AX_FUNC_WO_RECVY_EN)
|
return MACSUCCESS;
|
|
cnt = MAC_SER_STOP_DLY_CNT;
|
while (cnt) {
|
PLTFM_DELAY_US(MAC_SER_STOP_DLY_US);
|
val32 = MAC_REG_R32(R_AX_UDM0);
|
val32 = GET_FIELD(val32, FW_ST);
|
if (val32 != FW_ST_ERR_IN)
|
break;
|
cnt--;
|
}
|
|
if (!cnt) {
|
adapter->sm.ser_ctrl_st = MAC_AX_SER_CTRL_ERR;
|
PLTFM_MSG_ERR("[ERR]stop ser polling FW ST timeout\n");
|
return MACPOLLTO;
|
}
|
|
return ret;
|
}
|
|
u32 mac_chk_err_status(struct mac_ax_adapter *adapter, u8 *ser_status)
|
{
|
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
|
u32 cnt = MAC_SET_ERR_DLY_CNT;
|
u32 ret = MACSUCCESS;
|
enum mac_ax_err_info err;
|
|
PLTFM_MUTEX_LOCK(&adapter->hw_info->err_get_lock);
|
adapter->sm.l2_st = MAC_AX_L2_DIS;
|
|
while (--cnt) {
|
if (MAC_REG_R32(R_AX_HALT_C2H_CTRL))
|
break;
|
PLTFM_DELAY_US(MAC_SET_ERR_DLY_US);
|
}
|
if (!cnt) {
|
PLTFM_MSG_ERR("Polling FW err status fail\n");
|
ret = MACPOLLTO;
|
goto end;
|
}
|
|
err = (enum mac_ax_err_info)MAC_REG_R32(R_AX_HALT_C2H);
|
|
switch (err) {
|
case MAC_AX_ERR_L1_ERR_DMAC:
|
case MAC_AX_ERR_L0_PROMOTE_TO_L1:
|
*ser_status = MAC_AX_L1_TRUE;
|
break;
|
default:
|
*ser_status = MAC_AX_L1_FALSE;
|
break;
|
}
|
|
end:
|
adapter->sm.l2_st = MAC_AX_L2_EN;
|
PLTFM_MUTEX_UNLOCK(&adapter->hw_info->err_get_lock);
|
return ret;
|
}
|
|
u32 mac_set_l0_dbg_mode(struct mac_ax_adapter *adapter)
|
{
|
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
|
u32 ret;
|
u32 val32;
|
u32 cnt = MAC_SET_ERR_DLY_CNT;
|
|
MAC_REG_W32(R_AX_HALT_H2C, MAC_AX_L0_DBG_MODE);
|
val32 = MAC_REG_R32(R_AX_HALT_H2C_CTRL) | B_AX_HALT_H2C_TRIGGER;
|
MAC_REG_W32(R_AX_HALT_H2C_CTRL, val32);
|
while (--cnt) {
|
if (!(MAC_REG_R32(R_AX_HALT_H2C_CTRL)))
|
break;
|
PLTFM_DELAY_US(MAC_SET_ERR_DLY_US);
|
}
|
if (!cnt) {
|
PLTFM_MSG_ERR("Polling FW err status fail\n");
|
ret = MACPOLLTO;
|
return ret;
|
}
|
|
return MACSUCCESS;
|
}
|
|
u32 mac_set_l1_dbg_mode(struct mac_ax_adapter *adapter)
|
{
|
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
|
u32 ret;
|
u32 val32;
|
u32 cnt = MAC_SET_ERR_DLY_CNT;
|
|
MAC_REG_W32(R_AX_HALT_H2C, MAC_AX_L1_DBG_MODE);
|
val32 = MAC_REG_R32(R_AX_HALT_H2C_CTRL) | B_AX_HALT_H2C_TRIGGER;
|
MAC_REG_W32(R_AX_HALT_H2C_CTRL, val32);
|
while (--cnt) {
|
if (!(MAC_REG_R32(R_AX_HALT_H2C_CTRL)))
|
break;
|
PLTFM_DELAY_US(MAC_SET_ERR_DLY_US);
|
}
|
if (!cnt) {
|
PLTFM_MSG_ERR("Polling FW err status fail\n");
|
ret = MACPOLLTO;
|
return ret;
|
}
|
|
return MACSUCCESS;
|
}
|
|
u32 mac_reset_dbg_mode(struct mac_ax_adapter *adapter)
|
{
|
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
|
u32 ret;
|
u32 val32;
|
u32 cnt = MAC_SET_ERR_DLY_CNT;
|
|
MAC_REG_W32(R_BE_HALT_H2C, MAC_AX_RST_DBG_MODE);
|
val32 = MAC_REG_R32(R_BE_HALT_H2C_CTRL) | B_BE_HALT_H2C_TRIGGER;
|
MAC_REG_W32(R_BE_HALT_H2C_CTRL, val32);
|
while (--cnt) {
|
if (!(MAC_REG_R32(R_BE_HALT_C2H_CTRL)))
|
break;
|
PLTFM_DELAY_US(MAC_SET_ERR_DLY_US);
|
}
|
if (!cnt) {
|
PLTFM_MSG_ERR("Polling FW err status fail\n");
|
ret = MACPOLLTO;
|
return ret;
|
}
|
|
return MACSUCCESS;
|
}
|
|
u32 mac_dump_ser_cnt(struct mac_ax_adapter *adapter, struct mac_ser_status *status)
|
{
|
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
|
u32 val32;
|
|
val32 = MAC_REG_R32(R_AX_SER_DBG_INFO);
|
status->l0_cnt = GET_FIELD(val32, B_AX_SER_L0_COUNTER);
|
status->l1_cnt = GET_FIELD(val32, B_AX_SER_L1_COUNTER);
|
status->l0_pro_event = GET_FIELD(val32, B_AX_SER_L0_PROMOTE_L1_EVENT);
|
status->rmac_ppdu_hang_cnt = GET_FIELD(val32, B_AX_RMAC_PPDU_HANG_CNT);
|
|
return MACSUCCESS;
|
}
|
|
static void dump_cmac_cr(struct mac_ax_adapter *adapter, u8 band)
|
{
|
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
|
u32 base_addr, max_addr, i;
|
u32 ret;
|
|
ret = check_mac_en(adapter, band, MAC_AX_CMAC_SEL);
|
if (ret != MACSUCCESS)
|
return;
|
|
PLTFM_MSG_ERR("Dump CMAC band %d\n", band);
|
PLTFM_MSG_ERR("CMAC common\n");
|
base_addr = (band == 0) ? CMAC_AX_COMMON_BASE_ADDR : CMAC_AX_COMMON_BASE_ADDR_C1;
|
max_addr = CMAC_AX_COMMON_MAX_ADDR;
|
for (i = 0x0; i <= max_addr; i += 4)
|
PLTFM_MSG_ERR("0x186%05x = 0x%08x\n", base_addr + i, MAC_REG_R32(base_addr + i));
|
|
PLTFM_MSG_ERR("Scheduler\n");
|
base_addr = (band == 0) ? CMAC_AX_SCH_BASE_ADDR : CMAC_AX_SCH_BASE_ADDR_C1;
|
max_addr = CMAC_AX_SCH_MAX_ADDR;
|
for (i = 0x0; i <= max_addr; i += 4)
|
PLTFM_MSG_ERR("0x186%05x = 0x%08x\n", base_addr + i, MAC_REG_R32(base_addr + i));
|
|
PLTFM_MSG_ERR("PTCL\n");
|
base_addr = (band == 0) ? CMAC_AX_PTCL_BASE_ADDR : CMAC_AX_PTCL_BASE_ADDR_C1;
|
max_addr = CMAC_AX_PTCL_MAX_ADDR;
|
for (i = 0x0; i <= max_addr; i += 4)
|
PLTFM_MSG_ERR("0x186%05x = 0x%08x\n", base_addr + i, MAC_REG_R32(base_addr + i));
|
|
PLTFM_MSG_ERR("CDMA\n");
|
base_addr = (band == 0) ? CMAC_AX_CDMA_BASE_ADDR : CMAC_AX_CDMA_BASE_ADDR_C1;
|
max_addr = CMAC_AX_CDMA_MAX_ADDR;
|
for (i = 0x0; i <= max_addr; i += 4)
|
PLTFM_MSG_ERR("0x186%05x = 0x%08x\n", base_addr + i, MAC_REG_R32(base_addr + i));
|
|
PLTFM_MSG_ERR("TMAC\n");
|
base_addr = (band == 0) ? CMAC_AX_TMAC_BASE_ADDR : CMAC_AX_TMAC_BASE_ADDR_C1;
|
max_addr = CMAC_AX_TMAC_MAX_ADDR;
|
for (i = 0x0; i <= max_addr; i += 4)
|
PLTFM_MSG_ERR("0x186%05x = 0x%08x\n", base_addr + i, MAC_REG_R32(base_addr + i));
|
|
PLTFM_MSG_ERR("TRXPTCL\n");
|
base_addr = (band == 0) ? CMAC_AX_TRXPTCL_BASE_ADDR : CMAC_AX_TRXPTCL_BASE_ADDR_C1;
|
max_addr = CMAC_AX_TRXPTCL_MAX_ADDR;
|
for (i = 0x0; i <= max_addr; i += 4)
|
PLTFM_MSG_ERR("0x186%05x = 0x%08x\n", base_addr + i, MAC_REG_R32(base_addr + i));
|
|
PLTFM_MSG_ERR("RMAC\n");
|
base_addr = (band == 0) ? CMAC_AX_RMAC_BASE_ADDR : CMAC_AX_RMAC_BASE_ADDR_C1;
|
max_addr = CMAC_AX_RMAC_MAX_ADDR;
|
for (i = 0x0; i <= max_addr; i += 4)
|
PLTFM_MSG_ERR("0x186%05x = 0x%08x\n", base_addr + i, MAC_REG_R32(base_addr + i));
|
|
PLTFM_MSG_ERR("PWR\n");
|
base_addr = (band == 0) ? CMAC_AX_PWR_BASE_ADDR : CMAC_AX_PWR_BASE_ADDR_C1;
|
max_addr = CMAC_AX_PWR_MAX_ADDR;
|
for (i = 0x0; i <= max_addr; i += 4)
|
PLTFM_MSG_ERR("0x186%05x = 0x%08x\n", base_addr + i, MAC_REG_R32(base_addr + i));
|
|
PLTFM_MSG_ERR("BTCOEX\n");
|
base_addr = (band == 0) ? CMAC_AX_BTCOEX_BASE_ADDR : CMAC_AX_BTCOEX_BASE_ADDR_C1;
|
max_addr = CMAC_AX_BTCOEX_MAX_ADDR;
|
for (i = 0x0; i <= max_addr; i += 4)
|
PLTFM_MSG_ERR("0x186%05x = 0x%08x\n", base_addr + i, MAC_REG_R32(base_addr + i));
|
}
|
|
static void dump_dmac_cr(struct mac_ax_adapter *adapter)
|
{
|
struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
|
u32 base_addr, max_addr, i;
|
|
PLTFM_MSG_ERR("Dump DMAC\n");
|
PLTFM_MSG_ERR("TOP_OFF\n");
|
base_addr = DMAC_AX_TOP_OFF_BASE_ADDR;
|
max_addr = DMAC_AX_TOP_OFF_MAX_ADDR;
|
for (i = 0x0; i <= max_addr; i += 4)
|
PLTFM_MSG_ERR("0x1860%04x = 0x%08x\n", base_addr + i, MAC_REG_R32(base_addr + i));
|
|
PLTFM_MSG_ERR("WL_PON\n");
|
base_addr = DMAC_AX_WL_PON_BASE_ADDR;
|
max_addr = DMAC_AX_WL_PON_MAX_ADDR;
|
for (i = 0x0; i <= max_addr; i += 4)
|
PLTFM_MSG_ERR("0x1860%04x = 0x%08x\n", base_addr + i, MAC_REG_R32(base_addr + i));
|
|
PLTFM_MSG_ERR("Common\n");
|
base_addr = DMAC_AX_COMMON_BASE_ADDR;
|
max_addr = DMAC_AX_COMMON_MAX_ADDR;
|
for (i = 0x0; i <= max_addr; i += 4)
|
PLTFM_MSG_ERR("0x1860%04x = 0x%08x\n", base_addr + i, MAC_REG_R32(base_addr + i));
|
|
PLTFM_MSG_ERR("Dispatcher\n");
|
base_addr = DMAC_AX_DISPATCHER_BASE_ADDR;
|
max_addr = DMAC_AX_DISPATCHER_MAX_ADDR;
|
for (i = 0x0; i <= max_addr; i += 4)
|
PLTFM_MSG_ERR("0x1860%04x = 0x%08x\n", base_addr + i, MAC_REG_R32(base_addr + i));
|
|
PLTFM_MSG_ERR("WDE\n");
|
base_addr = DMAC_AX_WDE_BASE_ADDR;
|
max_addr = DMAC_AX_WDE_MAX_ADDR;
|
for (i = 0x0; i <= max_addr; i += 4)
|
PLTFM_MSG_ERR("0x1860%04x = 0x%08x\n", base_addr + i, MAC_REG_R32(base_addr + i));
|
|
PLTFM_MSG_ERR("PLE\n");
|
base_addr = DMAC_AX_PLE_BASE_ADDR;
|
max_addr = DMAC_AX_PLE_MAX_ADDR;
|
for (i = 0x0; i <= max_addr; i += 4)
|
PLTFM_MSG_ERR("0x1860%04x = 0x%08x\n", base_addr + i, MAC_REG_R32(base_addr + i));
|
|
PLTFM_MSG_ERR("WDRLS\n");
|
base_addr = DMAC_AX_WDRLS_BASE_ADDR;
|
max_addr = DMAC_AX_WDRLS_MAX_ADDR;
|
for (i = 0x0; i <= max_addr; i += 4)
|
PLTFM_MSG_ERR("0x1860%04x = 0x%08x\n", base_addr + i, MAC_REG_R32(base_addr + i));
|
|
PLTFM_MSG_ERR("BBRPT\n");
|
base_addr = DMAC_AX_BBRPT_BASE_ADDR;
|
max_addr = DMAC_AX_BBRPT_MAX_ADDR;
|
for (i = 0x0; i <= max_addr; i += 4)
|
PLTFM_MSG_ERR("0x1860%04x = 0x%08x\n", base_addr + i, MAC_REG_R32(base_addr + i));
|
|
PLTFM_MSG_ERR("CPUIO\n");
|
base_addr = DMAC_AX_CPUIO_BASE_ADDR;
|
max_addr = DMAC_AX_CPUIO_MAX_ADDR;
|
for (i = 0x0; i <= max_addr; i += 4)
|
PLTFM_MSG_ERR("0x1860%04x = 0x%08x\n", base_addr + i, MAC_REG_R32(base_addr + i));
|
|
PLTFM_MSG_ERR("PLTIN\n");
|
base_addr = DMAC_AX_PKTIN_BASE_ADDR;
|
max_addr = DMAC_AX_PKTIN_MAX_ADDR;
|
for (i = 0x0; i <= max_addr; i += 4)
|
PLTFM_MSG_ERR("0x1860%04x = 0x%08x\n", base_addr + i, MAC_REG_R32(base_addr + i));
|
|
PLTFM_MSG_ERR("MPDU Processor\n");
|
base_addr = DMAC_AX_MPDU_BASE_ADDR;
|
max_addr = DMAC_AX_MPDU_MAX_ADDR;
|
for (i = 0x0; i <= max_addr; i += 4)
|
PLTFM_MSG_ERR("0x1860%04x = 0x%08x\n", base_addr + i, MAC_REG_R32(base_addr + i));
|
|
PLTFM_MSG_ERR("SEC ENG\n");
|
base_addr = DMAC_AX_SEC_BASE_ADDR;
|
max_addr = DMAC_AX_SEC_MAX_ADDR;
|
for (i = 0x0; i <= max_addr; i += 4)
|
PLTFM_MSG_ERR("0x1860%04x = 0x%08x\n", base_addr + i, MAC_REG_R32(base_addr + i));
|
|
PLTFM_MSG_ERR("STA scheduler\n");
|
base_addr = DMAC_AX_SS_BASE_ADDR;
|
max_addr = DMAC_AX_SS_MAX_ADDR;
|
for (i = 0x0; i <= max_addr; i += 4)
|
PLTFM_MSG_ERR("0x1860%04x = 0x%08x\n", base_addr + i, MAC_REG_R32(base_addr + i));
|
|
PLTFM_MSG_ERR("Tx packet control\n");
|
base_addr = DMAC_AX_TXPKTCTL_BASE_ADDR;
|
max_addr = DMAC_AX_TXPKTCTL_MAX_ADDR;
|
for (i = 0x0; i <= max_addr; i += 4)
|
PLTFM_MSG_ERR("0x1860%04x = 0x%08x\n", base_addr + i, MAC_REG_R32(base_addr + i));
|
|
PLTFM_MSG_ERR("HCI Common\n");
|
base_addr = DMAC_AX_HCI_BASE_ADDR;
|
max_addr = DMAC_AX_HCI_MAX_ADDR;
|
for (i = 0x0; i <= max_addr; i += 4)
|
PLTFM_MSG_ERR("0x1860%04x = 0x%08x\n", base_addr + i, MAC_REG_R32(base_addr + i));
|
}
|
