/** @file */
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/******************************************************************************
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*
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* Copyright(c) 2019 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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******************************************************************************/
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#ifndef _MAC_AX_PCIE_H_
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#define _MAC_AX_PCIE_H_
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#include "../type.h"
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#include "../pcie_reg.h"
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#include "../mac_ax.h"
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/*--------------------Define -------------------------------------------*/
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#define INTF_INTGRA_MINREF_V1 90
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#define INTF_INTGRA_HOSTREF_V1 100
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#define GET_PCIE_FUNC_STUS(val, mask) (((val) & (mask)) ? \
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MAC_AX_PCIE_ENABLE : MAC_AX_PCIE_DISABLE)
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#define PCIE_POLL_IO_IDLE_CNT 100
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#define PCIE_POLL_IO_IDLE_DLY_US 10
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#define PCIE_POLL_DMACH_IDLE_CNT 100
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#define PCIE_POLL_DMACH_IDLE_DLY_US 10
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#define PCIE_POLL_SPEED_CHANGE_CNT 500
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#define PCIE_POLL_BDRAM_RST_CNT 10000
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#define PCIE_POLL_BDRAM_RST_DLY_US 50
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#define PCIE_POLL_AUTOK_CNT 1000
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#define PCIE_POLL_AUTOK_DLY_US 50
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#define MIO_ADDR_PAGE_SH 8
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#define MIO_WRITE_BYTE_ALL 0xF
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#define MIO_4BYTE_ALIGN 4
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#define MIO_SYNC_CNT 1000
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#define MIO_SYNC_DLY 1
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#define DBI_ADDR_MASK 0xFFC
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#define DBI_ADDR_2LSB_MASK 0x3
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#define DBI_WEN_DW 0xF
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#define DBI_WEN_B 1
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#define DBI_DLY_CNT 20
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#define DBI_DLY_US 10
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#define MDIO_ADDR_PG1 0x20
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#define MDIO_DLY_CNT 20
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#define MDIO_DLY_US 10
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#define BDRAM_SIDX_MSK 0x1f
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#define BDRAM_MAX_MSK 0x1f00
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#define BDRAM_MIN_MSK 0x1f0000
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#define MDIO_PG0_G1 0
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#define MDIO_PG1_G1 1
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#define MDIO_PG0_G2 2
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#define MDIO_PG1_G2 3
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#define BD_NORM_SIZE 12
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#define BD_TRUNC_SIZE 8
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#define RXBD_SEP_NORM_SIZE 20
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#define RXBD_SEP_TRUNC_OLD_SIZE 12
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#define RXBD_SEP_TRUNC_NEW_SIZE 16
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#define BD_MAX_NUM 0x3FF
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#define BD_IDX_INVALID 0xFFFF
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#define TXBD_BYTE_ALIGN 8
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#define RXBD_BYTE_ALIGN 4
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#define CMAC_CLK_ALLEN 0xFFFFFFFF
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#define PC_POWER_UP 1
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#define PC_POWER_DOWN 0
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#define BIT_WAKE_CTRL BIT5
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#define PCIE_DEFAULT_AGG_NUM 0x40
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#define PCIE_8852A_AGG_NUM 0x40 // temp setting for Drv request
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#define PCIE_8852B_AGG_NUM 0x40 // temp setting for Drv request
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#define PCIE_8852C_AGG_NUM 0x40 // temp setting for Drv request
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#define PCIE_8192XB_AGG_NUM 0x100
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#define PCIE_8851B_AGG_NUM 0x40
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#define PCIE_1115E_AGG_NUM 0x100
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#define PCIE_8851E_AGG_NUM 0x40 // temp setting for Drv request
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#define PCIE_8852D_AGG_NUM 0x40 // temp setting for Drv request
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#define PCIE_8852BT_AGG_NUM 0x40
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#define PCIE_AUTOK_DIV_2048 0x0
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#define PCIE_AUTOK_MGN 0x8
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#define PCIE_AUTOK_MGN_2048 64
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#define PCIE_AUTOK_UD_CNT 30
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#define PCIE_DPHY_DLY_0 0x0
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#define PCIE_DPHY_DLY_25US 0x1
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#define PCIE_AUTOK_4 0x3
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#define PROC_ID_LIST_NUM 2
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#define BASE_BOARD_ID_SHORT_LIST_NUM 28
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#define PROC_LONG_DLY 1
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#define PROC_SHORT_DLY 0
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#define PCIE_TP_THOLD 100
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#define HAXIDMA_SYNC_TX_CH_NUM 6
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#define HAXIDMA_SYNC_RX_CH_NUM 2
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#define HW_BD_IDX_MSK 0xFFFF
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#define HW_BD_IDX_SH 16
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#define HOST_BD_IDX_MSK 0xFFFF
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#define HOST_BD_IDX_SH 0
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#define C_WOW_LDO_ID_LIST_NUM 1
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#define C_WOW_LDO_ID_MSK 0xFFFF
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/*--------------------Define MACRO--------------------------------------*/
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#define EFUSE_2BYTES 2
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#define FIX_WAKE_EFUSE_OFFSET 0x74
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#define FIX_WAKE_EFUSE_BIT BIT5
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#define EFUSE_AVAIL_ENOUGH 8
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#define EFUSE_NOT_BURN_MASK 0xFF
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/*--------------------Define Enum---------------------------------------*/
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enum pcie_clkdly_hw {
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PCIE_CLKDLY_HW_0 = 0,
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PCIE_CLKDLY_HW_30US = 0x1,
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PCIE_CLKDLY_HW_50US = 0x2,
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PCIE_CLKDLY_HW_80US = 0x3,
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PCIE_CLKDLY_HW_100US = 0x4,
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PCIE_CLKDLY_HW_120US = 0x5,
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PCIE_CLKDLY_HW_150US = 0x6,
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PCIE_CLKDLY_HW_180US = 0x7,
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PCIE_CLKDLY_HW_200US = 0x8,
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PCIE_CLKDLY_HW_300US = 0x9,
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PCIE_CLKDLY_HW_400US = 0xA,
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PCIE_CLKDLY_HW_500US = 0xB,
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PCIE_CLKDLY_HW_1MS = 0xC,
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PCIE_CLKDLY_HW_3MS = 0xD,
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PCIE_CLKDLY_HW_5MS = 0xE,
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PCIE_CLKDLY_HW_10MS = 0xF
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};
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enum pcie_clkdly_hw_v1 {
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PCIE_CLKDLY_HW_V1_0 = 0,
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PCIE_CLKDLY_HW_V1_16US = 0x1,
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PCIE_CLKDLY_HW_V1_32US = 0x2,
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PCIE_CLKDLY_HW_V1_64US = 0x3,
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PCIE_CLKDLY_HW_V1_80US = 0x4,
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PCIE_CLKDLY_HW_V1_96US = 0x5,
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};
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enum pcie_l1dly_hw {
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PCIE_L1DLY_HW_16US = 4,
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PCIE_L1DLY_HW_32US = 5,
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PCIE_L1DLY_HW_64US = 6,
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PCIE_L1DLY_HW_INFI = 7
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};
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enum pcie_l0sdly_hw {
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PCIE_L0SDLY_HW_1US = 0,
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PCIE_L0SDLY_HW_2US = 1,
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PCIE_L0SDLY_HW_3US = 2,
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PCIE_L0SDLY_HW_4US = 3,
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PCIE_L0SDLY_HW_5US = 4,
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PCIE_L0SDLY_HW_6US = 5,
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PCIE_L0SDLY_HW_7US = 6
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};
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enum pcie_bd_ctrl_type {
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PCIE_BD_CTRL_DESC_L = 0,
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PCIE_BD_CTRL_DESC_H,
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PCIE_BD_CTRL_NUM,
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PCIE_BD_CTRL_IDX,
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PCIE_BD_CTRL_BDRAM,
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PCIE_BD_CTRL_LAST,
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PCIE_BD_CTRL_MAX = PCIE_BD_CTRL_LAST,
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PCIE_BD_CTRL_INVALID = PCIE_BD_CTRL_LAST,
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};
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/*--------------------Define Struct-------------------------------------*/
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struct txbd_ram {
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u8 sidx;
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u8 max;
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u8 min;
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};
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/**
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* @brief reg_read8_pcie
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*
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* @param *adapter
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* @param addr
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* @return Please Place Description here.
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* @retval u8
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*/
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u8 reg_read8_pcie(struct mac_ax_adapter *adapter, u32 addr);
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/**
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* @}
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* @}
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*/
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/**
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* @addtogroup HCI
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* @{
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* @addtogroup BasicIO
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* @{
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*/
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/**
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* @brief reg_write8_pcie
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*
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* @param *adapter
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* @param addr
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* @param val
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* @return Please Place Description here.
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* @retval void
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*/
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void reg_write8_pcie(struct mac_ax_adapter *adapter, u32 addr, u8 val);
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/**
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* @}
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* @}
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*/
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/**
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* @addtogroup HCI
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* @{
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* @addtogroup BasicIO
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* @{
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*/
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/**
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* @brief reg_read16_pcie
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*
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* @param *adapter
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* @param addr
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* @return Please Place Description here.
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* @retval u16
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*/
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u16 reg_read16_pcie(struct mac_ax_adapter *adapter, u32 addr);
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/**
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* @}
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* @}
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*/
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/**
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* @addtogroup HCI
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* @{
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* @addtogroup BasicIO
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* @{
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*/
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/**
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* @brief reg_write16_pcie
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*
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* @param *adapter
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* @param addr
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* @param val
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* @return Please Place Description here.
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* @retval void
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*/
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void reg_write16_pcie(struct mac_ax_adapter *adapter, u32 addr, u16 val);
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/**
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* @}
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* @}
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*/
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/**
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* @addtogroup HCI
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* @{
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* @addtogroup BasicIO
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* @{
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*/
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/**
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* @brief reg_read32_pcie
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*
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* @param *adapter
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* @param addr
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* @return Please Place Description here.
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* @retval u32
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*/
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u32 reg_read32_pcie(struct mac_ax_adapter *adapter, u32 addr);
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/**
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* @}
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* @}
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*/
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/**
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* @addtogroup HCI
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* @{
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* @addtogroup BasicIO
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* @{
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*/
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/**
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* @brief reg_write32_pcie
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*
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* @param *adapter
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* @param addr
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* @param val
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* @return Please Place Description here.
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* @retval void
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*/
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void reg_write32_pcie(struct mac_ax_adapter *adapter, u32 addr, u32 val);
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/**
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* @}
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* @}
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*/
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/**
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* @addtogroup HCI
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* @{
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* @addtogroup PCIE
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* @{
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*/
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/**
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* @brief dbi_r8_pcie
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*
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* @param *adapter
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* @param addr
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* @param *val
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* @return Please Place Description here.
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* @retval u32
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*/
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u32 dbi_r8_pcie(struct mac_ax_adapter *adapter, u16 addr, u8 *val);
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/**
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* @}
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* @}
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*/
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/**
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* @addtogroup HCI
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* @{
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* @addtogroup PCIE
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* @{
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*/
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/**
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* @brief dbi_w8_pcie
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*
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* @param *adapter
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* @param addr
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* @param data
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* @return Please Place Description here.
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* @retval u32
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*/
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u32 dbi_w8_pcie(struct mac_ax_adapter *adapter, u16 addr, u8 data);
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/**
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* @}
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* @}
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*/
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/**
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* @addtogroup HCI
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* @{
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* @addtogroup PCIE
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* @{
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*/
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/**
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* @brief dbi_r32_pcie
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*
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* @param *adapter
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* @param addr
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* @param *val
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* @return Please Place Description here.
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* @retval u32
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*/
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u32 dbi_r32_pcie(struct mac_ax_adapter *adapter, u16 addr, u32 *val);
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/**
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* @}
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* @}
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*/
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/**
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* @addtogroup HCI
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* @{
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* @addtogroup PCIE
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* @{
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*/
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/**
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* @brief dbi_w32_pcie
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*
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* @param *adapter
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* @param addr
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* @param data
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* @return Please Place Description here.
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* @retval u32
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*/
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u32 dbi_w32_pcie(struct mac_ax_adapter *adapter, u16 addr, u32 data);
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/**
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* @}
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* @}
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*/
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/**
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* @addtogroup HCI
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* @{
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* @addtogroup PCIE
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* @{
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*/
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/**
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* @brief mdio_r16_pcie
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*
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* @param *adapter
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* @param addr
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* @param speed
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* @param *val
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* @return Please Place Description here.
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* @retval u32
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*/
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u32 mdio_r16_pcie(struct mac_ax_adapter *adapter, u8 addr, u8 speed, u16 *val);
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/**
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* @}
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* @}
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*/
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/**
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* @addtogroup HCI
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* @{
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* @addtogroup PCIE
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* @{
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*/
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/**
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* @brief mdio_w16_pcie
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*
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* @param *adapter
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* @param addr
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* @param data
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* @param speed
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* @return Please Place Description here.
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* @retval u32
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*/
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u32 mdio_w16_pcie(struct mac_ax_adapter *adapter, u8 addr, u16 data, u8 speed);
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/**
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* @}
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* @}
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*/
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/**
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* @addtogroup HCI
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* @{
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* @addtogroup PCIE
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* @{
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*/
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/**
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* @brief update_pcie_func_u32
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*
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* @param *val
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* @param bitmask
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* @param ctrl
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* @param def_ctrl
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* @return Please Place Description here.
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* @retval u32
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*/
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void update_pcie_func_u32(u32 *val, u32 bitmask,
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enum mac_ax_pcie_func_ctrl ctrl,
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enum mac_ax_pcie_func_ctrl def_ctrl);
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/**
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* @}
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* @}
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*/
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/**
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* @addtogroup HCI
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* @{
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* @addtogroup PCIE
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* @{
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*/
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/**
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* @brief update_pcie_func_u8
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*
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* @param *val
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* @param bitmask
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* @param ctrl
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* @param def_ctrl
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* @return Please Place Description here.
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* @retval u32
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*/
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void update_pcie_func_u8(u8 *val, u8 bitmask,
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enum mac_ax_pcie_func_ctrl ctrl,
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enum mac_ax_pcie_func_ctrl def_ctrl);
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/**
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* @}
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* @}
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*/
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/**
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* @addtogroup HCI
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* @{
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* @addtogroup PCIE
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* @{
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*/
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/**
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* @brief calc_avail_wptr
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*
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* @param rptr
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* @param wptr
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* @param bndy
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* @return Please Place Description here.
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* @retval u32
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*/
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u16 calc_avail_wptr(u16 rptr, u16 wptr, u16 bndy);
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/**
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* @}
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* @}
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*/
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/**
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* @addtogroup HCI
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* @{
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* @addtogroup PCIE
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* @{
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*/
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/**
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* @brief calc_avail_rptr
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*
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* @param rptr
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* @param wptr
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* @param bndy
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* @return Please Place Description here.
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* @retval u32
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*/
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u16 calc_avail_rptr(u16 rptr, u16 wptr, u16 bndy);
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/**
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* @}
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* @}
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*/
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/**
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* @addtogroup HCI
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* @{
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* @addtogroup PCIE
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* @{
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*/
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/**
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* @brief cfgspc_set_pcie
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*
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* @param *adapter
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* @param *param
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* @return Please Place Description here.
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* @retval u32
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*/
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u32 cfgspc_set_pcie(struct mac_ax_adapter *adapter,
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struct mac_ax_pcie_cfgspc_param *param);
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/**
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* @}
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* @}
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*/
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/**
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* @addtogroup HCI
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* @{
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* @addtogroup PCIE
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* @{
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*/
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/**
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* @brief ltr_set_pcie
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*
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* @param *adapter
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* @param *param
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* @return Please Place Description here.
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* @retval u32
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*/
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u32 ltr_set_pcie(struct mac_ax_adapter *adapter,
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struct mac_ax_pcie_ltr_param *param);
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/**
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* @}
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* @}
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*/
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/**
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* @addtogroup HCI
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* @{
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* @addtogroup PCIE
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* @{
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*/
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/**
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* @addtogroup HCI
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* @{
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* @addtogroup PCIE
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* @{
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*/
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/**
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* @brief clr_idx_all_pcie
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*
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* @param *adapter
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* @return Please Place Description here.
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* @retval u32
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*/
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u32 clr_idx_all_pcie(struct mac_ax_adapter *adapter);
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/**
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* @}
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* @}
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*/
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/**
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* @addtogroup HCI
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* @{
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* @addtogroup PCIE
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* @{
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*/
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/**
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* @brief ctrl_txhci_pcie
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*
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* @param *adapter
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* @param en
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* @return Please Place Description here.
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* @retval u32
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*/
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u32 ctrl_txhci_pcie(struct mac_ax_adapter *adapter, enum mac_ax_func_sw en);
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/**
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* @}
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* @}
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*/
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/**
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* @addtogroup HCI
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* @{
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* @addtogroup PCIE
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* @{
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*/
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/**
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* @brief ctrl_rxhci_pcie
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*
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* @param *adapter
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* @param en
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* @return Please Place Description here.
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* @retval u32
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*/
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u32 ctrl_rxhci_pcie(struct mac_ax_adapter *adapter, enum mac_ax_func_sw en);
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/**
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* @}
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* @}
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*/
|
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/**
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* @addtogroup HCI
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* @{
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* @addtogroup PCIE
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* @{
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*/
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/**
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* @brief ctrl_dma_io_pcie
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*
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* @param *adapter
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* @param en
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* @return Please Place Description here.
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* @retval u32
|
*/
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u32 ctrl_dma_io_pcie(struct mac_ax_adapter *adapter, enum mac_ax_func_sw en);
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/**
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* @}
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* @}
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*/
|
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/**
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* @addtogroup HCI
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* @{
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* @addtogroup PCIE
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* @{
|
*/
|
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/**
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* @brief pcie_pre_init
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*
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* @param *adapter
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* @param *param
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* @return Please Place Description here.
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* @retval u32
|
*/
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u32 pcie_pre_init(struct mac_ax_adapter *adapter, void *param);
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/**
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* @}
|
* @}
|
*/
|
|
/**
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* @addtogroup HCI
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* @{
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* @addtogroup PCIE
|
* @{
|
*/
|
|
/**
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* @brief pcie_init
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*
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* @param *adapter
|
* @param *param
|
* @return Please Place Description here.
|
* @retval u32
|
*/
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u32 pcie_init(struct mac_ax_adapter *adapter, void *param);
|
/**
|
* @}
|
* @}
|
*/
|
|
/**
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* @addtogroup HCI
|
* @{
|
* @addtogroup PCIE
|
* @{
|
*/
|
|
/**
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* @brief pcie_deinit
|
*
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* @param *adapter
|
* @param *param
|
* @return Please Place Description here.
|
* @retval u32
|
*/
|
u32 pcie_deinit(struct mac_ax_adapter *adapter, void *param);
|
/**
|
* @}
|
* @}
|
*/
|
|
/**
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* @addtogroup HCI
|
* @{
|
* @addtogroup PCIE
|
* @{
|
*/
|
|
/**
|
* @brief lv1rst_stop_dma_pcie
|
*
|
* @param *adapter
|
* @param val
|
* @return Please Place Description here.
|
* @retval u32
|
*/
|
u32 lv1rst_stop_dma_pcie(struct mac_ax_adapter *adapter, u8 val);
|
/**
|
* @}
|
* @}
|
*/
|
|
/**
|
* @addtogroup HCI
|
* @{
|
* @addtogroup PCIE
|
* @{
|
*/
|
|
/**
|
* @brief lv1rst_start_dma_pcie
|
*
|
* @param *adapter
|
* @param val
|
* @return Please Place Description here.
|
* @retval u32
|
*/
|
u32 lv1rst_start_dma_pcie(struct mac_ax_adapter *adapter, u8 val);
|
/**
|
* @}
|
* @}
|
*/
|
|
/**
|
* @addtogroup HCI
|
* @{
|
* @addtogroup PCIE
|
* @{
|
*/
|
|
/**
|
* @brief pcie_pwr_switch
|
*
|
* @param *vadapter
|
* @param pre_switch
|
* @param on
|
* @return Please Place Description here.
|
* @retval u32
|
*/
|
u32 pcie_pwr_switch(void *vadapter,
|
u8 pre_switch, u8 on);
|
/**
|
* @}
|
* @}
|
*/
|
|
/**
|
* @addtogroup HCI
|
* @{
|
* @addtogroup PCIE
|
* @{
|
*/
|
|
/**
|
* @brief set_pcie_wowlan
|
*
|
* @param *adapter
|
* @param w_c
|
* @return Please Place Description here.
|
* @retval u32
|
*/
|
u32 set_pcie_wowlan(struct mac_ax_adapter *adapter, enum mac_ax_wow_ctrl w_c);
|
/**
|
* @}
|
* @}
|
*/
|
|
/**
|
* @addtogroup HCI
|
* @{
|
* @addtogroup PCIE
|
* @{
|
*/
|
|
/**
|
* @brief set_pcie_l2_leave
|
*
|
* @param *adapter
|
* @param set
|
* @return Please Place Description here.
|
* @retval u32
|
*/
|
u32 set_pcie_l2_leave(struct mac_ax_adapter *adapter, u8 set);
|
/**
|
* @}
|
* @}
|
*/
|
|
/**
|
* @brief pcie_get_txagg_num
|
*
|
* @param *adapter
|
* @param band
|
* @return Please Place Description here.
|
* @retval u32
|
*/
|
u32 pcie_get_txagg_num(struct mac_ax_adapter *adapter, u8 band);
|
/**
|
* @}
|
* @}
|
*/
|
|
/**
|
* @addtogroup HCI
|
* @{
|
* @addtogroup PCIE
|
* @{
|
*/
|
|
/**
|
* @brief pcie_get_rx_state
|
*
|
* @param *adapter
|
* @return Please Place Description here.
|
* @retval u32
|
*/
|
u32 pcie_get_rx_state(struct mac_ax_adapter *adapter, u32 *val);
|
/**
|
* @}
|
* @}
|
*/
|
|
/**
|
* @addtogroup HCI
|
* @{
|
* @addtogroup PCIE
|
* @{
|
*/
|
|
/**
|
* @brief trigger_txdma_pcie
|
*
|
* @param *adapter
|
* @param *txbd_ring
|
* @param ch_idx
|
* @return Please Place Description here.
|
* @retval u32
|
*/
|
u32 trigger_txdma_pcie(struct mac_ax_adapter *adapter,
|
struct tx_base_desc *txbd_ring, u8 ch_idx);
|
/**
|
* @}
|
* @}
|
*/
|
|
/**
|
* @addtogroup HCI
|
* @{
|
* @addtogroup PCIE
|
* @{
|
*/
|
|
/**
|
* @brief notify_rxdone_pcie
|
*
|
* @param *adapter
|
* @param *rxbd
|
* @param ch
|
* @return Please Place Description here.
|
* @retval u32
|
*/
|
u32 notify_rxdone_pcie(struct mac_ax_adapter *adapter,
|
struct rx_base_desc *rxbd, u8 ch);
|
/**
|
* @}
|
* @}
|
*/
|
|
/**
|
* @addtogroup HCI
|
* @{
|
* @addtogroup PCIE
|
* @{
|
*/
|
|
/**
|
* @brief dbcc_hci_ctrl_pcie
|
*
|
* @param *adapter
|
* @param *info
|
* @return Please Place Description here.
|
* @retval u32
|
*/
|
u32 dbcc_hci_ctrl_pcie(struct mac_ax_adapter *adapter,
|
struct mac_ax_dbcc_hci_ctrl *info);
|
/**
|
* @}
|
* @}
|
*/
|
|
/**
|
* @brief pcie_autok_counter_avg
|
*
|
* @param *adapter
|
* @return Please Place Description here.
|
* @retval u32
|
*/
|
u32 pcie_autok_counter_avg(struct mac_ax_adapter *adapter);
|
/**
|
* @}
|
* @}
|
*/
|
|
#ifdef RTW_WKARD_GET_PROCESSOR_ID
|
/**
|
* @brief chk_proc_long_ldy
|
*
|
* @param *adapter
|
* @return Please Place Description here.
|
* @retval u32
|
*/
|
u32 chk_proc_long_ldy(struct mac_ax_adapter *adapter);
|
/**
|
* @}
|
* @}
|
*/
|
#endif
|
|
/**
|
* @addtogroup HCI
|
* @{
|
* @addtogroup PCIE
|
* @{
|
*/
|
|
/**
|
* @brief pcie_tp_adjust
|
*
|
* @param *adapter
|
* @param tp
|
* @return Please Place Description here.
|
* @retval u32
|
*/
|
u32 pcie_tp_adjust(struct mac_ax_adapter *adapter, struct mac_ax_tp_param tp);
|
/**
|
* @}
|
* @}
|
*/
|
|
/**
|
* @brief sync_trx_bd_idx_pcie
|
*
|
* @param *adapter
|
* @return Please Place Description here.
|
* @retval u32
|
*/
|
u32 sync_trx_bd_idx_pcie(struct mac_ax_adapter *adapter);
|
/**
|
* @}
|
* @}
|
*/
|
|
/**
|
* @brief ctrl_txdma_pcie
|
*
|
* @param *adapter
|
* @param opt
|
* @return Please Place Description here.
|
* @retval u32
|
*/
|
u32 ctrl_txdma_pcie(struct mac_ax_adapter* adapter, u8 opt);
|
/**
|
* @}
|
* @}
|
*/
|
|
/**
|
* @brief poll_txdma_idle_pcie
|
*
|
* @param *adapter
|
* @return Please Place Description here.
|
* @retval u32
|
*/
|
u32 poll_txdma_idle_pcie(struct mac_ax_adapter* adapter);
|
/**
|
* @}
|
* @}
|
*/
|
|
/**
|
* @brief clr_hci_trx_pcie
|
*
|
* @param *adapter
|
* @return Please Place Description here.
|
* @retval u32
|
*/
|
u32 clr_hci_trx_pcie(struct mac_ax_adapter* adapter);
|
/**
|
* @}
|
* @}
|
*/
|
|
u32 mac_read_pcie_cfg_spc(struct mac_ax_adapter *adapter, u16 addr, u32 *val);
|
|
#endif
|
