/******************************************************************************
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*
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* Copyright(c) 2019 - 2021 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#define _HAL_TX_C_
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#include "hal_headers.h"
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/**
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* this function will be used in read / write pointer mechanism and
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* return the number of available read pointer
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* @rptr: input, the read pointer
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* @wptr: input, the write pointer
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* @bndy: input, the boundary of read / write pointer mechanism
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*/
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u16 hal_calc_avail_rptr(u16 rptr, u16 wptr, u16 bndy)
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{
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u16 avail_rptr = 0;
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if (wptr >= rptr)
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avail_rptr = wptr - rptr;
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else if (rptr > wptr)
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avail_rptr = wptr + (bndy - rptr);
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return avail_rptr;
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}
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/**
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* this function will be used in read / write pointer mechanism and
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* return the number of available write pointer
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* @rptr: input, the read pointer
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* @wptr: input, the write pointer
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* @bndy: input, the boundary of read / write pointer mechanism
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*/
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u16 hal_calc_avail_wptr(u16 rptr, u16 wptr, u16 bndy)
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{
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u16 avail_wptr = 0;
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if (rptr > wptr)
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avail_wptr = rptr - wptr - 1;
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else if (wptr >= rptr)
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avail_wptr = rptr + (bndy - wptr) - 1;
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return avail_wptr;
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}
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enum rtw_hal_status
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rtw_hal_enable_hwamsdu(void *hal,
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u8 enable,
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u8 max_num,
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u8 en_single_amsdu,
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u8 en_last_amsdu_padding)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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return rtw_hal_mac_enable_hwamsdu(hal_info, enable, max_num, en_single_amsdu, en_last_amsdu_padding);
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}
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/**
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* rtw_hal_tx_chnl_mapping - query hw tx dma channel mapping to the sw xmit ring
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* identified by macid, tid and band
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* @hal: see struct hal_info_t
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* @macid: input target macid is 0 ~ 127
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* @cat: input target packet category, see enum rtw_phl_ring_cat
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* @band: input target band, 0 for band 0 / 1 for band 1
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*
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* returns the mapping hw tx dma channel
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*/
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u8 rtw_hal_tx_chnl_mapping(void *hal, u16 macid,
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enum rtw_phl_ring_cat cat, u8 band)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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struct hal_trx_ops *trx_ops = hal_info->trx_ops;
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u8 tx_chnl = 0;
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tx_chnl = trx_ops->map_hw_tx_chnl(hal_info, macid, cat, band);
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return tx_chnl;
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}
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/**
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* rtw_hal_get_fwcmd_queue_idx - get idx of fwcmd queue
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* @hal: see struct hal_info_t
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*
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* returns u8 idx of fwcmd queue
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*/
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u8 rtw_hal_get_fwcmd_queue_idx(void *hal)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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struct hal_trx_ops *trx_ops = hal_info->trx_ops;
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return trx_ops->get_fwcmd_queue_idx();
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}
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void rtw_hal_clear_rwptr(void *hal)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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if (RTW_HAL_STATUS_SUCCESS != rtw_hal_mac_clear_rwptr(hal_info))
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PHL_ERR("%s failure \n", __func__);
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}
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void rtw_hal_cfg_txhci(void *hal, u8 en)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "%s : enable %d.\n", __func__, en);
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if (RTW_HAL_STATUS_SUCCESS != rtw_hal_mac_cfg_txhci(hal_info, en))
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PHL_ERR("%s failure \n", __func__);
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}
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enum rtw_hal_status rtw_hal_chk_allq_empty(void *hal, u8 *empty)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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FUNCIN();
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return rtw_hal_mac_chk_allq_empty(hal_info, empty);
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}
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enum rtw_hal_status rtw_hal_set_resp_ack_chk_cca(void *hal, u8 band, u8 en)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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FUNCIN();
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return rtw_hal_mac_set_resp_ack_chk_cca(hal_info, band, en);
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}
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enum rtw_hal_status rtw_hal_sifs_chk_cca_en(void *hal, u8 band, u8 en)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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FUNCIN();
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return rtw_hal_mac_sifs_chk_cca_en(hal_info, band, en);
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}
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enum rtw_hal_status
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rtw_hal_fill_txdesc(void *hal,
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struct rtw_xmit_req *treq,
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u8 *wd_buf,
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u32 *wd_len)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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return rtw_hal_mac_fill_txdesc(hal_info->mac, treq, wd_buf, wd_len);
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}
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enum rtw_hal_status
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rtw_hal_get_hwseq(void *hal, u16 macid, u8 ref_sel, u8 ssn_sel, u16 *hw_seq)
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{
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enum rtw_hal_status sts = RTW_HAL_STATUS_SUCCESS;
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sts = rtw_hal_mac_get_hwseq(hal, macid, ref_sel, ssn_sel, hw_seq);
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return sts;
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}
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enum rtw_hal_status
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rtw_hal_poll_hw_tx_done(void *hal)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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enum rtw_hal_status sts = RTW_HAL_STATUS_SUCCESS;
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sts = rtw_hal_mac_poll_hw_tx_done(hal_info);
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return sts;
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}
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enum rtw_hal_status
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rtw_hal_hw_tx_resume(void *hal)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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enum rtw_hal_status sts = RTW_HAL_STATUS_SUCCESS;
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sts = rtw_hal_mac_hw_tx_resume(hal_info);
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return sts;
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}
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u8 rtw_hal_poll_txdma_idle(void *hal)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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enum rtw_hal_status ret = RTW_HAL_STATUS_SUCCESS;
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FUNCIN();
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ret = rtw_hal_mac_poll_txdma_idle(hal_info);
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return (ret == RTW_HAL_STATUS_SUCCESS) ? true : false;
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}
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#ifdef CONFIG_PCI_HCI
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/**
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* rtw_hal_convert_qsel_to_tid - convert qsel to tid value
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* @hal: see struct hal_info_t
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* @qsel: HW queue selection
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*
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* returns enum RTW_HAL_STATUS
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*/
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u8 rtw_hal_convert_qsel_to_tid(void *hal, u8 qsel_id, u8 tid_indic)
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{
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enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS;
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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struct hal_trx_ops *trx_ops = hal_info->trx_ops;
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hstatus = trx_ops->qsel_to_tid(hal_info, qsel_id, tid_indic);
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return hstatus;
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}
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/**
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* rtw_hal_tx_res_query - query current HW tx resource with specifc dma channel
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* @hal: see struct hal_info_t
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* @dma_ch: the target dma channel
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* @host_idx: current host index of this channel
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* @hw_idx: current hw index of this channel
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*
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* this function returns the number of available tx resource
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* NOTE, input host_idx and hw_idx ptr shall NOT be NULL
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*/
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u16 rtw_hal_tx_res_query(void *hal, u8 dma_ch, u16 *host_idx, u16 *hw_idx)
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{
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enum rtw_hal_status sts = RTW_HAL_STATUS_FAILURE;
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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u16 res_num = 0;
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sts = rtw_hal_mac_tx_res_query(hal_info, dma_ch, host_idx, hw_idx,
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&res_num);
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return res_num;
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}
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enum phl_band_idx rtw_hal_query_txch_hwband(void *hal, u8 dma_ch)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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struct hal_trx_ops *trx_ops = hal_info->trx_ops;
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enum phl_band_idx band_idx = HW_BAND_0;
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band_idx = trx_ops->query_txch_hwband(dma_ch);
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return band_idx;
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}
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/**
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* rtw_hal_query_txch_num - query total hw tx dma channels number
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*
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* returns the number of hw tx dma channel
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*/
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u8 rtw_hal_query_txch_num(void *hal)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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struct hal_trx_ops *trx_ops = hal_info->trx_ops;
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u8 ch_num = 0;
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ch_num = trx_ops->query_txch_num();
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return ch_num;
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}
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enum rtw_hal_status rtw_hal_trx_init(void *hal, u8 *txbd_buf, u8 *rxbd_buf)
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{
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enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS;
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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struct hal_trx_ops *trx_ops = hal_info->trx_ops;
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hstatus = trx_ops->init(hal_info, txbd_buf, rxbd_buf);
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return hstatus;
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}
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void rtw_hal_trx_deinit(void *hal)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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struct hal_trx_ops *trx_ops = hal_info->trx_ops;
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trx_ops->deinit(hal_info);
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}
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/**
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* rtw_hal_update_wd_page - update wd page for xmit packet
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* @hal: see struct hal_info_t
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* @phl_pkt_req: packet xmit request from phl, see struct rtw_phl_pkt_req
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*
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* returns enum RTW_HAL_STATUS
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*/
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enum rtw_hal_status rtw_hal_update_wd_page(void *hal, void *phl_pkt_req)
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{
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enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS;
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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struct hal_trx_ops *trx_ops = hal_info->trx_ops;
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hstatus = trx_ops->update_wd(hal_info, phl_pkt_req);
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return hstatus;
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}
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/**
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* rtw_hal_update_txbd - update tx bd for xmit packet
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* @hal: see struct hal_info_t
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* @wd: buffer pointer of wd page to fill in txbd
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*
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* returns enum RTW_HAL_STATUS
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* NOTE, this function is PCIe specific function
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*/
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enum rtw_hal_status rtw_hal_update_txbd(void *hal, void *txbd, void *wd, u8 dma_ch, u16 wd_num)
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{
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enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS;
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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struct hal_trx_ops *trx_ops = hal_info->trx_ops;
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hstatus = trx_ops->update_txbd(hal, txbd, wd, dma_ch, wd_num);
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return hstatus;
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}
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/**
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* rtw_hal_update_trigger_txstart - trigger hw to start tx
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* @hal: see struct hal_info_t
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* @txbd: the target txbd to update
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* @dma_ch: the dma channel index of this txbd_ring
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*
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* returns enum RTW_HAL_STATUS
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*/
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enum rtw_hal_status
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rtw_hal_trigger_txstart(void *hal, struct tx_base_desc *txbd, u8 dma_ch)
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{
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enum rtw_hal_status sts = RTW_HAL_STATUS_FAILURE;
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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sts = rtw_hal_mac_trigger_txstart(hal_info, txbd, dma_ch);
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if (sts != RTW_HAL_STATUS_SUCCESS) {
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PHL_TRACE(COMP_PHL_XMIT, _PHL_INFO_, "%s : trigger tx start fail!\n",
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__func__);
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}
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return sts;
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}
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#endif /*CONFIG_PCI_HCI*/
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#ifdef CONFIG_USB_HCI
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enum rtw_hal_status rtw_hal_trx_init(void *hal)
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{
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enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS;
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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struct hal_trx_ops *trx_ops = hal_info->trx_ops;
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hstatus = trx_ops->init(hal_info);
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return hstatus;
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}
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void rtw_hal_trx_deinit(void *hal)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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struct hal_trx_ops *trx_ops = hal_info->trx_ops;
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trx_ops->deinit(hal_info);
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}
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u8 rtw_hal_get_bulkout_id(void *hal, u8 dma_ch, u8 mode)
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{
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enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS;
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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struct hal_trx_ops *trx_ops = hal_info->trx_ops;
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hstatus = trx_ops->get_bulkout_id(hal, dma_ch, mode);
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return hstatus;
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}
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enum rtw_hal_status
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rtw_hal_usb_tx_agg_cfg(void *hal, u8* wd_buf, u8 agg_num)
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{
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enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS;
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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struct hal_trx_ops *trx_ops = hal_info->trx_ops;
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hstatus = trx_ops->usb_tx_agg_cfg(hal, wd_buf, agg_num);
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return hstatus;
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}
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u8 rtw_hal_get_max_bulkout_wd_num(void *hal)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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struct hal_trx_ops *trx_ops = hal_info->trx_ops;
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return trx_ops->get_max_bulkout_wd_num(hal);
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}
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u16 rtw_hal_get_max_dma_txagg_msk(void *hal)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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return hal_mac_usb_get_max_dma_txagg_msk(hal_info);
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}
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u32 rtw_hal_get_wd_len(void *hal,
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struct rtw_xmit_req *tx_req)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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struct hal_trx_ops *trx_ops = hal_info->trx_ops;
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u32 wd_len = 0;
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wd_len = trx_ops->hal_get_wd_len(hal_info, tx_req);
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return wd_len;
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}
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#endif
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#ifdef CONFIG_SDIO_HCI
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void rtw_hal_sdio_tx_cfg(void *hal)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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rtw_hal_mac_sdio_tx_cfg(hal_info->hal_com);
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}
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enum rtw_hal_status rtw_hal_sdio_tx(void *hal, u8 dma_ch, u8 *buf, u32 buf_len,
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u8 agg_count, u16 *pkt_len, u8 *wp_offset)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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u32 txaddr;
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u32 txlen;
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bool ready;
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ready = rtw_hal_mac_sdio_check_tx_allow(hal_info->hal_com, dma_ch,
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buf, buf_len, agg_count,
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pkt_len, wp_offset, &txaddr,
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&txlen);
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if (!ready)
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return RTW_HAL_STATUS_RESOURCE;
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hal_sdio_cmd53_w(hal_info->hal_com, txaddr, txlen, buf);
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return RTW_HAL_STATUS_SUCCESS;
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}
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#endif /* CONFIG_SDIO_HCI */
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/**
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* rtw_hal_fill_wd - fill wd-info and wd-boddy for xmit packet
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* @hal: see struct hal_info_t
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* @phl_pkt_req: packet xmit request from phl, see struct rtw_phl_pkt_req
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*
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* returns enum RTW_HAL_STATUS
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*/
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enum rtw_hal_status rtw_hal_fill_wd(void *hal,
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struct rtw_xmit_req *tx_req,
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u8 *wd_buf, u32 *wd_len)
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{
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enum rtw_hal_status hstatus = RTW_HAL_STATUS_SUCCESS;
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
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struct hal_trx_ops *trx_ops = hal_info->trx_ops;
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#endif
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#ifdef RTW_WKARD_CCX_RPT_LIMIT_CTRL
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if (tx_req->mdata.spe_rpt) {
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if (tx_req->mdata.data_tx_cnt_lmt_en)
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hal_info->hal_com->spe_pkt_cnt_lmt = tx_req->mdata.data_tx_cnt_lmt;
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}
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#endif
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#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
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if (trx_ops->hal_fill_wd)
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hstatus = trx_ops->hal_fill_wd(hal_info, tx_req, wd_buf, wd_len);
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else
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#endif
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hstatus = rtw_hal_mac_fill_txdesc(hal_info->mac, tx_req, wd_buf, wd_len);
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return hstatus;
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}
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enum rtw_hal_status rtw_hal_cfg_hw_cts2self(void *hal, u8 band_sel, u8 enable,
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u8 non_sec_thr, u8 sec_thr)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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struct mac_ax_cts2self_cfg mac_hw_cts_cfg;
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enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
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if (enable)
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mac_hw_cts_cfg.threshold_sel = MAC_AX_CTS2SELF_BOTH_THRESHOLD;
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else
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mac_hw_cts_cfg.threshold_sel = MAC_AX_CTS2SELF_DISABLE;
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mac_hw_cts_cfg.band_sel = band_sel;
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mac_hw_cts_cfg.non_sec_threshold = non_sec_thr;
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mac_hw_cts_cfg.sec_threshold = sec_thr;
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hstatus = rtw_hal_mac_cfg_hw_cts2slef(hal_info, &mac_hw_cts_cfg);
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return hstatus;
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}
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