/******************************************************************************
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*
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* Copyright(c) 2019 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef _HAL_SOUND_H_
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#define _HAL_SOUND_H_
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#ifdef CONFIG_PHL_CMD_BF
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#define HAL_NPDA_RU_IDX_START 0
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#define HAL_NPDA_RU_IDX_END_20MHZ 8
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#define HAL_NPDA_RU_IDX_END_40MHZ 17
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#define HAL_NPDA_RU_IDX_END_80MHZ 36
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#define HAL_NPDA_RU_IDX_END_160MHZ 73
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#define HAL_SND_HE_BFRP_STA_SZ 5
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#define HAL_SND_HE_NDPA_STA_SZ 4
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#define HAL_SND_VHT_NDPA_STA_SZ 2
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#define HAL_SND_VHT_NDPA_FRM_CTRL 0x54
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#define HAL_SND_HE_NDPA_FRM_CTRL 0x54
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#define HAL_SND_VHT_BFRP_FRM_CTRL 0x44
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#define HAL_SND_HE_BFRP_FRM_CTRL 0x24 /* Trigger Frame */
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#define HAL_SND_TRIG_INFO_BFRP 0x1
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enum hal_snd_pkt_sel {
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HAL_SND_PKT_SEL_UST_NDPA = 0,
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HAL_SND_PKT_SEL_BST_NDPA =1,
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HAL_SND_PKT_SEL_LAST_NDP = 2,
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HAL_SND_PKT_SEL_MID_NDP = 3,
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HAL_SND_PKT_SEL_MID_BFRP = 4,
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HAL_SND_PKT_SEL_LAST_BFRP = 5,
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HAL_SND_PKT_SEL_MAX
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};
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enum hal_snd_pkt_ndpa_type {
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HAL_SND_PKT_NDPA_HT = 1,
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HAL_SND_PKT_NDPA_VHT = 2,
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HAL_SND_PKT_NDPA_HE = 3,
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HAL_SND_PKT_NDPA_MAX
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};
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struct hal_snd_pkt_xmit_para {
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enum channel_width bw;
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enum rtw_data_rate rate;
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enum rtw_gi_ltf gi_ltf;
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u8 stbc;
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u8 ldpc;
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};
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struct hal_snd_obj {
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struct hal_snd_pkt_xmit_para ndpa_xpara;
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struct hal_snd_pkt_xmit_para bfrp_xpara;
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};
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enum rtw_hal_status hal_snd_obj_init(void *hal);
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enum rtw_hal_status hal_snd_obj_deinit(void *hal);
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#else
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#define hal_snd_obj_init(_h) RTW_HAL_STATUS_SUCCESS
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#define hal_snd_obj_deinit(_h) RTW_HAL_STATUS_SUCCESS
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#endif
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#endif
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