/******************************************************************************
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*
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* Copyright(c) 2019 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#define _HAL_SER_C_
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#include "hal_headers.h"
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enum rtw_hal_status rtw_hal_ser_ctrl(void *hal, enum rtw_hal_ser_rsn rsn, bool en)
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{
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enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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hstatus = rtw_hal_mac_ser_ctrl(hal_info, rsn, en);
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return hstatus;
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}
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u32
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rtw_hal_ser_get_error_status(void *hal, u32 *err)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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enum RTW_PHL_SER_NOTIFY_EVENT notify = RTW_PHL_SER_L2_RESET;
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rtw_hal_mac_ser_get_error_status(hal_info, err);
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if ((*err == MAC_AX_ERR_L1_ERR_DMAC) || (*err == MAC_AX_ERR_L0_PROMOTE_TO_L1)) {
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notify = RTW_PHL_SER_PAUSE_TRX;
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} else if (*err == MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE) {
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notify = RTW_PHL_SER_DO_RECOVERY;
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} else if (*err == MAC_AX_ERR_L1_RESET_RECOVERY_DONE) {
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notify = RTW_PHL_SER_READY;
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} else if (*err < MAC_AX_ERR_L0_PROMOTE_TO_L1) {
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notify = RTW_PHL_SER_L0_RESET;
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} else if (*err == MAC_AX_DUMP_SHAREBUFF_INDICATOR) {
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notify = RTW_PHL_SER_DUMP_FW_LOG;
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} else if (*err == MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC) {
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notify = RTW_PHL_SER_LOG_ONLY;
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} else if ((*err == MAC_AX_ERR_L1_PROMOTE_TO_L2) ||
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((*err >= MAC_AX_ERR_L2_ERR_AH_DMA) && (*err <= MAC_AX_GET_ERR_MAX))) {
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notify = RTW_PHL_SER_L2_RESET;
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}
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return notify;
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}
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enum rtw_hal_status rtw_hal_ser_set_error_status(void *hal, u32 err)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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return rtw_hal_mac_ser_set_error_status(hal_info, err);
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}
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bool rtw_hal_ser_chk_ser_l1(void *hal)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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return rtw_hal_mac_ser_chk_ser_l1(hal_info);
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}
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enum rtw_hal_status rtw_hal_trigger_cmac_err(void *hal)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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return rtw_hal_mac_trigger_cmac_err(hal_info);
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}
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enum rtw_hal_status rtw_hal_trigger_dmac_err(void *hal)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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return rtw_hal_mac_trigger_dmac_err(hal_info);
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}
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enum rtw_hal_status rtw_hal_lv1_rcvy(void *hal, u32 step)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
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PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "===> rtw_hal_lv1_rcvy step %d\n", step);
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status = rtw_hal_mac_lv1_rcvy(hal_info, step);
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PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "<=== rtw_hal_lv1_rcvy step %d, status 0x%x\n", step, status);
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return status;
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}
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void rtw_hal_dump_fw_rsvd_ple(void *hal)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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u32 mac_err;
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mac_err = rtw_hal_mac_dump_fw_rsvd_ple(hal_info);
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}
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void
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rtw_hal_ser_reset_wdt_intr(void *hal)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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u32 mac_err;
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mac_err = rtw_hal_mac_ser_reset_wdt_intr(hal_info);
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PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "rtw_hal_ser_reset_wdt_intr status 0x%x\n",mac_err);
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}
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void rtw_hal_ser_int_cfg(void *hal, struct rtw_phl_com_t *phl_com,
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enum RTW_PHL_SER_CFG_STEP step)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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#ifdef CONFIG_SYNC_INTERRUPT
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struct rtw_phl_evt_ops *evt_ops = &phl_com->evt_ops;
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#endif /* CONFIG_SYNC_INTERRUPT */
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struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
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struct hal_spec_t *hal_spec = phl_get_ic_spec(phl_com);
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/* check whether to config imr during ser */
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if (!hal_spec->ser_cfg_int)
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return;
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switch (step) {
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case RTW_PHL_SER_M1_PRE_CFG:
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/**
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* 1. disable imr
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* 2. set imr used during ser
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*/
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#ifdef CONFIG_SYNC_INTERRUPT
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evt_ops->set_interrupt_caps(phlcom_to_drvpriv(phl_com), false);
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#else
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if (hal_ops->disable_interrupt)
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hal_ops->disable_interrupt(hal);
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#endif /* CONFIG_SYNC_INTERRUPT */
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if (hal_ops->init_int_default_value)
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hal_ops->init_int_default_value(hal, INT_SET_OPT_SER_START);
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break;
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case RTW_PHL_SER_M1_POST_CFG:
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/**
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* 1. enable interrupt
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*/
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#ifdef CONFIG_SYNC_INTERRUPT
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evt_ops->set_interrupt_caps(phlcom_to_drvpriv(phl_com), true);
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#else
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if (hal_ops->enable_interrupt)
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hal_ops->enable_interrupt(hal);
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#endif /* CONFIG_SYNC_INTERRUPT */
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break;
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case RTW_PHL_SER_M5_CFG:
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/**
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* 1. disable interrupt
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* 2. set imr used after ser
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* 3. enable interrupt
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*/
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#ifdef CONFIG_SYNC_INTERRUPT
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evt_ops->set_interrupt_caps(phlcom_to_drvpriv(phl_com), false);
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#else
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if (hal_ops->disable_interrupt)
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hal_ops->disable_interrupt(hal);
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#endif /* CONFIG_SYNC_INTERRUPT */
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if (hal_ops->init_int_default_value)
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hal_ops->init_int_default_value(hal, INT_SET_OPT_SER_DONE);
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#ifdef CONFIG_SYNC_INTERRUPT
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evt_ops->set_interrupt_caps(phlcom_to_drvpriv(phl_com), true);
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#else
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if (hal_ops->enable_interrupt)
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hal_ops->enable_interrupt(hal);
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#endif /* CONFIG_SYNC_INTERRUPT */
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break;
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default:
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PHL_ERR("%s(): unknown step!\n", __func__);
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}
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}
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