/******************************************************************************
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*
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* Copyright(c) 2019 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#define _HAL_PCI_C_
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#include "hal_headers.h"
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#ifdef CONFIG_PCI_HCI
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static u8 pci_read8(struct rtw_hal_com_t *hal, u32 addr)
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{
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return _os_read8_pcie(hal->drv_priv, addr);
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}
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static u16 pci_read16(struct rtw_hal_com_t *hal, u32 addr)
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{
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return _os_read16_pcie(hal->drv_priv, addr);
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}
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static u32 pci_read32(struct rtw_hal_com_t *hal, u32 addr)
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{
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return _os_read32_pcie(hal->drv_priv, addr);
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}
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static int pci_write8(struct rtw_hal_com_t *hal, u32 addr, u8 val)
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{
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return _os_write8_pcie(hal->drv_priv, addr, val);
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}
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static int pci_write16(struct rtw_hal_com_t *hal, u32 addr, u16 val)
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{
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return _os_write16_pcie(hal->drv_priv, addr, val);
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}
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static int pci_write32(struct rtw_hal_com_t *hal, u32 addr, u32 val)
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{
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return _os_write32_pcie(hal->drv_priv, addr, val);
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}
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#ifdef RTW_WKARD_BUS_WRITE
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static int pci_write_post_cfg(struct rtw_hal_com_t *hal, u32 addr, u32 val)
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{
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struct hal_info_t *hal_info = hal->hal_priv;
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struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
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enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
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if(NULL != hal_ops->write_reg_post_cfg) {
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hal_status = hal_ops->write_reg_post_cfg(hal_info, addr, val);
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}
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return hal_status;
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}
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#endif
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void hal_pci_set_io_ops(struct rtw_hal_com_t *hal, struct hal_io_ops *pops)
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{
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/*_rtw_memset((u8 *)pops, 0, sizeof(struct hal_io_ops));*/
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_os_mem_set(hal->drv_priv, (u8 *)pops, 0, sizeof(struct hal_io_ops));
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pops->_read8 = &pci_read8;
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pops->_read16 = &pci_read16;
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pops->_read32 = &pci_read32;
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pops->_write8 = &pci_write8;
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pops->_write16 = &pci_write16;
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pops->_write32 = &pci_write32;
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#ifdef RTW_WKARD_BUS_WRITE
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pops->_write_post_cfg = &pci_write_post_cfg;
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#endif
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}
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enum rtw_hal_status rtw_hal_set_l2_leave(void *hal)
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{
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enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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/* Only AON registers are accessed */
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status = hal_mac_set_l2_leave(hal_info);
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if (status != RTW_HAL_STATUS_SUCCESS) {
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PHL_ERR("%s : fail\n", __func__);
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}
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return status;
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}
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void rtw_hal_clear_bdidx(void *hal)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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FUNCIN();
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if (RTW_HAL_STATUS_SUCCESS != rtw_hal_mac_clr_bdidx(hal_info))
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PHL_ERR("%s failure \n", __func__);
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}
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void rtw_hal_rst_bdram(void *hal)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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FUNCIN();
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if (RTW_HAL_STATUS_SUCCESS != rtw_hal_mac_rst_bdram(hal_info))
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PHL_ERR("%s failure \n", __func__);
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}
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void rtw_hal_cfg_dma_io(void *hal, u8 en)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "%s : enable %u.\n", __func__, en);
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if (RTW_HAL_STATUS_SUCCESS != rtw_hal_mac_cfg_dma_io(hal_info, en))
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PHL_ERR("%s failure \n", __func__);
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}
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enum rtw_hal_status
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rtw_hal_pcie_cfg_get(void *hal, struct rtw_pcie_cfgspc_param *cfg)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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enum rtw_hal_status hsts = RTW_HAL_STATUS_FAILURE;
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struct mac_ax_pcie_cfgspc_param pcicfg;
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_os_mem_set(hal_to_drvpriv(hal_info), &pcicfg, 0, sizeof(pcicfg));
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if (!hal_info->hal_ops.get_pcicfg)
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return RTW_HAL_STATUS_FAILURE;
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hsts = hal_info->hal_ops.get_pcicfg(hal_info, cfg);
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return hsts;
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}
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#ifdef RTW_WKARD_DYNAMIC_LTR
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enum rtw_hal_status
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rtw_hal_ltr_en_hw_mode(void *hal, bool hw_mode)
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{
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enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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status = rtw_hal_mac_ltr_set_pcie(hal_info,
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hw_mode ? RTW_PCIE_BUS_FUNC_ENABLE : RTW_PCIE_BUS_FUNC_DISABLE,
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0, 0, 0, 0);
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if (status != RTW_HAL_STATUS_SUCCESS) {
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PHL_ERR("%s : fail\n", __func__);
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return status;
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}
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return status;
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}
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enum rtw_hal_status
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rtw_hal_ltr_sw_trigger(void *hal, enum rtw_pcie_ltr_state state)
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{
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enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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status = rtw_hal_mac_ltr_sw_trigger(hal_info, state);
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if (status != RTW_HAL_STATUS_SUCCESS)
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PHL_ERR("%s : fail\n", __func__);
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return status;
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}
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void rtw_hal_ltr_update_stats(void *hal, bool clear)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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struct rtw_trx_stat *trx_stat = &hal_info->hal_com->trx_stat;
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static u32 dly_start_time = 0;
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if(clear) {
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dly_start_time = 0;
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} else {
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/* first in */
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if (dly_start_time == 0) {
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dly_start_time = _os_get_cur_time_us();
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trx_stat->ltr_last_tx_dly_time = 0;
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}
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trx_stat->ltr_tx_dly_count++;
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trx_stat->ltr_last_tx_dly_time =
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phl_get_passing_time_us(dly_start_time);
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}
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}
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bool rtw_hal_ltr_is_sw_ctrl(struct rtw_phl_com_t *phl_com, void *hal)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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struct bus_cap_t *bus_cap = &hal_info->hal_com->bus_cap;
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return bus_cap->ltr_sw_ctrl ?
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(phl_com->bus_sw_cap.ltr_sw_ctrl ? true : false) : false;
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}
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bool rtw_hal_ltr_is_hw_ctrl(struct rtw_phl_com_t *phl_com, void *hal)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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struct bus_cap_t *bus_cap = &hal_info->hal_com->bus_cap;
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return bus_cap->ltr_hw_ctrl ?
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(phl_com->bus_sw_cap.ltr_hw_ctrl ? true : false) : false;
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}
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#endif
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void rtw_hal_set_pcicfg(struct rtw_phl_com_t *phl_com, void *hal)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
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struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
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if (NULL != hal_ops->hal_set_pcicfg)
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hal_status = hal_ops->hal_set_pcicfg(hal_info);
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if (hal_status != RTW_HAL_STATUS_SUCCESS)
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PHL_ERR("%s: set pci cfg fail\n", __func__);
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}
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#endif /*CONFIG_PCI_HCI*/
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