/******************************************************************************
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*
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* Copyright(c) 2019 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef _HAL_LD_FILE_H_
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#define _HAL_LD_FILE_H_
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#define PHYPG_BAND2G 0
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#define PHYPG_BAND5G 1
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#define PHYPG_RF1Tx 0
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#define PHYPG_RF2Tx 1
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#define PHYPG_OFFSET 15
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enum PHY_PG_RATE_def {
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CCK_11M_1M = 0,
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OFDM_18M_6M = 1,
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OFDM_54M_24M = 2,
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HE1SS_MCS3_0 = 3,
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HE1SS_MCS7_4 = 4,
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HE1SS_MCS11_8 = 5,
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HE1SS_DCM4_0 = 6,
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HE2SS_MCS3_0 = 3,
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HE2SS_MCS7_4 = 4,
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HE2SS_MCS11_8 = 5,
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HE2SS_DCM4_0 = 6,
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Legacy_AllRate2_1 = 7,
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HE_AllRate2_2 = 8,
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OFDM_AllRate5_1 = 9,
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OFDM_AllRate6_1 = 10,
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};
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struct _hal_file_regd_ext {
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u16 domain;
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char country[2];
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char reg_name[10];
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};
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typedef struct hal_txpwr_lmt_t {
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u8 band;
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u8 bw;
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u8 ntx;
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u8 rs;
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u8 bf;
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u8 reg;
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u8 ch;
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s8 val;
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u8 tx_shap_idx;
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} HAL_TXPWR_LMT_T , *PHAL_TXPWR_LMT_T;
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typedef struct hal_txpwr_lmt_ru_t {
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u8 band;
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u8 rubw;
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u8 ntx;
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u8 rs;
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u8 reg;
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u8 ch;
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s8 val;
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u8 tx_shap_idx;
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} Hal_Txpwr_lmt_Ru_t , *pHal_Txpwr_lmt_Ru_t;
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enum _halrf_tx_pw_lmt_ru_bandwidth_type {
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_PW_LMT_RU_BW_RU26,
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_PW_LMT_RU_BW_RU52,
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_PW_LMT_RU_BW_RU106,
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_PW_LMT_RU_BW_NULL
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};
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enum _halrf_pw_lmt_band_type {
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_PW_LMT_BAND_2_4G = 0,
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_PW_LMT_BAND_5G = 1,
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_PW_LMT_BAND_6G = 2,
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_PW_LMT_MAX_BAND = 3
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};
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enum _halrf_pw_lmt_bandwidth_type {
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_PW_LMT_BW_20M = 0,
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_PW_LMT_BW_40M = 1,
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_PW_LMT_BW_80M = 2,
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_PW_LMT_BW_160M = 3,
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_PW_LMT_MAX_BANDWIDTH_NUM = 4
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};
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enum _halrf_pw_lmt_ratesection_type {
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_PW_LMT_RS_CCK = 0,
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_PW_LMT_RS_OFDM = 1,
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_PW_LMT_RS_HT = 2,
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_PW_LMT_RS_VHT = 3,
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_PW_LMT_RS_HE = 4,
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_PW_LMT_MAX_RS_NUM = 5
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};
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enum _halrf_pw_lmt_rfpath_type {
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_PW_LMT_PH_1T = 0,
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_PW_LMT_PH_2T = 1,
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_PW_LMT_PH_3T = 2,
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_PW_LMT_PH_4T = 3,
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_PW_LMT_MAX_PH_NUM = 4
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};
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enum _halrf_pw_lmt_beamforming_type {
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_PW_LMT_NONBF = 0,
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_PW_LMT_BF = 1,
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_PW_LMT_MAX_BF_NUM = 2
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};
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/*@--------------------------Define Parameters-------------------------------*/
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#define AVG_THERMAL_NUM 8
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#define MAX_RF_PATH 4
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#define DELTA_SWINGIDX_SIZE 30
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#define BAND_NUM 4
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#define BAND_NUM_6G 4
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#define DELTA_SWINTSSI_SIZE 61
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/*@---------------------------End Define Parameters---------------------------*/
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struct hal_txpwr_track_t {
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/* u8 is_txpowertracking; */
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u8 tx_powercount;
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bool is_txpowertracking_init;
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bool is_txpowertracking;
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u8 txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */
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u8 tm_trigger;
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u8 internal_pa_5g[2]; /* pathA / pathB */
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u8 thermal_meter[2]; /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
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u8 thermal_value;
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u8 thermal_value_path[MAX_RF_PATH];
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u8 thermal_value_lck;
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u8 thermal_value_iqk;
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s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */
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u8 thermal_value_avg[AVG_THERMAL_NUM];
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u8 thermal_value_avg_path[MAX_RF_PATH][AVG_THERMAL_NUM];
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u8 thermal_value_avg_index;
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u8 thermal_value_avg_index_path[MAX_RF_PATH];
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s8 power_index_offset_path[MAX_RF_PATH];
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u8 thermal_value_rx_gain;
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u8 thermal_value_crystal;
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u8 thermal_value_dpk_store;
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u8 thermal_value_dpk_track;
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bool txpowertracking_in_progress;
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bool is_reloadtxpowerindex;
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u8 is_rf_pi_enable;
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u32 txpowertracking_callback_cnt; /* cosa add for debug */
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u8 is_cck_in_ch14;
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u8 CCK_index;
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u8 OFDM_index[MAX_RF_PATH];
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s8 power_index_offset;
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s8 delta_power_index;
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s8 delta_power_index_path[MAX_RF_PATH];
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s8 delta_power_index_last;
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s8 delta_power_index_last_path[MAX_RF_PATH];
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bool is_tx_power_changed;
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/*struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];*/
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u8 delta_lck;
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s8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_6ga_p[BAND_NUM_6G][DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_6ga_n[BAND_NUM_6G][DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_6gb_p[BAND_NUM_6G][DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_6gb_n[BAND_NUM_6G][DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_6gc_p[BAND_NUM_6G][DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_6gc_n[BAND_NUM_6G][DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_6gd_p[BAND_NUM_6G][DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_6gd_n[BAND_NUM_6G][DELTA_SWINGIDX_SIZE];
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s8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
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s8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
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s8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
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s8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
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s8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
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s8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
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s8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
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s8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
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s8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
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s8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
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s8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
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s8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
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s8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
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s8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
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u8 bb_swing_idx_ofdm[MAX_RF_PATH];
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u8 bb_swing_idx_ofdm_current;
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u8 bb_swing_idx_ofdm_base;
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u8 bb_swing_idx_ofdm_base_path[MAX_RF_PATH];
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bool bb_swing_flag_ofdm;
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u8 bb_swing_idx_cck;
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u8 bb_swing_idx_cck_current;
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u8 bb_swing_idx_cck_base;
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u8 default_ofdm_index;
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u8 default_cck_index;
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bool bb_swing_flag_cck;
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s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
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s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
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s8 absolute_cck_swing_idx[MAX_RF_PATH];
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s8 remnant_cck_swing_idx;
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s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */
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bool modify_tx_agc_flag_path_a;
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bool modify_tx_agc_flag_path_b;
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bool modify_tx_agc_flag_path_c;
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bool modify_tx_agc_flag_path_d;
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bool modify_tx_agc_flag_path_a_cck;
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bool modify_tx_agc_flag_path_b_cck;
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s8 kfree_offset[MAX_RF_PATH];
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/*Add by Yuchen for Kfree Phydm*/
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u8 reg_rf_kfree_enable; /*for registry*/
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u8 rf_kfree_enable; /*for efuse enable check*/
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};
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int rtw_hal_find_ext_regd_num(struct rtw_para_pwrlmt_info_t *para_info, const char *regd_name);
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void rtw_hal_dl_all_para_file(struct rtw_phl_com_t *phl_com, char *ic_name, void *hal);
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u8 rtw_hal_efuse_shadow_file_load(void *hal, char *ic_name, bool is_limit);
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u8 rtw_hal_ld_fw_symbol(struct rtw_phl_com_t *phl_com,
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struct rtw_hal_com_t *hal_com, const char *name, u8 **buf, u32 *buf_size);
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#endif /*_HAL_LD_FILE_H_*/
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