/******************************************************************************
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*
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* Copyright(c) 2019 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#define _HAL_API_C_
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#include "hal_headers.h"
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enum rtw_hal_status rtw_hal_get_tsf(void *hal, enum phl_band_idx band,
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u8 port, u32 *tsf_h, u32 *tsf_l)
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{
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return rtw_hal_mac_get_tsf(hal, band, port, tsf_h, tsf_l);
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}
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enum rtw_hal_status
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rtw_hal_tsf_sync(void *hal, u8 port_sync_from,
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u8 port_sync_to, enum phl_band_idx band,
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s32 sync_offset_tu, enum hal_tsf_sync_act act)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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return rtw_hal_mac_tsf_sync(hal_info, port_sync_from,
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port_sync_to, band, sync_offset_tu, act);
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}
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enum rtw_hal_status
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rtw_hal_config_rts_th(void *hal, u8 band_idx, u16 rts_time_th, u16 rts_len_th)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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return rtw_hal_mac_set_hw_rts_th(hal_info, band_idx, rts_time_th, rts_len_th);
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}
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u32 rtw_hal_get_btc_req_slot(void *hal, enum phl_band_idx hw_band)
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{
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return rtw_hal_btc_req_bt_slot_t(hal, hw_band);
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}
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/**
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* This function is used to pause/unpause multiple macid
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* @hal: see hal_info_t
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* @macid_arr: macid array to be pause/unpause
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* 1 means to be set (pause/unpause)
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* 0 means don't care
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* @macid_arr_sz: size of macid array
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* @pause: all macid of this array to be paused/unpaused
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* 1=paused,0=unpaused
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*/
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enum rtw_hal_status
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rtw_hal_set_macid_grp_pause(void *hal, u32 *macid_arr, u8 arr_size, bool pause)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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struct rtw_hal_com_t *hal_com = hal_info->hal_com;
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return rtw_hal_mac_set_macid_grp_pause(hal_com, macid_arr, arr_size, pause);
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}
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/**
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* This function is used to pause/unpause single macid
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* @hal: see hal_info_t
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* @macid: macid be pause/unpause
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* @pause: all macid of this array to be paused/unpaused
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* 1=paused,0=unpaused
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*/
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enum rtw_hal_status
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rtw_hal_set_macid_pause(void *hal, u16 macid, bool pause)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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struct rtw_hal_com_t *hal_com = hal_info->hal_com;
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return rtw_hal_mac_set_macid_pause(hal_com, macid, pause);
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}
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/**
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* This function is used to pause/unpause AC queue of a single macid
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* @hal: see hal_info_t
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* @macid: macid be pause/unpause
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* @pause: paused/unpaused (1=paused,0=unpaused)
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*/
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enum rtw_hal_status rtw_hal_set_macid_pause_ac(void *hal, u16 macid, bool pause)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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struct rtw_hal_com_t *hal_com = hal_info->hal_com;
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return rtw_hal_mac_set_macid_pause_sleep(hal_com, macid, pause, false);
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}
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enum rtw_hal_status
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rtw_hal_set_macid_pkt_drop(void *hal, u16 macid, u8 sel, u8 band, u8 port,
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u8 mbssid)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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struct rtw_hal_com_t *hal_com = hal_info->hal_com;
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return rtw_hal_mac_set_macid_pkt_drop(hal_com, macid, sel, band, port,
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mbssid);
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}
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enum rtw_hal_status rtw_hal_set_dfs_tb_ctrl(void *hal, u8 set)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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return rtw_hal_mac_set_dfs_tb_ctrl(hal_info, set);
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}
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u32 rtw_hal_get_phy_stat_info(void *hal, enum phl_band_idx hw_band,
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enum phl_stat_info_query phy_stat)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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struct rtw_hal_com_t *hal_com = hal_info->hal_com;
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struct rtw_hal_stat_info *stat_info = &hal_com->band[hw_band].stat_info;
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switch (phy_stat) {
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case STAT_INFO_FA_ALL:
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return stat_info->cnt_fail_all;
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case STAT_INFO_CCA_ALL:
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return stat_info->cnt_cca_all;
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default:
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return 0;
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}
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}
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enum rtw_hal_status rtw_hal_get_rx_cnt_by_idx(void *hal,
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enum phl_band_idx hw_band,
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enum phl_rxcnt_idx idx,
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u16 *rx_cnt)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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return rtw_hal_mac_get_rx_cnt_by_idx(hal_info, hw_band, idx, rx_cnt);
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}
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enum rtw_hal_status rtw_hal_set_reset_rx_cnt(void *hal,
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enum phl_band_idx hw_band)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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return rtw_hal_mac_set_reset_rx_cnt(hal_info, hw_band);
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}
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enum rtw_hal_status
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rtw_hal_set_dctrl_tbl_seq(void *hal,
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struct rtw_phl_stainfo_t *sta, u32 seq)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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enum rtw_hal_status sts = RTW_HAL_STATUS_FAILURE;
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struct mac_ax_dctl_info dctrl = {0}, dctrl_mask = {0};
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if (NULL == sta)
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goto out;
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dctrl.seq0 = seq;
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dctrl.seq1 = seq;
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dctrl.seq2 = seq;
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dctrl.seq3 = seq;
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dctrl_mask.seq0 = 0x0FFF;
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dctrl_mask.seq1 = 0x0FFF;
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dctrl_mask.seq2 = 0x0FFF;
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dctrl_mask.seq3 = 0x0FFF;
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sts = rtw_hal_dmc_tbl_cfg(hal_info, &dctrl ,&dctrl_mask, sta->macid);
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out:
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return sts;
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}
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#ifdef CONFIG_PHL_DRV_HAS_NVM
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enum rtw_hal_status
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rtw_hal_extract_efuse_info(void *hal, u8 *efuse_map,
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enum rtw_efuse_info info_type,
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void *value,
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u8 size, u8 map_valid)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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enum rtw_phl_status hal_status = RTW_HAL_STATUS_FAILURE;
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if (info_type <= EFUSE_INFO_MAC_MAX)
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hal_status = rtw_hal_mac_get_efuse_info(hal_info->hal_com,
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efuse_map,
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info_type,
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value,
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size,
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1);
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else if (info_type <= EFUSE_INFO_BB_MAX)
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hal_status = rtw_hal_bb_get_efuse_info(hal_info->hal_com,
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efuse_map,
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info_type,
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value,
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size,
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1);
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else if (info_type <= EFUSE_INFO_RF_MAX)
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hal_status = rtw_hal_rf_get_efuse_info(hal_info->hal_com,
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efuse_map,
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info_type,
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value,
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size,
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1);
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else if (info_type <= EFUSE_INFO_BTCOEX_MAX)
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hal_status = rtw_hal_btc_get_efuse_info(hal_info->hal_com,
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efuse_map,
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info_type,
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value,
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size,
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1);
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return hal_status;
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}
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enum rtw_hal_status
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rtw_hal_get_efuse_size(void *hal, u32 *log_efuse_size, u32 *limit_efuse_size,
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u32 *mask_size, u32 *limit_mask_size)
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{
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enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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if (log_efuse_size)
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hal_status = rtw_hal_mac_get_log_efuse_size(hal_info->hal_com,
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log_efuse_size,
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false);
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if (limit_efuse_size && (hal_status == RTW_HAL_STATUS_SUCCESS))
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hal_status = rtw_hal_mac_get_log_efuse_size(hal_info->hal_com,
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limit_efuse_size,
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true);
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if (mask_size && (hal_status == RTW_HAL_STATUS_SUCCESS))
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hal_status = rtw_hal_mac_get_efuse_mask_size(hal_info->hal_com,
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mask_size,
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false);
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if (limit_mask_size && (hal_status == RTW_HAL_STATUS_SUCCESS))
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hal_status = rtw_hal_mac_get_efuse_mask_size(hal_info->hal_com,
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limit_mask_size,
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true);
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return hal_status;
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}
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enum rtw_hal_status
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rtw_hal_nvm_apply_dev_cap(void *hal, struct rtw_phl_com_t *phl_com)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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struct rtw_hal_com_t *hal_com = hal_info->hal_com;
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enum rtw_hal_status hal_sts;
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hal_com->dev_hw_cap.pkg_type = phl_com->dev_sw_cap.pkg_type;
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hal_com->dev_hw_cap.rfe_type = phl_com->dev_sw_cap.rfe_type;
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hal_com->dev_hw_cap.xcap = phl_com->dev_sw_cap.xcap;
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hal_com->dev_hw_cap.domain = phl_com->dev_sw_cap.domain;
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hal_sts = rtw_hal_mac_set_xcap(hal_com, 0, hal_com->dev_hw_cap.xcap);
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if (hal_sts != RTW_HAL_STATUS_SUCCESS)
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return RTW_HAL_STATUS_FAILURE;
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hal_sts = rtw_hal_mac_set_xcap(hal_com, 1, hal_com->dev_hw_cap.xcap);
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#ifdef CONFIG_RTW_MULTI_DEV_MULTI_BAND
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if (hal_sts == RTW_HAL_STATUS_SUCCESS) {
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struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
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if (hal_ops->cfg_share_xstal != NULL) {
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#ifdef CONFIG_SHARE_XSTAL
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hal_sts = hal_ops->cfg_share_xstal(hal_info, phl_com,
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true);
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#else
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hal_sts = hal_ops->cfg_share_xstal(hal_info, phl_com,
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false);
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#endif /* CONFIG_SHARE_XSTAL */
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}
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}
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#endif /* CONFIG_RTW_MULTI_DEV_MULTI_BAND */
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return hal_sts;
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}
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enum rtw_hal_status
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rtw_hal_flash_get_info(struct rtw_hal_com_t *hal_com,
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enum rtw_efuse_info info_type,
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void *value,
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u8 size)
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{
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u32 ret = _os_nvm_get_info(hal_com->drv_priv, info_type, value, size);
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return (ret == _SUCCESS) ? RTW_HAL_STATUS_SUCCESS : RTW_HAL_STATUS_FAILURE;
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}
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#endif /* CONFIG_PHL_DRV_HAS_NVM */
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enum rtw_hal_status
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rtw_hal_set_fw_ul_fixinfo(void *hal,
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struct rtw_phl_ax_ul_fixinfo *ul_fixinfo)
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{
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enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
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hstatus = rtw_hal_mac_set_fw_ul_fixinfo(hal, ul_fixinfo);
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return hstatus;
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}
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u16 rtw_hal_get_ampdu_num(void *hal, u8 band)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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return rtw_hal_mac_query_ampdu_num(hal_info, band);
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}
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enum rtw_chip_id rtw_hal_get_chip_id(void *hal)
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{
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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return hal_get_chip_id(hal_info->hal_com);
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}
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enum rtw_hal_status rtw_hal_set_append_fcs(void *hal, u8 enable)
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{
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return rtw_hal_mac_set_append_fcs((struct hal_info_t *)hal, enable);
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}
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enum rtw_hal_status
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rtw_hal_pwr_switch_mac(void *hal, bool on)
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{
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enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
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hstatus = rtw_hal_mac_pwr_switch(hal, on);
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return hstatus;
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}
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enum rtw_hal_status rtw_hal_get_freerun_counter(void *hal, u8 band, u32 *freerun_h, u32 *freerun_l)
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{
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enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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status = rtw_hal_mac_get_freerun_cnt(hal_info->hal_com, band, freerun_h, freerun_l);
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if (status != RTW_HAL_STATUS_SUCCESS) {
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PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_get_freerun_counter(): get failed\n");
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}
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return status;
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}
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enum rtw_hal_status rtw_hal_reset_freerun_counter(void *hal, u8 band)
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{
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enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
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struct hal_info_t *hal_info = (struct hal_info_t *)hal;
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status = rtw_hal_mac_reset_freerun_cnt(hal_info->hal_com, band);
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if (status != RTW_HAL_STATUS_SUCCESS) {
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PHL_TRACE(COMP_PHL_MCC, _PHL_ERR_, "rtw_hal_reset_freerun_counter(): get failed\n");
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}
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return status;
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}
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u8 rtw_hal_query_group_cntry_num(void *hal, struct rtw_regu_policy *policy,
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u8 group_id)
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{
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struct hal_info_t *hal_info = NULL;
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struct hal_ops_t *hal_ops = NULL;
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struct hal_regu_ops *regu_ops = NULL;
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if (!hal || !policy)
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return 0;
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hal_info = (struct hal_info_t *)hal;
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hal_ops = hal_get_ops(hal_info);
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if (!hal_ops)
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return 0;
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regu_ops = hal_get_regu_ops(hal_ops);
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if (regu_ops && regu_ops->hal_query_group_cntry_num)
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return regu_ops->hal_query_group_cntry_num(policy, group_id);
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return 0;
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}
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void rtw_hal_fill_group_cntry_list(void *hal,
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struct rtw_regu_policy *policy, char *list,
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u32 group_size, u8 group_id)
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{
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struct hal_info_t *hal_info = NULL;
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struct hal_ops_t *hal_ops = NULL;
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struct hal_regu_ops *regu_ops = NULL;
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if (!hal || !policy)
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return;
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hal_info = (struct hal_info_t *)hal;
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hal_ops = hal_get_ops(hal_info);
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if (!hal_ops)
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return;
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regu_ops = hal_get_regu_ops(hal_ops);
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if (regu_ops && regu_ops->hal_fill_group_cntry_list)
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regu_ops->hal_fill_group_cntry_list(policy, list,
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group_size, group_id);
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}
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u8 rtw_hal_get_cntry_idx(void *hal, char *cntry)
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{
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struct hal_info_t *hal_info = NULL;
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struct hal_ops_t *hal_ops = NULL;
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struct hal_regu_ops *regu_ops = NULL;
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if (!hal)
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return INVALID_CNTRY_IDX;
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hal_info = (struct hal_info_t *)hal;
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hal_ops = hal_get_ops(hal_info);
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if (!hal_ops)
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return INVALID_CNTRY_IDX;
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regu_ops = hal_get_regu_ops(hal_ops);
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if (regu_ops && regu_ops->hal_get_cntry_idx)
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return regu_ops->hal_get_cntry_idx(cntry);
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return INVALID_CNTRY_IDX;
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}
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u8 rtw_hal_get_cntry_tbl_size(void *hal)
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{
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struct hal_info_t *hal_info = NULL;
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struct hal_ops_t *hal_ops = NULL;
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struct hal_regu_ops *regu_ops = NULL;
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if (!hal)
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return 0;
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hal_info = (struct hal_info_t *)hal;
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hal_ops = hal_get_ops(hal_info);
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if (!hal_ops)
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return 0;
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regu_ops = hal_get_regu_ops(hal_ops);
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if (regu_ops && regu_ops->hal_get_cntry_tbl_size)
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return regu_ops->hal_get_cntry_tbl_size();
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return 0;
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}
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void rtw_hal_qry_cntry_chnlplan(
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void *hal, struct rtw_regulation_country_chplan *chplan,
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char *country)
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{
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struct hal_info_t *hal_info = NULL;
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struct hal_ops_t *hal_ops = NULL;
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struct hal_regu_ops *regu_ops = NULL;
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if (!hal)
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return;
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hal_info = (struct hal_info_t *)hal;
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hal_ops = hal_get_ops(hal_info);
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if (!hal_ops)
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return;
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regu_ops = hal_get_regu_ops(hal_ops);
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if (regu_ops && regu_ops->hal_qry_cntry_chnlplan)
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regu_ops->hal_qry_cntry_chnlplan(chplan, country);
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}
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void rtw_hal_get_chplan_update_info(
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void *hal, u8 group, u8 did,
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void *info, enum band_type band)
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{
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struct hal_info_t *hal_info = NULL;
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struct hal_ops_t *hal_ops = NULL;
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struct hal_regu_ops *regu_ops = NULL;
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if (!hal)
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return;
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hal_info = (struct hal_info_t *)hal;
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hal_ops = hal_get_ops(hal_info);
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if (!hal_ops)
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return;
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regu_ops = hal_get_regu_ops(hal_ops);
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if (regu_ops && regu_ops->hal_get_chplan_update_info)
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regu_ops->hal_get_chplan_update_info(group, did, info, band);
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}
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u8 rtw_hal_get_chnlplan_ver(void *hal)
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{
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struct hal_info_t *hal_info = NULL;
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struct hal_ops_t *hal_ops = NULL;
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struct hal_regu_ops *regu_ops = NULL;
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if (!hal)
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return INVALID_VER;
|
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hal_info = (struct hal_info_t *)hal;
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hal_ops = hal_get_ops(hal_info);
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if (!hal_ops)
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return INVALID_VER;
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regu_ops = hal_get_regu_ops(hal_ops);
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if (regu_ops && regu_ops->hal_get_chnlplan_ver)
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return regu_ops->hal_get_chnlplan_ver();
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return INVALID_VER;
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}
|
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u8 rtw_hal_get_country_ver(void *hal)
|
{
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struct hal_info_t *hal_info = NULL;
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struct hal_ops_t *hal_ops = NULL;
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struct hal_regu_ops *regu_ops = NULL;
|
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if (!hal)
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return INVALID_VER;
|
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hal_info = (struct hal_info_t *)hal;
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hal_ops = hal_get_ops(hal_info);
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if (!hal_ops)
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return INVALID_VER;
|
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regu_ops = hal_get_regu_ops(hal_ops);
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if (regu_ops && regu_ops->hal_get_country_ver)
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return regu_ops->hal_get_country_ver();
|
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return INVALID_VER;
|
}
|
|
void rtw_hal_get_chdef_6g(void * hal, u8 ch_idx,
|
struct chdef_6ghz *chdef)
|
{
|
struct hal_info_t *hal_info = NULL;
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struct hal_ops_t *hal_ops = NULL;
|
struct hal_regu_ops *regu_ops = NULL;
|
|
if (!hal)
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return;
|
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hal_info = (struct hal_info_t *)hal;
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hal_ops = hal_get_ops(hal_info);
|
if (!hal_ops)
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return;
|
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regu_ops = hal_get_regu_ops(hal_ops);
|
if (regu_ops && regu_ops->hal_get_chdef_6g)
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regu_ops->hal_get_chdef_6g(ch_idx, chdef);
|
}
|
|
u8 rtw_hal_get_domain_regulation(void *hal,
|
u8 domain, u8 band)
|
{
|
struct hal_info_t *hal_info = NULL;
|
struct hal_ops_t *hal_ops = NULL;
|
struct hal_regu_ops *regu_ops = NULL;
|
|
if (!hal)
|
return REGULATION_MAX;
|
|
hal_info = (struct hal_info_t *)hal;
|
hal_ops = hal_get_ops(hal_info);
|
if (!hal_ops)
|
return REGULATION_MAX;
|
|
regu_ops = hal_get_regu_ops(hal_ops);
|
if (regu_ops && regu_ops->hal_get_domain_regulation)
|
return regu_ops->hal_get_domain_regulation(domain, band);
|
|
return REGULATION_MAX;
|
}
|
|
u8 rtw_hal_get_domain_idx(void *hal,
|
u8 domain, bool is_6g)
|
{
|
struct hal_info_t *hal_info = NULL;
|
struct hal_ops_t *hal_ops = NULL;
|
struct hal_regu_ops *regu_ops = NULL;
|
|
if (!hal)
|
return INVALID_DOMAIN_INDEX;
|
|
hal_info = (struct hal_info_t *)hal;
|
hal_ops = hal_get_ops(hal_info);
|
if (!hal_ops)
|
return INVALID_DOMAIN_INDEX;
|
|
regu_ops = hal_get_regu_ops(hal_ops);
|
if (regu_ops && regu_ops->hal_get_domain_idx)
|
return regu_ops->hal_get_domain_idx(domain, is_6g);
|
|
return INVALID_DOMAIN_INDEX;
|
}
|
|
u8 rtw_hal_get_cat6g_by_country(
|
void *hal, char * country)
|
{
|
struct hal_info_t *hal_info = NULL;
|
struct hal_ops_t *hal_ops = NULL;
|
struct hal_regu_ops *regu_ops = NULL;
|
|
if (!hal)
|
return 0;
|
|
hal_info = (struct hal_info_t *)hal;
|
hal_ops = hal_get_ops(hal_info);
|
if (!hal_ops)
|
return 0;
|
|
regu_ops = hal_get_regu_ops(hal_ops);
|
if (regu_ops && regu_ops->hal_get_cat6g_by_country)
|
return regu_ops->hal_get_cat6g_by_country(country);
|
|
return 0;
|
}
|
|
void rtw_hal_get_6g_regulatory_info(void *hal, u8 domain,
|
u8 *dm_code, u8 *regulation, u8 *ch_idx)
|
{
|
struct hal_info_t *hal_info = NULL;
|
struct hal_ops_t *hal_ops = NULL;
|
struct hal_regu_ops *regu_ops = NULL;
|
|
if (!hal)
|
return;
|
|
hal_info = (struct hal_info_t *)hal;
|
hal_ops = hal_get_ops(hal_info);
|
if (!hal_ops)
|
return;
|
|
regu_ops = hal_get_regu_ops(hal_ops);
|
if (regu_ops && regu_ops->hal_get_6g_regulatory_info)
|
regu_ops->hal_get_6g_regulatory_info(domain,
|
dm_code, regulation, ch_idx);
|
}
|
|
enum rtw_hal_status
|
rtw_hal_set_bcn_early_rpt(void *hal, u8 band, u8 port, u8 en)
|
{
|
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
|
|
hstatus = rtw_hal_mac_cfg_bcn_early_rpt(hal, band, port, en);
|
|
return hstatus;
|
}
|
|
#ifdef CONFIG_PHL_CSUM_OFFLOAD_RX
|
enum rtw_hal_status rtw_hal_chk_rx_tcpip_chksum_ofd(void *h,
|
struct rtw_r_meta_data *mdata,
|
u8 status)
|
{
|
struct hal_info_t *hal = (struct hal_info_t *)h;
|
|
return rtw_hal_mac_chk_rx_tcpip_chksum_ofd(hal, mdata, status);
|
}
|
#endif /* CONFIG_PHL_CSUM_OFFLOAD_RX */
|
