/******************************************************************************
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*
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* Copyright(c) 2007 - 2019 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#define _PCI_OPS_LINUX_C_
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#include <drv_types.h>
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#ifdef RTK_129X_PLATFORM
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#include <soc/realtek/rtd129x_lockapi.h>
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#define IO_2K_MASK 0xFFFFF800
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#define IO_4K_MASK 0xFFFFF000
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#define MAX_RETRY 5
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u32 pci_io_read_129x(struct dvobj_priv *pdvobjpriv, u32 addr, u8 size)
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{
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unsigned long mask_addr = pdvobjpriv->mask_addr;
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unsigned long tran_addr = pdvobjpriv->tran_addr;
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PPCI_DATA pci_data = dvobj_to_pci(pdvobjpriv);
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u8 busnumber = pdvobjpriv->pcipriv.busnumber;
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u32 rval = 0;
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u32 mask;
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u32 translate_val = 0;
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u32 tmp_addr = addr & 0xFFF;
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u32 pci_error_status = 0;
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int retry_cnt = 0;
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unsigned long flags, sp_flags;
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_rtw_spinlock_irq(&pdvobjpriv->io_reg_lock, &sp_flags);
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/* PCIE1.1 0x9804FCEC, PCIE2.0 0x9803CCEC & 0x9803CC68
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* can't be used because of 1295 hardware issue.
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*/
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if ((tmp_addr == 0xCEC) || ((busnumber == 0x01) &&
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(tmp_addr == 0xC68))) {
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mask = IO_2K_MASK;
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writel(0xFFFFF800, (u8 *)mask_addr);
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translate_val = readl((u8 *)tran_addr);
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writel(translate_val|(addr&mask), (u8 *)tran_addr);
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} else if (addr >= 0x1000) {
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mask = IO_4K_MASK;
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translate_val = readl((u8 *)tran_addr);
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writel(translate_val|(addr&mask), (u8 *)tran_addr);
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} else
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mask = 0x0;
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pci_read_129x_retry:
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/* All RBUS1 driver need to have a workaround for emmc hardware error */
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/* Need to protect 0xXXXX_X8XX~ 0xXXXX_X9XX */
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if ((tmp_addr > 0x7FF) && (tmp_addr < 0xA00))
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rtk_lockapi_lock(flags, __func__);
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switch (size) {
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case 1:
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rval = readb((u8 *)pci_data->pci_mem_start + (addr&~mask));
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break;
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case 2:
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rval = readw((u8 *)pci_data->pci_mem_start + (addr&~mask));
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break;
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case 4:
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rval = readl((u8 *)pci_data->pci_mem_start + (addr&~mask));
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break;
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default:
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RTW_WARN("RTD129X: %s: wrong size %d\n", __func__, size);
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break;
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}
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if ((tmp_addr > 0x7FF) && (tmp_addr < 0xA00))
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rtk_lockapi_unlock(flags, __func__);
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//DLLP error patch
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pci_error_status = readl( (u8 *)(pdvobjpriv->ctrl_start + 0x7C));
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if(pci_error_status & 0x1F) {
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writel(pci_error_status, (u8 *)(pdvobjpriv->ctrl_start + 0x7C));
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RTW_WARN("RTD129X: %s: DLLP(#%d) 0x%x reg=0x%x val=0x%x\n",
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__func__, retry_cnt, pci_error_status, addr, rval);
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if(retry_cnt < MAX_RETRY) {
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retry_cnt++;
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goto pci_read_129x_retry;
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}
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}
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/* PCIE1.1 0x9804FCEC, PCIE2.0 0x9803CCEC & 0x9803CC68
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* can't be used because of 1295 hardware issue.
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*/
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if ((tmp_addr == 0xCEC) || ((busnumber == 0x01) &&
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(tmp_addr == 0xC68))) {
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writel(translate_val, (u8 *)tran_addr);
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writel(0xFFFFF000, (u8 *)mask_addr);
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} else if (addr >= 0x1000) {
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writel(translate_val, (u8 *)tran_addr);
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}
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_rtw_spinunlock_irq(&pdvobjpriv->io_reg_lock, &sp_flags);
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return rval;
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}
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void pci_io_write_129x(struct dvobj_priv *pdvobjpriv,
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u32 addr, u8 size, u32 wval)
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{
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unsigned long mask_addr = pdvobjpriv->mask_addr;
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unsigned long tran_addr = pdvobjpriv->tran_addr;
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PPCI_DATA pci_data = dvobj_to_pci(pdvobjpriv);
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u8 busnumber = pdvobjpriv->pcipriv.busnumber;
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u32 mask;
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u32 translate_val = 0;
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u32 tmp_addr = addr & 0xFFF;
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unsigned long sp_flags;
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_rtw_spinlock_irq(&pdvobjpriv->io_reg_lock, &sp_flags);
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/* PCIE1.1 0x9804FCEC, PCIE2.0 0x9803CCEC & 0x9803CC68
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* can't be used because of 1295 hardware issue.
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*/
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if ((tmp_addr == 0xCEC) || ((busnumber == 0x01) &&
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(tmp_addr == 0xC68))) {
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mask = IO_2K_MASK;
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writel(0xFFFFF800, (u8 *)mask_addr);
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translate_val = readl((u8 *)tran_addr);
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writel(translate_val|(addr&mask), (u8 *)tran_addr);
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} else if (addr >= 0x1000) {
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mask = IO_4K_MASK;
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translate_val = readl((u8 *)tran_addr);
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writel(translate_val|(addr&mask), (u8 *)tran_addr);
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} else
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mask = 0x0;
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/* All RBUS1 driver need to have a workaround for emmc hardware error */
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/* Need to protect 0xXXXX_X8XX~ 0xXXXX_X9XX */
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if ((tmp_addr > 0x7FF) && (tmp_addr < 0xA00))
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rtk_lockapi_lock(flags, __func__);
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switch (size) {
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case 1:
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writeb((u8)wval,
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(u8 *)pci_data->pci_mem_start + (addr&~mask));
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break;
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case 2:
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writew((u16)wval,
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(u8 *)pci_data->pci_mem_start + (addr&~mask));
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break;
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case 4:
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writel((u32)wval,
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(u8 *)pci_data->pci_mem_start + (addr&~mask));
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break;
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default:
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RTW_WARN("RTD129X: %s: wrong size %d\n", __func__, size);
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break;
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}
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if ((tmp_addr > 0x7FF) && (tmp_addr < 0xA00))
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rtk_lockapi_unlock(flags, __func__);
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/* PCIE1.1 0x9804FCEC, PCIE2.0 0x9803CCEC & 0x9803CC68
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* can't be used because of 1295 hardware issue.
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*/
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if ((tmp_addr == 0xCEC) || ((busnumber == 0x01) &&
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(tmp_addr == 0xC68))) {
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writel(translate_val, (u8 *)tran_addr);
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writel(0xFFFFF000, (u8 *)mask_addr);
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} else if (addr >= 0x1000) {
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writel(translate_val, (u8 *)tran_addr);
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}
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_rtw_spinunlock_irq(&pdvobjpriv->io_reg_lock, &sp_flags);
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}
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u8 os_pci_read8(struct dvobj_priv *dvobj, u32 addr)
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{
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return (u8)pci_io_read_129x(dvobj, addr, 1);
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}
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u16 os_pci_read16(struct dvobj_priv *dvobj, u32 addr)
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{
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return (u16)pci_io_read_129x(dvobj, addr, 2);
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}
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u32 os_pci_read32(struct dvobj_priv *dvobj, u32 addr)
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{
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return (u32)pci_io_read_129x(dvobj, addr, 4);
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}
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/*
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* 2009.12.23. by tynli. Suggested by SD1 victorh.
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* For ASPM hang on AMD and Nvidia.
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* 20100212 Tynli: Do read IO operation after write for
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* all PCI bridge suggested by SD1. Origianally this is only for INTEL.
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*/
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static int os_pci_write8(struct dvobj_priv *dvobj, u32 addr, u8 val)
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{
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pci_io_write_129x(dvobj, addr, 1, val);
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return 1;
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}
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static int os_pci_write16(struct dvobj_priv *dvobj, u32 addr, u16 val)
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{
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pci_io_write_129x(dvobj, addr, 2, val);
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return 2;
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}
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int os_pci_write32(struct dvobj_priv *dvobj, u32 addr, u32 val)
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{
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pci_io_write_129x(dvobj, addr, 4, val);
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return 4;
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}
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#elif defined (RTK_1319_PLATFORM)
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#include <soc/realtek/rtk_pcie.h>
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#ifndef RTK_1319_PCIE_PORT
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#define RTK_1319_PCIE_PORT 2
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#endif
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u8 os_pci_read8(struct dvobj_priv *dvobj, u32 addr)
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{
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#if (1 == RTK_1319_PCIE_PORT)
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return (u8)rtk_pcie2_13xx_read(addr, 1);
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#elif (2 == RTK_1319_PCIE_PORT)
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return (u8)rtk_pcie3_13xx_read(addr, 1);
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#endif
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}
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u16 os_pci_read16(struct dvobj_priv *dvobj, u32 addr)
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{
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#if (1 == RTK_1319_PCIE_PORT)
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return (u16)rtk_pcie2_13xx_read(addr, 2);
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#elif (2 == RTK_1319_PCIE_PORT)
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return (u16)rtk_pcie3_13xx_read(addr, 2);
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#endif
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}
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u32 os_pci_read32(struct dvobj_priv *dvobj, u32 addr)
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{
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#if (1 == RTK_1319_PCIE_PORT)
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return (u32)rtk_pcie2_13xx_read(addr, 4);
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#elif (2 == RTK_1319_PCIE_PORT)
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return (u32)rtk_pcie3_13xx_read(addr, 4);
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#endif
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}
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int os_pci_write8(struct dvobj_priv *dvobj, u32 addr, u8 val)
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{
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#if (1 == RTK_1319_PCIE_PORT)
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rtk_pcie2_13xx_write(addr, 1, val);
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#elif (2 == RTK_1319_PCIE_PORT)
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rtk_pcie3_13xx_write(addr, 1, val);
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#endif
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return 1;
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}
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int os_pci_write16(struct dvobj_priv *dvobj, u32 addr, u16 val)
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{
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#if (1 == RTK_1319_PCIE_PORT)
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rtk_pcie2_13xx_write(addr, 2, val);
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#elif (2 == RTK_1319_PCIE_PORT)
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rtk_pcie3_13xx_write(addr, 2, val);
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#endif
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return 2;
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}
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int os_pci_write32(struct dvobj_priv *dvobj, u32 addr, u32 val)
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{
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#if (1 == RTK_1319_PCIE_PORT)
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rtk_pcie2_13xx_write(addr, 4, val);
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#elif (2 == RTK_1319_PCIE_PORT)
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rtk_pcie3_13xx_write(addr, 4, val);
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#endif
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return 4;
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}
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#else /* original*/
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u8 os_pci_read8(struct dvobj_priv *dvobj, u32 addr)
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{
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return 0xff & readb((u8 *)dvobj_to_pci(dvobj)->pci_mem_start + addr);
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}
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u16 os_pci_read16(struct dvobj_priv *dvobj, u32 addr)
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{
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return readw((u8 *)dvobj_to_pci(dvobj)->pci_mem_start + addr);
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}
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u32 os_pci_read32(struct dvobj_priv *dvobj, u32 addr)
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{
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return readl((u8 *)dvobj_to_pci(dvobj)->pci_mem_start + addr);
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}
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/*
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* 2009.12.23. by tynli. Suggested by SD1 victorh.
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* For ASPM hang on AMD and Nvidia.
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* 20100212 Tynli: Do read IO operation after write for
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* all PCI bridge suggested by SD1. Origianally this is only for INTEL.
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*/
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int os_pci_write8(struct dvobj_priv *dvobj, u32 addr, u8 val)
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{
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writeb(val, (u8 *)dvobj_to_pci(dvobj)->pci_mem_start + addr);
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return 1;
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}
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int os_pci_write16(struct dvobj_priv *dvobj, u32 addr, u16 val)
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{
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writew(val, (u8 *)dvobj_to_pci(dvobj)->pci_mem_start + addr);
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return 2;
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}
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int os_pci_write32(struct dvobj_priv *dvobj, u32 addr, u32 val)
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{
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writel(val, (u8 *)dvobj_to_pci(dvobj)->pci_mem_start + addr);
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return 4;
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}
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#endif
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