/******************************************************************************
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*
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* Copyright(c) 2007 - 2019 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef _RTW_MP_H_
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#define _RTW_MP_H_
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#include <drv_types.h>
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#define RTWPRIV_VER_INFO 1
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#define MAX_MP_XMITBUF_SZ 2048
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#define NR_MP_XMITFRAME 8
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#define MP_READ_REG_MAX_OFFSET 0x4FFF
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#define TX_POWER_BASE 4 /* dbm * 4 */
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#define TX_POWER_CODE_WORD_BASE 8 /* dbm * 8 */
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#define RTW_IWD_MAX_LEN 128
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struct mp_xmit_frame {
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_list list;
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struct pkt_attrib attrib;
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struct sk_buff *pkt;
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int frame_tag;
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_adapter *padapter;
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#ifdef CONFIG_USB_HCI
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/* insert urb, irp, and irpcnt info below... */
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/* max frag_cnt = 8 */
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u8 *mem_addr;
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u32 sz[8];
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u8 bpending[8];
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sint ac_tag[8];
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sint last[8];
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uint irpcnt;
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uint fragcnt;
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#endif /* CONFIG_USB_HCI */
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uint mem[(MAX_MP_XMITBUF_SZ >> 2)];
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};
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struct mp_wiparam {
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u32 bcompleted;
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u32 act_type;
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u32 io_offset;
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u32 io_value;
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};
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typedef void(*wi_act_func)(void *padapter);
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struct mp_tx {
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u8 stop;
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u32 count, sended;
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u8 payload;
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struct pkt_attrib attrib;
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/* struct tx_desc desc; */
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/* u8 resvdtx[7]; */
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u8 desc[TXDESC_SIZE];
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u8 *pallocated_buf;
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u8 *buf;
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u32 buf_size, write_size;
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_thread_hdl_ PktTxThread;
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};
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#define MP_MAX_LINES 1000
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#define MP_MAX_LINES_BYTES 256
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typedef struct _RT_PMAC_PKT_INFO {
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u8 MCS;
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u8 Nss;
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u8 Nsts;
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u32 N_sym;
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u8 SIGA2B3;
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} RT_PMAC_PKT_INFO, *PRT_PMAC_PKT_INFO;
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typedef struct _RT_PMAC_TX_INFO {
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u8 bEnPMacTx:1; /* 0: Disable PMac 1: Enable PMac */
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u8 Mode:3; /* 0: Packet TX 3:Continuous TX */
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u8 Ntx:4; /* 0-7 */
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u8 TX_RATE; /* MPT_RATE_E */
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u8 TX_RATE_HEX;
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u8 TX_SC;
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u8 bSGI:1;
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u8 bSPreamble:1;
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u8 bSTBC:1;
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u8 bLDPC:1;
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u8 NDP_sound:1;
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u8 BandWidth:3; /* 0: 20 1:40 2:80Mhz */
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u8 m_STBC; /* bSTBC + 1 */
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u16 PacketPeriod;
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u32 PacketCount;
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u32 PacketLength;
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u8 PacketPattern;
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u16 SFD;
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u8 SignalField;
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u8 ServiceField;
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u16 LENGTH;
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u8 CRC16[2];
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u8 LSIG[3];
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u8 HT_SIG[6];
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u8 VHT_SIG_A[6];
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u8 VHT_SIG_B[4];
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u8 VHT_SIG_B_CRC;
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u8 VHT_Delimiter[4];
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u8 MacAddress[6];
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} RT_PMAC_TX_INFO, *PRT_PMAC_TX_INFO;
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struct rtw_mp_giltf_data {
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u8 gi;
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u8 ltf;
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char type_str[8];
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};
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typedef void (*MPT_WORK_ITEM_HANDLER)(void *adapter);
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typedef struct _MPT_CONTEXT {
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/* Indicate if we have started Mass Production Test. */
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BOOLEAN bMassProdTest;
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/* Indicate if the driver is unloading or unloaded. */
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BOOLEAN bMptDrvUnload;
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_sema MPh2c_Sema;
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_timer MPh2c_timeout_timer;
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/* Event used to sync H2c for BT control */
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BOOLEAN MptH2cRspEvent;
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BOOLEAN MptBtC2hEvent;
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BOOLEAN bMPh2c_timeout;
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/* 8190 PCI does not support NDIS_WORK_ITEM. */
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/* Work Item for Mass Production Test. */
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/* NDIS_WORK_ITEM MptWorkItem;
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* RT_WORK_ITEM MptWorkItem; */
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/* Event used to sync the case unloading driver and MptWorkItem is still in progress.
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* NDIS_EVENT MptWorkItemEvent; */
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/* To protect the following variables.
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* NDIS_SPIN_LOCK MptWorkItemSpinLock; */
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/* Indicate a MptWorkItem is scheduled and not yet finished. */
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BOOLEAN bMptWorkItemInProgress;
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/* An instance which implements function and context of MptWorkItem. */
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MPT_WORK_ITEM_HANDLER CurrMptAct;
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/* 1=Start, 0=Stop from UI. */
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u32 MptTestStart;
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/* _TEST_MODE, defined in MPT_Req2.h */
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u32 MptTestItem;
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/* Variable needed in each implementation of CurrMptAct. */
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u32 MptActType; /* Type of action performed in CurrMptAct. */
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/* The Offset of IO operation is depend of MptActType. */
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u32 MptIoOffset;
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/* The Value of IO operation is depend of MptActType. */
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u32 MptIoValue;
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/* The RfPath of IO operation is depend of MptActType. */
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u32 mpt_rf_path;
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u8 MptChannelToSw; /* Channel to switch. */
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u8 MptInitGainToSet; /* Initial gain to set. */
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/* u32 bMptAntennaA; */ /* TRUE if we want to use antenna A. */
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u32 MptBandWidth; /* bandwidth to switch. */
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u32 mpt_rate_index;/* rate index. */
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/* Register value kept for Single Carrier Tx test. */
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u8 btMpCckTxPower;
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/* Register value kept for Single Carrier Tx test. */
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u8 btMpOfdmTxPower;
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/* For MP Tx Power index */
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u8 TxPwrLevel[4]; /* rf-A, rf-B*/
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u32 RegTxPwrLimit;
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/* Content of RCR Regsiter for Mass Production Test. */
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u32 MptRCR;
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/* TRUE if we only receive packets with specific pattern. */
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BOOLEAN bMptFilterPattern;
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/* Rx OK count, statistics used in Mass Production Test. */
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u32 MptRxOkCnt;
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/* Rx CRC32 error count, statistics used in Mass Production Test. */
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u32 MptRxCrcErrCnt;
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BOOLEAN bCckContTx; /* TRUE if we are in CCK Continuous Tx test. */
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BOOLEAN bOfdmContTx; /* TRUE if we are in OFDM Continuous Tx test. */
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/* TRUE if we have start Continuous Tx test. */
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BOOLEAN is_start_cont_tx;
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/* TRUE if we are in Single Carrier Tx test. */
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BOOLEAN bSingleCarrier;
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/* TRUE if we are in Carrier Suppression Tx Test. */
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BOOLEAN is_carrier_suppression;
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/* TRUE if we are in Single Tone Tx test. */
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BOOLEAN is_single_tone;
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/* ACK counter asked by K.Y.. */
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BOOLEAN bMptEnableAckCounter;
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u32 MptAckCounter;
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/* SD3 Willis For 8192S to save 1T/2T RF table for ACUT Only fro ACUT delete later ~~~! */
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/* s8 BufOfLines[2][MAX_LINES_HWCONFIG_TXT][MAX_BYTES_LINE_HWCONFIG_TXT]; */
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/* s8 BufOfLines[2][MP_MAX_LINES][MP_MAX_LINES_BYTES]; */
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/* s32 RfReadLine[2]; */
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u8 APK_bound[2]; /* for APK path A/path B */
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BOOLEAN bMptIndexEven;
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u8 backup0xc50;
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u8 backup0xc58;
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u8 backup0xc30;
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u8 backup0x52_RF_A;
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u8 backup0x52_RF_B;
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u32 backup0x58_RF_A;
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u32 backup0x58_RF_B;
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u8 h2cReqNum;
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u8 c2hBuf[32];
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u8 btInBuf[100];
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u32 mptOutLen;
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u8 mptOutBuf[100];
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RT_PMAC_TX_INFO PMacTxInfo;
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RT_PMAC_PKT_INFO PMacPktInfo;
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u8 HWTxmode;
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BOOLEAN bldpc;
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BOOLEAN bstbc;
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} MPT_CONTEXT, *PMPT_CONTEXT;
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/* #endif */
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/* #define RTPRIV_IOCTL_MP ( SIOCIWFIRSTPRIV + 0x17) */
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enum {
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WRITE_REG = 1,
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READ_REG,
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WRITE_RF,
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READ_RF,
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MP_START,
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MP_STOP,
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MP_RATE,
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MP_CHANNEL,
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MP_TRXSC_OFFSET,
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MP_BANDWIDTH,
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MP_TXPOWER,
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MP_ANT_TX,
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MP_ANT_RX,
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MP_CTX,
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MP_QUERY,
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MP_ARX,
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MP_PSD,
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MP_PWRTRK,
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MP_THER,
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MP_IOCTL,
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EFUSE_GET,
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EFUSE_SET,
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MP_RESET_STATS,
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MP_DUMP,
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MP_PHYPARA,
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MP_SetRFPathSwh,
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MP_QueryDrvStats,
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CTA_TEST,
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MP_DISABLE_BT_COEXIST,
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MP_PwrCtlDM,
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MP_GETVER,
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MP_MON,
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EFUSE_BT_MASK,
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EFUSE_MASK,
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EFUSE_FILE,
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EFUSE_FILE_STORE,
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MP_TX,
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MP_RX,
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MP_IQK,
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MP_LCK,
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MP_HW_TX_MODE,
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MP_GET_TXPOWER_INX,
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MP_CUSTOMER_STR,
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MP_PWRLMT,
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MP_PWRBYRATE,
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BT_EFUSE_FILE,
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MP_SWRFPath,
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MP_LINK,
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MP_DPK_TRK,
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MP_DPK,
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MP_GET_TSSIDE,
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MP_SET_TSSIDE,
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MP_GET_PHL_TEST,
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MP_SET_PHL_TEST,
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MP_SET_PHL_TX_PATTERN,
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MP_SET_PHL_PLCP_TX_DATA,
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MP_SET_PHL_PLCP_TX_USER,
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MP_SET_PHL_TX_METHOD,
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MP_SET_PHL_CONIFG_PHY_NUM,
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MP_PHL_RFK,
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MP_PHL_BTC_PATH,
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MP_GET_HE,
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MP_UUID,
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MP_GPIO,
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MP_BAND,
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MP_MACLOOPBK,
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MP_MAC_IOTEST,
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MP_NULL,
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#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
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VENDOR_IE_SET ,
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VENDOR_IE_GET ,
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#endif
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#if defined(RTW_PHL_TX) || defined(RTW_PHL_RX) || defined(CONFIG_PHL_TEST_SUITE)
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PHL_TEST_SET,
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PHL_TEST_GET,
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#endif
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#ifdef CONFIG_WOWLAN
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MP_WOW_ENABLE,
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MP_WOW_SET_PATTERN,
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#endif
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#ifdef CONFIG_AP_WOWLAN
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MP_AP_WOW_ENABLE,
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#endif
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MP_SD_IREAD,
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MP_SD_IWRITE,
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#ifdef CONFIG_FPGA_INCLUDED
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FPGA_SET,
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#endif
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};
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struct rtw_plcp_user {
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u8 plcp_usr_idx;
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u16 plcp_mcs;
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u8 coding;
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u8 dcm;
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u8 aid;
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u32 plcp_txlen; /*apep*/
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u32 ru_alloc;
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u8 plcp_nss;
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u8 txbf;
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u8 pwr_boost_db;
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};
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struct mp_priv {
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_adapter *papdater;
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/* Testing Flag */
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u32 mode;/* 0 for normal type packet, 1 for loopback packet (16bytes TXCMD) */
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u32 prev_fw_state;
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/* OID cmd handler */
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struct mp_wiparam workparam;
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/* u8 act_in_progress; */
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/* Tx Section */
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u8 TID;
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u32 tx_pktcount;
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u32 pktInterval;
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u32 pktLength;
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struct mp_tx tx;
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/* Rx Section */
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u32 rx_bssidpktcount;
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u32 rx_pktcount;
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u32 rx_pktcount_filter_out;
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u32 rx_crcerrpktcount;
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u32 rx_pktloss;
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BOOLEAN rx_bindicatePkt;
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struct recv_stat rxstat;
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BOOLEAN brx_filter_beacon;
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/* RF/BB relative */
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u8 band;
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u32 channel;
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u8 bandwidth;
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u8 prime_channel_offset;
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u8 txpoweridx;
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s16 txpowerdbm;
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u16 rateidx;
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s16 pre_refcw_cck_pwridxa;
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s16 pre_refcw_cck_pwridxb;
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s16 pre_refcw_ofdm_pwridxa;
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s16 pre_refcw_ofdm_pwridxb;
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u32 preamble;
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/* u8 modem; */
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u32 CrystalCap;
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/* u32 curr_crystalcap; */
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u8 antenna_tx;
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u8 antenna_rx;
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u8 antenna_trx;
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u8 curr_rfpath;
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u8 check_mp_pkt;
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u8 bSetTxPower;
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/* uint ForcedDataRate; */
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u8 mp_dm;
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u8 mac_filter[ETH_ALEN];
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u8 bmac_filter;
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/* RF PATH Setting for WLG WLA BTG BT */
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u8 rf_path_cfg;
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u8 btc_path; /* BTC_MODE_NORMAL, BTC_MODE_WL,BTC_MODE_BT */
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struct wlan_network mp_network;
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NDIS_802_11_MAC_ADDRESS network_macaddr;
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u8 *pallocated_mp_xmitframe_buf;
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u8 *pmp_xmtframe_buf;
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_queue free_mp_xmitqueue;
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u32 free_mp_xmitframe_cnt;
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BOOLEAN bSetRxBssid;
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BOOLEAN bTxBufCkFail;
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BOOLEAN bRTWSmbCfg;
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BOOLEAN bloopback;
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BOOLEAN bloadefusemap;
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BOOLEAN bloadBTefusemap;
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BOOLEAN bprocess_mp_mode;
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MPT_CONTEXT mpt_ctx;
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u8 *TXradomBuffer;
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u8 mp_keep_btc_mode;
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u8 mplink_buf[2048];
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u32 mplink_rx_len;
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BOOLEAN mplink_brx;
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BOOLEAN mplink_btx;
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bool tssitrk_on;
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bool bspecif_tssi_de;
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u32 specif_tsside_val;
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u8 tssi_mode;
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u8 rtw_mp_cur_phy;
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u8 rtw_mp_dbcc;
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s16 path_pwr_offset[4]; /* rf-A, rf-B*/
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u8 rtw_mp_tx_method;
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u16 rtw_mp_tx_time;
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u8 rtw_mp_tx_state;
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u8 rtw_mp_pmact_patt_idx;
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u8 rtw_mp_pmact_ppdu_type;
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u8 rtw_mp_data_bandwidth;
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u8 rtw_mp_stbc;
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u8 rtw_mp_plcp_gi;
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u8 rtw_mp_plcp_ltf;
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u8 rtw_mp_he_sigb;
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u8 rtw_mp_he_sigb_dcm;
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u32 rtw_mp_plcp_tx_time;
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u8 rtw_mp_plcp_tx_mode;
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u8 rtw_mp_he_er_su_ru_106_en;
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u8 rtw_mp_trxsc;
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u16 rtw_mp_plcp_rualloc;
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u8 rtw_mp_plcp_tx_user;
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u32 rtw_mp_ru_tone;
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u8 ru_tone_sel_list[6];
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u8 ru_alloc_list[68];
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u8 rtw_coding;
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struct rtw_mp_giltf_data st_giltf[5];
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struct rtw_plcp_user mp_plcp_user[4];
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u8 mp_plcp_useridx;
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u8 keep_ips_status;
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u8 keep_lps_status;
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u8 tx_shape_idx;
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u8 gpio_id;
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u8 gpio_enable;
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u8 is_tmac_mode;
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_thread_hdl_ rx_cal_thread;
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u8 rx_cal_stop;
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u8 rx_cal_process;
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u8 loopbk_speed;
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u8 mac_iotest_res;
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u16 rx_rate;
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};
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#define PPDU_TYPE_STR(idx)\
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(idx == RTW_MP_TYPE_CCK) ? "CCK" :\
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(idx == RTW_MP_TYPE_LEGACY) ? "LEGACY" :\
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(idx == RTW_MP_TYPE_HT_MF) ? "HT_MF" :\
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(idx == RTW_MP_TYPE_HT_GF) ? "HT_GF" :\
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(idx == RTW_MP_TYPE_VHT) ? "VHT" :\
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(idx == RTW_MP_TYPE_HE_SU) ? "HE_SU" :\
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(idx == RTW_MP_TYPE_HE_ER_SU) ? "HE_ER_SU" :\
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(idx == RTW_MP_TYPE_HE_MU_OFDMA) ? "HE_MU" :\
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(idx == RTW_MP_TYPE_HE_TB) ? "HE_TB" :\
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"UNknow"
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typedef struct _IOCMD_STRUCT_ {
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u8 cmdclass;
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u16 value;
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u8 index;
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} IOCMD_STRUCT;
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struct rf_reg_param {
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u32 path;
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u32 offset;
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u32 value;
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};
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struct bb_reg_param {
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u32 offset;
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u32 value;
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};
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/* *********************************************************************** */
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#define LOWER _TRUE
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#define RAISE _FALSE
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/* Hardware Registers */
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#if 0
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#if 0
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#define IOCMD_CTRL_REG 0x102502C0
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#define IOCMD_DATA_REG 0x102502C4
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#else
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#define IOCMD_CTRL_REG 0x10250370
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#define IOCMD_DATA_REG 0x10250374
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#endif
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#define IOCMD_GET_THERMAL_METER 0xFD000028
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#define IOCMD_CLASS_BB_RF 0xF0
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#define IOCMD_BB_READ_IDX 0x00
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#define IOCMD_BB_WRITE_IDX 0x01
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#define IOCMD_RF_READ_IDX 0x02
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#define IOCMD_RF_WRIT_IDX 0x03
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#endif
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#define BB_REG_BASE_ADDR 0x800
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/* MP variables */
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#if 0
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#define _2MAC_MODE_ 0
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#define _LOOPBOOK_MODE_ 1
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#endif
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typedef enum _MP_MODE_ {
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MP_OFF,
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MP_ON,
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MP_ERR,
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MP_CONTINUOUS_TX,
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MP_SINGLE_CARRIER_TX,
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MP_CARRIER_SUPPRISSION_TX,
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MP_SINGLE_TONE_TX,
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MP_PACKET_TX,
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MP_PACKET_RX
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} MP_MODE;
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typedef enum _TEST_MODE {
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TEST_NONE ,
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PACKETS_TX ,
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PACKETS_RX ,
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CONTINUOUS_TX ,
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OFDM_Single_Tone_TX ,
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CCK_Carrier_Suppression_TX
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} TEST_MODE;
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typedef enum _MPT_BANDWIDTH {
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MPT_BW_20MHZ = 0,
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MPT_BW_40MHZ_DUPLICATE = 1,
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MPT_BW_40MHZ_ABOVE = 2,
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MPT_BW_40MHZ_BELOW = 3,
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MPT_BW_40MHZ = 4,
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MPT_BW_80MHZ = 5,
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MPT_BW_80MHZ_20_ABOVE = 6,
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MPT_BW_80MHZ_20_BELOW = 7,
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MPT_BW_80MHZ_20_BOTTOM = 8,
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MPT_BW_80MHZ_20_TOP = 9,
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MPT_BW_80MHZ_40_ABOVE = 10,
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MPT_BW_80MHZ_40_BELOW = 11,
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} MPT_BANDWIDTHE, *PMPT_BANDWIDTH;
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#define MAX_RF_PATH_NUMS RF_PATH_MAX
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extern u8 mpdatarate[NumRates];
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/* MP set force data rate base on the definition. */
|
typedef enum _MPT_RATE_INDEX {
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/* CCK rate. */
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MPT_RATE_1M = 1 , /* 0 */
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MPT_RATE_2M,
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MPT_RATE_55M,
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MPT_RATE_11M, /* 3 */
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/* OFDM rate. */
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MPT_RATE_6M, /* 4 */
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MPT_RATE_9M,
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MPT_RATE_12M,
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MPT_RATE_18M,
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MPT_RATE_24M,
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MPT_RATE_36M,
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MPT_RATE_48M,
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MPT_RATE_54M, /* 11 */
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/* HT rate. */
|
MPT_RATE_MCS0, /* 12 */
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MPT_RATE_MCS1,
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MPT_RATE_MCS2,
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MPT_RATE_MCS3,
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MPT_RATE_MCS4,
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MPT_RATE_MCS5,
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MPT_RATE_MCS6,
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MPT_RATE_MCS7, /* 19 */
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MPT_RATE_MCS8,
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MPT_RATE_MCS9,
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MPT_RATE_MCS10,
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MPT_RATE_MCS11,
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MPT_RATE_MCS12,
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MPT_RATE_MCS13,
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MPT_RATE_MCS14,
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MPT_RATE_MCS15, /* 27 */
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MPT_RATE_MCS16,
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MPT_RATE_MCS17, /* #29 */
|
MPT_RATE_MCS18,
|
MPT_RATE_MCS19,
|
MPT_RATE_MCS20,
|
MPT_RATE_MCS21,
|
MPT_RATE_MCS22, /* #34 */
|
MPT_RATE_MCS23,
|
MPT_RATE_MCS24,
|
MPT_RATE_MCS25,
|
MPT_RATE_MCS26,
|
MPT_RATE_MCS27, /* #39 */
|
MPT_RATE_MCS28, /* #40 */
|
MPT_RATE_MCS29, /* #41 */
|
MPT_RATE_MCS30, /* #42 */
|
MPT_RATE_MCS31, /* #43 */
|
/* VHT rate. Total: 20*/
|
MPT_RATE_VHT1SS_MCS0 = 100,/* #44*/
|
MPT_RATE_VHT1SS_MCS1, /* # */
|
MPT_RATE_VHT1SS_MCS2,
|
MPT_RATE_VHT1SS_MCS3,
|
MPT_RATE_VHT1SS_MCS4,
|
MPT_RATE_VHT1SS_MCS5,
|
MPT_RATE_VHT1SS_MCS6, /* # */
|
MPT_RATE_VHT1SS_MCS7,
|
MPT_RATE_VHT1SS_MCS8,
|
MPT_RATE_VHT1SS_MCS9, /* #53 */
|
MPT_RATE_VHT2SS_MCS0, /* #54 */
|
MPT_RATE_VHT2SS_MCS1,
|
MPT_RATE_VHT2SS_MCS2,
|
MPT_RATE_VHT2SS_MCS3,
|
MPT_RATE_VHT2SS_MCS4,
|
MPT_RATE_VHT2SS_MCS5,
|
MPT_RATE_VHT2SS_MCS6,
|
MPT_RATE_VHT2SS_MCS7,
|
MPT_RATE_VHT2SS_MCS8,
|
MPT_RATE_VHT2SS_MCS9, /* #63 */
|
MPT_RATE_VHT3SS_MCS0,
|
MPT_RATE_VHT3SS_MCS1,
|
MPT_RATE_VHT3SS_MCS2,
|
MPT_RATE_VHT3SS_MCS3,
|
MPT_RATE_VHT3SS_MCS4,
|
MPT_RATE_VHT3SS_MCS5,
|
MPT_RATE_VHT3SS_MCS6, /* #126 */
|
MPT_RATE_VHT3SS_MCS7,
|
MPT_RATE_VHT3SS_MCS8,
|
MPT_RATE_VHT3SS_MCS9,
|
MPT_RATE_VHT4SS_MCS0,
|
MPT_RATE_VHT4SS_MCS1, /* #131 */
|
MPT_RATE_VHT4SS_MCS2,
|
MPT_RATE_VHT4SS_MCS3,
|
MPT_RATE_VHT4SS_MCS4,
|
MPT_RATE_VHT4SS_MCS5,
|
MPT_RATE_VHT4SS_MCS6, /* #136 */
|
MPT_RATE_VHT4SS_MCS7,
|
MPT_RATE_VHT4SS_MCS8,
|
MPT_RATE_VHT4SS_MCS9,
|
MPT_RATE_LAST
|
} MPT_RATE_E, *PMPT_RATE_E;
|
|
#define MAX_TX_PWR_INDEX_N_MODE 64 /* 0x3F */
|
|
#define MPT_IS_CCK_RATE(_value) (MPT_RATE_1M <= _value && _value <= MPT_RATE_11M)
|
#define MPT_IS_OFDM_RATE(_value) (MPT_RATE_6M <= _value && _value <= MPT_RATE_54M)
|
#define MPT_IS_HT_RATE(_value) (MPT_RATE_MCS0 <= _value && _value <= MPT_RATE_MCS31)
|
#define MPT_IS_HT_1S_RATE(_value) (MPT_RATE_MCS0 <= _value && _value <= MPT_RATE_MCS7)
|
#define MPT_IS_HT_2S_RATE(_value) (MPT_RATE_MCS8 <= _value && _value <= MPT_RATE_MCS15)
|
#define MPT_IS_HT_3S_RATE(_value) (MPT_RATE_MCS16 <= _value && _value <= MPT_RATE_MCS23)
|
#define MPT_IS_HT_4S_RATE(_value) (MPT_RATE_MCS24 <= _value && _value <= MPT_RATE_MCS31)
|
|
#define MPT_IS_VHT_RATE(_value) (MPT_RATE_VHT1SS_MCS0 <= _value && _value <= MPT_RATE_VHT4SS_MCS9)
|
#define MPT_IS_VHT_1S_RATE(_value) (MPT_RATE_VHT1SS_MCS0 <= _value && _value <= MPT_RATE_VHT1SS_MCS9)
|
#define MPT_IS_VHT_2S_RATE(_value) (MPT_RATE_VHT2SS_MCS0 <= _value && _value <= MPT_RATE_VHT2SS_MCS9)
|
#define MPT_IS_VHT_3S_RATE(_value) (MPT_RATE_VHT3SS_MCS0 <= _value && _value <= MPT_RATE_VHT3SS_MCS9)
|
#define MPT_IS_VHT_4S_RATE(_value) (MPT_RATE_VHT4SS_MCS0 <= _value && _value <= MPT_RATE_VHT4SS_MCS9)
|
|
#define MPT_IS_2SS_RATE(_rate) ((MPT_RATE_MCS8 <= _rate && _rate <= MPT_RATE_MCS15) || \
|
(MPT_RATE_VHT2SS_MCS0 <= _rate && _rate <= MPT_RATE_VHT2SS_MCS9))
|
#define MPT_IS_3SS_RATE(_rate) ((MPT_RATE_MCS16 <= _rate && _rate <= MPT_RATE_MCS23) || \
|
(MPT_RATE_VHT3SS_MCS0 <= _rate && _rate <= MPT_RATE_VHT3SS_MCS9))
|
#define MPT_IS_4SS_RATE(_rate) ((MPT_RATE_MCS24 <= _rate && _rate <= MPT_RATE_MCS31) || \
|
(MPT_RATE_VHT4SS_MCS0 <= _rate && _rate <= MPT_RATE_VHT4SS_MCS9))
|
|
typedef enum _POWER_MODE_ {
|
POWER_LOW = 0,
|
POWER_NORMAL
|
} POWER_MODE;
|
|
/* The following enumeration is used to define the value of Reg0xD00[30:28] or JaguarReg0x914[18:16]. */
|
typedef enum _OFDM_TX_MODE {
|
OFDM_ALL_OFF = 0,
|
OFDM_ContinuousTx = 1,
|
OFDM_SingleCarrier = 2,
|
OFDM_SingleTone = 4,
|
} OFDM_TX_MODE;
|
|
|
#define RX_PKT_BROADCAST 1
|
#define RX_PKT_DEST_ADDR 2
|
#define RX_PKT_PHY_MATCH 3
|
|
typedef enum _ENCRY_CTRL_STATE_ {
|
HW_CONTROL, /* hw encryption& decryption */
|
SW_CONTROL, /* sw encryption& decryption */
|
HW_ENCRY_SW_DECRY, /* hw encryption & sw decryption */
|
SW_ENCRY_HW_DECRY /* sw encryption & hw decryption */
|
} ENCRY_CTRL_STATE;
|
|
typedef enum _MPT_TXPWR_DEF {
|
MPT_CCK,
|
MPT_OFDM, /* L and HT OFDM */
|
MPT_OFDM_AND_HT,
|
MPT_HT,
|
MPT_VHT
|
} MPT_TXPWR_DEF;
|
|
|
#define IS_MPT_HT_RATE(_rate) (_rate >= MPT_RATE_MCS0 && _rate <= MPT_RATE_MCS31)
|
#define IS_MPT_VHT_RATE(_rate) (_rate >= MPT_RATE_VHT1SS_MCS0 && _rate <= MPT_RATE_VHT4SS_MCS9)
|
#define IS_MPT_CCK_RATE(_rate) (_rate >= MPT_RATE_1M && _rate <= MPT_RATE_11M)
|
#define IS_MPT_OFDM_RATE(_rate) (_rate >= MPT_RATE_6M && _rate <= MPT_RATE_54M)
|
|
typedef enum _mp_tx_pkt_payload{
|
MP_TX_Payload_00 = 0,
|
MP_TX_Payload_a5,
|
MP_TX_Payload_5a,
|
MP_TX_Payload_ff,
|
MP_TX_Payload_prbs9,
|
MP_TX_Payload_default_random
|
} mp_tx_pkt_payload;
|
|
/*************************************************************************/
|
#if 0
|
extern struct mp_xmit_frame *alloc_mp_xmitframe(struct mp_priv *pmp_priv);
|
extern int free_mp_xmitframe(struct xmit_priv *pxmitpriv, struct mp_xmit_frame *pmp_xmitframe);
|
#endif
|
/* SYNC to PHL MP define*/
|
/* mp command class */
|
enum rtw_mp_class {
|
RTW_MP_CLASS_CONFIG = 0,
|
RTW_MP_CLASS_TX = 1,
|
RTW_MP_CLASS_RX = 2,
|
RTW_MP_CLASS_EFUSE = 3,
|
RTW_MP_CLASS_REG = 4,
|
RTW_MP_CLASS_TXPWR = 5,
|
RTW_MP_CLASS_CAL = 6,
|
RTW_MP_CLASS_FLASH = 7,
|
RTW_MP_CLASS_MAX,
|
};
|
|
enum rtw_mp_tx_method {
|
RTW_MP_SW_TX = 0,
|
RTW_MP_PMACT_TX,
|
RTW_MP_TMACT_TX,
|
RTW_MP_FW_PMACT_TX,
|
};
|
|
enum rtw_mp_tx_cmd {
|
RTW_MP_TX_NONE = 0,
|
RTW_MP_TX_PACKETS,
|
RTW_MP_TX_CONTINUOUS,
|
RTW_MP_TX_SINGLE_TONE,
|
RTW_MP_TX_CCK_Carrier_Suppression,
|
RTW_MP_TX_CONFIG_PLCP_COMMON_INFO,
|
RTW_MP_TX_CMD_PHY_OK,
|
RTW_MP_TX_CONFIG_PLCP_PATTERN,
|
RTW_MP_TX_CONFIG_PLCP_USER_INFO,
|
RTW_MP_TX_TB_TEST,
|
RTW_MP_TX_DPD_BYPASS,
|
RTW_MP_TX_CHECK_TX_IDLE,
|
RTW_MP_TX_CMD_BB_LOOPBCK,
|
RTW_MP_TX_CMD_MAX,
|
};
|
|
/* mp config command */
|
enum rtw_mp_config_cmdid {
|
RTW_MP_CONFIG_CMD_GET_BW,
|
RTW_MP_CONFIG_CMD_GET_RF_STATUS,
|
RTW_MP_CONFIG_CMD_SET_RATE_IDX,
|
RTW_MP_CONFIG_CMD_SET_RF_TXRX_PATH,
|
RTW_MP_CONFIG_CMD_SET_RESET_PHY_COUNT,
|
RTW_MP_CONFIG_CMD_SET_RESET_MAC_COUNT,
|
RTW_MP_CONFIG_CMD_SET_RESET_DRV_COUNT,
|
RTW_MP_CONFIG_CMD_SET_TXRX_MODE,
|
RTW_MP_CONFIG_CMD_PBC,
|
RTW_MP_CONFIG_CMD_START_DUT,
|
RTW_MP_CONFIG_CMD_STOP_DUT,
|
RTW_MP_CONFIG_CMD_GET_MIMPO_RSSI,
|
RTW_MP_CONFIG_CMD_GET_BOARD_TYPE,
|
RTW_MP_CONFIG_CMD_GET_MODULATION,
|
RTW_MP_CONFIG_CMD_GET_RF_MODE,
|
RTW_MP_CONFIG_CMD_GET_RF_PATH,
|
RTW_MP_CONFIG_CMD_SET_MODULATION,
|
RTW_MP_CONFIG_CMD_GET_DEVICE_INFO,
|
RTW_MP_CONFIG_CMD_SET_PHY_INDEX,
|
RTW_MP_CONFIG_CMD_GET_MAC_ADDR,
|
RTW_MP_CONFIG_CMD_SET_MAC_ADDR,
|
RTW_MP_CONFIG_CMD_SET_CH_BW,
|
RTW_MP_CONFIG_CMD_GET_TX_NSS,
|
RTW_MP_CONFIG_CMD_GET_RX_NSS,
|
RTW_MP_CONFIG_CMD_SWITCH_BT_PATH,
|
RTW_MP_CONFIG_CMD_GET_RFE_TYPE,
|
RTW_MP_CONFIG_CMD_GET_DEV_IDX,
|
RTW_MP_CONFIG_CMD_TRIGGER_FW_CONFLICT,
|
RTW_MP_CONFIG_CMD_GET_UUID,
|
RTW_MP_CONFIG_CMD_SET_REGULATION,
|
RTW_MP_CONFIG_CMD_SET_BT_UART,
|
RTW_MP_CONFIG_CMD_SWITCH_ANTENNA,
|
RTW_MP_CONFIG_CMD_SET_MAC_LOOPBK_ENTER,
|
RTW_MP_CONFIG_CMD_SET_HCI_SPEED,
|
RTW_MP_CONFIG_CMD_GET_HCI_SPEED,
|
RTW_MP_CONFIG_CMD_SET_MAC_GENERNAL_IO_TEST,
|
RTW_MP_CONFIG_CMD_SET_MAC_L1SS_ENABLE,
|
RTW_MP_CONFIG_CMD_SET_GPIO,
|
RTW_MP_CONFIG_CMD_SET_MAC_LOOPBK_SPEED,
|
RTW_MP_CONFIG_CMD_MAX,
|
};
|
|
/* mp rx command */
|
enum rtw_mp_rx_cmd {
|
RTW_MP_RX_CMD_PHY_CRC_OK = 0,
|
RTW_MP_RX_CMD_PHY_CRC_ERR = 1,
|
RTW_MP_RX_CMD_MAC_CRC_OK = 2,
|
RTW_MP_RX_CMD_MAC_CRC_ERR = 3,
|
RTW_MP_RX_CMD_DRV_CRC_OK = 4,
|
RTW_MP_RX_CMD_DRV_CRC_ERR = 5,
|
RTW_MP_RX_CMD_GET_RSSI = 6,
|
RTW_MP_RX_CMD_GET_RXEVM = 7,
|
RTW_MP_RX_CMD_GET_PHYSTS = 8,
|
RTW_MP_RX_CMD_TRIGGER_RXEVM = 9,
|
RTW_MP_RX_CMD_SET_GAIN_OFFSET = 10,
|
RTW_MP_RX_CMD_GET_RSSI_EX = 11,
|
RTW_MP_RX_CMD_SET_RX_FLTR = 12,
|
RTW_MP_RX_CMD_MAX,
|
|
};
|
|
/* mp reg command */
|
enum rtw_mp_reg_cmd {
|
RTW_MP_REG_CMD_READ_MAC = 0,
|
RTW_MP_REG_CMD_WRITE_MAC = 1,
|
RTW_MP_REG_CMD_READ_RF = 2,
|
RTW_MP_REG_CMD_WRITE_RF = 3,
|
RTW_MP_REG_CMD_READ_SYN = 4,
|
RTW_MP_REG_CMD_WRITE_SYN = 5,
|
RTW_MP_REG_CMD_READ_BB = 6,
|
RTW_MP_REG_CMD_WRITE_BB = 7,
|
RTW_MP_REG_CMD_SET_XCAP = 8,
|
RTW_MP_REG_CMD_GET_XCAP = 9,
|
RTW_MP_REG_CMD_MAX,
|
};
|
|
/* mp tx power command */
|
enum rtw_mp_txpwr_cmd {
|
RTW_MP_TXPWR_CMD_READ_PWR_TABLE = 0,
|
RTW_MP_TXPWR_CMD_GET_PWR_TRACK_STATUS = 1,
|
RTW_MP_TXPWR_CMD_SET_PWR_TRACK_STATUS = 2,
|
RTW_MP_TXPWR_CMD_SET_TXPWR = 3,
|
RTW_MP_TXPWR_CMD_GET_TXPWR = 4,
|
RTW_MP_TXPWR_CMD_GET_TXPWR_INDEX = 5,
|
RTW_MP_TXPWR_CMD_GET_THERMAL = 6,
|
RTW_MP_TXPWR_CMD_GET_TSSI = 7,
|
RTW_MP_TXPWR_CMD_SET_TSSI = 8,
|
RTW_MP_TXPWR_CMD_GET_TXPWR_REF = 9,
|
RTW_MP_TXPWR_CMD_GET_TXPWR_REF_CW = 10,
|
RTW_MP_TXPWR_CMD_SET_TXPWR_INDEX = 11,
|
RTW_MP_TXPWR_CMD_GET_TXINFOPWR = 12,
|
RTW_MP_TXPWR_CMD_SET_RFMODE = 13,
|
RTW_MP_TXPWR_CMD_SET_TSSI_OFFSET = 14,
|
RTW_MP_TXPWR_CMD_GET_ONLINE_TSSI_DE = 15,
|
RTW_MP_TXPWR_CMD_SET_PWR_LMT_EN = 16,
|
RTW_MP_TXPWR_CMD_GET_PWR_LMT_EN = 17,
|
RTW_MP_TXPWR_CMD_SET_TX_POW_PATTERN_SHARP = 18,
|
RTW_MP_TXPWR_CMD_SET_TX_POW_TABLE_SWITCH = 19,
|
RTW_MP_TXPWR_CMD_MAX,
|
};
|
|
/*
|
enum rtw_mp_flash_cmd {
|
RTW_MP_FLASH_CMD_WIFI_READ,
|
RTW_MP_FLASH_CMD_WIFI_WRITE,
|
RTW_MP_FLASH_CMD_MAX,
|
};
|
*/
|
|
enum rtw_mp_cal_cmd {
|
RTW_MP_CAL_CMD_TRIGGER_CAL = 0,
|
RTW_MP_CAL_CMD_SET_CAPABILITY_CAL = 1,
|
RTW_MP_CAL_CMD_GET_CAPABILITY_CAL = 2,
|
RTW_MP_CAL_CMD_GET_TSSI_DE_VALUE = 3,
|
RTW_MP_CAL_CMD_SET_TSSI_DE_TX_VERIFY = 4,
|
RTW_MP_CAL_CMD_GET_TXPWR_FINAL_ABS = 5,
|
RTW_MP_CAL_CMD_TRIGGER_DPK_TRACKING = 6,
|
RTW_MP_CAL_CMD_SET_TSSI_AVG = 7,
|
RTW_MP_CAL_CMD_PSD_INIT = 8,
|
RTW_MP_CAL_CMD_PSD_RESTORE = 9,
|
RTW_MP_CAL_CMD_PSD_GET_POINT_DATA = 10,
|
RTW_MP_CAL_CMD_PSD_QUERY = 11,
|
RTW_MP_CAL_CMD_EVENT_TRIGGER = 12,
|
RTW_MP_CAL_CMD_TRIGGER_WATCHDOG_CAL = 13,
|
RTW_MP_CAL_CMD_MAX,
|
};
|
|
enum rtw_mp_pmac_mode {
|
RTW_MP_PMAC_NONE_TEST,
|
RTW_MP_PMAC_PKTS_TX,
|
RTW_MP_PMAC_PKTS_RX,
|
RTW_MP_PMAC_CONT_TX,
|
RTW_MP_PMAC_FW_TRIG_TX,
|
RTW_MP_PMAC_OFDM_SINGLE_TONE_TX,
|
RTW_MP_PMAC_CCK_CARRIER_SIPPRESSION_TX
|
};
|
|
enum rtw_mp_calibration_type {
|
RTW_MP_CAL_CHL_RFK = 0,
|
RTW_MP_CAL_DACK = 1,
|
RTW_MP_CAL_IQK = 2,
|
RTW_MP_CAL_LCK = 3,
|
RTW_MP_CAL_DPK = 4,
|
RTW_MP_CAL_DPK_TRACK = 5,
|
RTW_MP_CAL_TSSI = 6,
|
RTW_MP_CAL_GAPK = 7,
|
RTW_MP_CAL_MAX,
|
};
|
|
enum rtw_mp_ppdu_type {
|
RTW_MP_TYPE_CCK = 0,
|
RTW_MP_TYPE_LEGACY,
|
RTW_MP_TYPE_HT_MF,
|
RTW_MP_TYPE_HT_GF,
|
RTW_MP_TYPE_VHT,
|
RTW_MP_TYPE_HE_SU,
|
RTW_MP_TYPE_HE_ER_SU,
|
RTW_MP_TYPE_HE_MU_OFDMA,
|
RTW_MP_TYPE_HE_TB
|
};
|
|
typedef enum _mp_ant_path {
|
MP_ANTENNA_NONE = 0,
|
MP_ANTENNA_D = 1,
|
MP_ANTENNA_C = 2,
|
MP_ANTENNA_CD = 3,
|
MP_ANTENNA_B = 4,
|
MP_ANTENNA_BD = 5,
|
MP_ANTENNA_BC = 6,
|
MP_ANTENNA_BCD = 7,
|
MP_ANTENNA_A = 8,
|
MP_ANTENNA_AD = 9,
|
MP_ANTENNA_AC = 10,
|
MP_ANTENNA_ACD = 11,
|
MP_ANTENNA_AB = 12,
|
MP_ANTENNA_ABD = 13,
|
MP_ANTENNA_ABC = 14,
|
MP_ANTENNA_ABCD = 15
|
} mp_ant_path;
|
|
struct rtw_mp_mac_lbk_tx_rpt {
|
u32 total_cnt;
|
u32 idle_cnt;
|
u32 busy_cnt;
|
};
|
|
struct rtw_gpio_config_arg {
|
u8 gpio_mode;
|
u8 gpio_id;
|
u8 gpio_enable;
|
};
|
|
struct rtw_pwr_config_arg {
|
u8 pwr_state;
|
u8 pwr_lvl;
|
};
|
struct rtw_mp_cmd_arg {
|
u8 mp_class;
|
u8 cmd;
|
u8 cmd_ok;
|
u8 status;
|
};
|
|
#define RTW_MP_TEST_NAME_LEN 32
|
#define RTW_MP_TEST_RPT_RSN_LEN 32
|
|
struct rtw_mp_test_rpt {
|
char name[RTW_MP_TEST_NAME_LEN];
|
u8 status;
|
char rsn[RTW_MP_TEST_RPT_RSN_LEN];
|
u32 total_time; // in ms
|
};
|
|
|
|
struct rtw_mp_config_arg {
|
u8 mp_class;
|
u8 cmd;
|
u8 cmd_ok;
|
u8 status;
|
u8 channel;
|
u8 bandwidth;
|
u8 rate_idx;
|
u8 ant_tx;
|
u8 tx_rfpath;
|
u8 ant_rx;
|
u8 rx_rfpath;
|
u8 rf_path;
|
u8 get_rfstats;
|
u8 modulation;
|
u8 bustype;
|
u32 chipid;
|
u8 cur_phy;
|
u8 mac_addr[6];
|
u8 sc_idx;
|
u8 dbcc_en;
|
u8 btc_mode;
|
u8 rfe_type;
|
u8 dev_id;
|
u32 offset;
|
u8 voltag;
|
u8 band;
|
u32 uuid;
|
u8 regulation;
|
u8 frc_switch;
|
u8 is_tmac_mode;
|
u32 drv_ver;
|
u8 phy_idx;
|
u8 is_bt_uart;
|
u8 ant_sw;
|
u8 hci_speed;
|
struct rtw_gpio_config_arg gpio_cfg;
|
struct rtw_pwr_config_arg pwr_cfg;
|
};
|
|
struct rtw_mp_tx_arg {
|
u8 mp_class;
|
u8 cmd;
|
u8 cmd_ok;
|
u8 status;
|
u8 tx_method;
|
u8 plcp_ppdu_type; /*offline gen*/
|
u16 plcp_case_id; /*offline gen*/
|
u8 bCarrierSuppression;
|
u8 is_cck;
|
u8 start_tx;
|
u16 tx_cnt;
|
u16 period; /* us */
|
u16 tx_time; /* us */
|
u32 tx_ok;
|
u8 tx_path;
|
u8 tx_mode; /* mode: 0 = tmac, 1 = pmac */
|
u8 tx_concurrent_en; /* concurrent tx */
|
u8 phy_idx;
|
u8 dpd_bypass;
|
/* plcp info */
|
u32 dbw; /*0:BW20, 1:BW40, 2:BW80, 3:BW160/BW80+80*/
|
u32 source_gen_mode;
|
u32 locked_clk;
|
u32 dyn_bw;
|
u32 ndp_en;
|
u32 long_preamble_en; /*bmode*/
|
u32 stbc;
|
u32 gi; /*0:0.4,1:0.8,2:1.6,3:3.2*/
|
u32 tb_l_len;
|
u32 tb_ru_tot_sts_max;
|
u32 vht_txop_not_allowed;
|
u32 tb_disam;
|
u32 doppler;
|
u32 he_ltf_type; /*0:1x,1:2x,2:4x*/
|
u32 ht_l_len;
|
u32 preamble_puncture;
|
u32 he_mcs_sigb;/*0~5*/
|
u32 he_dcm_sigb;
|
u32 he_sigb_compress_en;
|
u32 max_tx_time_0p4us;
|
u32 ul_flag;
|
u32 tb_ldpc_extra;
|
u32 bss_color;
|
u32 sr;
|
u32 beamchange_en;
|
u32 he_er_u106ru_en;
|
u32 ul_srp1;
|
u32 ul_srp2;
|
u32 ul_srp3;
|
u32 ul_srp4;
|
u32 mode;
|
u32 group_id;
|
u32 ppdu_type;/*0: bmode,1:Legacy,2:HT_MF,3:HT_GF,4:VHT,5:HE_SU,6:HE_ER_SU,7:HE_MU,8:HE_TB*/
|
u32 txop;
|
u32 tb_strt_sts;
|
u32 tb_pre_fec_padding_factor;
|
u32 cbw;
|
u32 txsc;
|
u32 tb_mumimo_mode_en;
|
u32 nominal_t_pe; /* def = 2*/
|
u32 ness; /* def = 0*/
|
u32 n_user;
|
u32 tb_rsvd;/*def = 0*/
|
/* plcp user info */
|
u32 plcp_usr_idx;
|
u32 mcs;
|
u32 mpdu_len;
|
u32 n_mpdu;
|
u32 fec;
|
u32 dcm;
|
u32 aid;
|
u32 scrambler_seed; /* rand (1~255)*/
|
u32 random_init_seed; /* rand (1~255)*/
|
u32 apep;
|
u32 ru_alloc;
|
u32 nss;
|
u32 txbf;
|
u32 pwr_boost_db;
|
//struct mp_plcp_param_t plcp_param; /*online gen*/
|
u32 data_rate;
|
u8 plcp_sts;
|
|
/*HE-TB Test*/
|
u8 bSS_id_addr0;
|
u8 bSS_id_addr1;
|
u8 bSS_id_addr2;
|
u8 bSS_id_addr3;
|
u8 bSS_id_addr4;
|
u8 bSS_id_addr5;
|
u8 is_link_mode;
|
|
/* tx state*/
|
u8 tx_state;
|
|
/* bb loop back*/
|
u8 enable;
|
u8 is_dgt;
|
u8 cck_lbk_en;
|
u8 is_bt_link;
|
|
u32 puncture;
|
/* txsb */
|
u32 txsb;
|
u32 eht_mcs_sig;
|
|
/* sw tx*/
|
u8 mac_addr_0;
|
u8 mac_addr_1;
|
u8 mac_addr_2;
|
u8 mac_addr_3;
|
u8 mac_addr_4;
|
u8 mac_addr_5;
|
u32 sw_tx_payload_size;
|
|
/* ampdu control */
|
u8 ampdu_num;
|
u8 sw_tx_en;
|
|
/* mac loop back */
|
struct rtw_mp_mac_lbk_tx_rpt tx_rpt;
|
};
|
|
struct rtw_mp_rx_arg {
|
u8 mp_class;
|
u8 cmd;
|
u8 cmd_ok;
|
u8 status;
|
u32 rx_ok;
|
u32 rx_err;
|
u8 rssi;
|
u8 rx_path;
|
u8 rx_evm;
|
u8 user;
|
u8 strm;
|
u8 rxevm_table;
|
u8 enable;
|
u32 phy_user0_rxevm;
|
u32 phy_user1_rxevm;
|
u32 phy_user2_rxevm;
|
u32 phy_user3_rxevm;
|
s8 offset;
|
u8 rf_path;
|
u8 iscck;
|
s32 rssi_ex[4];
|
u8 rx_phy_idx;
|
u8 rx_fltr_addr[6];
|
u8 rx_fltr_enable;
|
};
|
|
enum rtw_mp_tssi_pwrtrk_type{
|
RTW_MP_TSSI_OFF = 0,
|
RTW_MP_TSSI_ON,
|
RTW_MP_TSSI_CAL
|
};
|
|
|
struct rtw_mp_reg_arg {
|
u8 mp_class;
|
u8 cmd;
|
u8 cmd_ok;
|
u8 status;
|
u32 io_offset;
|
u32 io_value;
|
u8 io_type;
|
u8 ofdm;
|
u8 rfpath;
|
u8 sc_xo;
|
u8 xsi_offset;
|
u8 xsi_value;
|
};
|
|
struct rtw_mp_txpwr_arg {
|
u8 mp_class;
|
u8 cmd;
|
u8 cmd_ok;
|
u8 status;
|
s16 txpwr;
|
u16 txpwr_index;
|
u8 txpwr_track_status;
|
u8 txpwr_status;
|
u32 tssi;
|
u8 thermal;
|
u8 rfpath;
|
u8 ofdm;
|
u8 tx_path;
|
u16 rate;
|
u8 bandwidth;
|
u8 channel;
|
s16 table_item; /*get an element of power table*/
|
u8 dcm;
|
u8 beamforming;
|
u8 offset;
|
s16 txpwr_ref;
|
u8 is_cck;
|
u8 rf_mode;
|
u32 tssi_de_offset;
|
s32 dbm;
|
s32 pout;
|
s32 online_tssi_de;
|
bool pwr_lmt_en;
|
u8 sharp_id;
|
u8 cur_phy;
|
};
|
|
struct rtw_mp_cal_arg {
|
u8 mp_class;
|
u8 cmd;
|
u8 cmd_ok;
|
u8 status;
|
u8 cal_type;
|
u8 enable;
|
u8 rfpath;
|
u16 io_value;
|
u8 channel;
|
u8 bandwidth;
|
s32 xdbm;
|
u8 path;
|
u8 iq_path;
|
u32 avg;
|
u32 fft;
|
s32 point;
|
u32 upoint;
|
u32 start_point;
|
u32 stop_point;
|
u32 buf;
|
u32 outbuf[400];
|
u8 event;
|
u8 func;
|
};
|
|
enum RTW_TEST_SUB_MODULE {
|
RTW_TEST_SUB_MODULE_MP = 0,
|
RTW_TEST_SUB_MODULE_FPGA = 1,
|
RTW_TEST_SUB_MODULE_VERIFY = 2,
|
RTW_TEST_SUB_MODULE_TOOL = 3,
|
RTW_TEST_SUB_MODULE_TRX = 4,
|
RTW_TEST_SUB_MODULE_UNKNOWN,
|
};
|
|
struct rtw_test_module_info {
|
u8 tm_type;
|
u8 tm_mode;
|
};
|
|
#define RTW_MAX_TEST_CMD_BUF 2000
|
struct rtw_mp_test_cmdbuf {
|
u8 type;
|
u16 len;
|
u8 buf[RTW_MAX_TEST_CMD_BUF];
|
};
|
|
enum rtw_mp_nss
|
{
|
MP_NSS1,
|
MP_NSS2,
|
MP_NSS3,
|
MP_NSS4
|
};
|
|
#define RU_TONE_STR(idx)\
|
(idx == MP_RU_TONE_26) ? "26-Tone" :\
|
(idx == MP_RU_TONE_52) ? "52-Tone" :\
|
(idx == MP_RU_TONE_106) ? "106-Tone" :\
|
(idx == MP_RU_TONE_242) ? "242-Tone" :\
|
(idx == MP_RU_TONE_484) ? "484-Tone" :\
|
(idx == MP_RU_TONE_996) ? "996-Tone" :\
|
"UNknow"
|
|
enum rtw_mp_resourceUnit
|
{
|
MP_RU_TONE_26,
|
MP_RU_TONE_52,
|
MP_RU_TONE_106,
|
MP_RU_TONE_242,
|
MP_RU_TONE_484,
|
MP_RU_TONE_996,
|
MP_RU_TONE_996X2,
|
MP_RU_TONE_HESIGB,
|
MP_RU_TONE_996X4,
|
MP_RU_TONE_52_26,
|
MP_RU_TONE_106_26,
|
MP_RU_TONE_484_242,
|
MP_RU_TONE_996_484,
|
MP_RU_TONE_996_484_242,
|
MP_RU_TONE_996X2_484,
|
MP_RU_TONE_996X3,
|
MP_RU_TONE_996X3_484
|
};
|
/* SYNC to PHL MP define END */
|
|
|
#define MP_IS_HT_HRATE(_rate) ((_rate) >= HRATE_MCS0 && (_rate) <= HRATE_MCS31)
|
#define MP_IS_VHT_HRATE(_rate) ((_rate) >= HRATE_VHT_NSS1_MCS0 && (_rate) <= HRATE_VHT_NSS4_MCS9)
|
#define MP_IS_CCK_HRATE(_rate) ((_rate) == HRATE_CCK1 || (_rate) == HRATE_CCK2 || \
|
(_rate) == HRATE_CCK5_5 || (_rate) == HRATE_CCK11)
|
|
#define MP_IS_OFDM_HRATE(_rate) ((_rate) >= HRATE_OFDM6 && (_rate) <= HRATE_OFDM54)
|
#define MP_IS_HE_HRATE(_rate) ((_rate) >= HRATE_HE_NSS1_MCS0 && (_rate) <= HRATE_HE_NSS4_MCS11)
|
|
#define MP_IS_HT1SS_HRATE(_rate) ((_rate) >= HRATE_MCS0 && (_rate) <= HRATE_MCS7)
|
#define MP_IS_HT2SS_HRATE(_rate) ((_rate) >= HRATE_MCS8 && (_rate) <= HRATE_MCS15)
|
#define MP_IS_HT3SS_HRATE(_rate) ((_rate) >= HRATE_MCS16 && (_rate) <= HRATE_MCS23)
|
#define MP_IS_HT4SS_HRATE(_rate) ((_rate) >= HRATE_MCS24 && (_rate) <= HRATE_MCS31)
|
|
#define MP_IS_VHT1SS_HRATE(_rate) ((_rate) >= HRATE_VHT_NSS1_MCS0 && (_rate) <= HRATE_VHT_NSS1_MCS9)
|
#define MP_IS_VHT2SS_HRATE(_rate) ((_rate) >= HRATE_VHT_NSS2_MCS0 && (_rate) <= HRATE_VHT_NSS2_MCS9)
|
#define MP_IS_VHT3SS_HRATE(_rate) ((_rate) >= HRATE_VHT_NSS3_MCS0 && (_rate) <= HRATE_VHT_NSS3_MCS9)
|
#define MP_IS_VHT4SS_HRATE(_rate) ((_rate) >= HRATE_VHT_NSS4_MCS0 && (_rate) <= HRATE_VHT_NSS4_MCS9)
|
|
#define MP_IS_HE1SS_HRATE(_rate) ((_rate) >= HRATE_HE_NSS1_MCS0 && (_rate) <= HRATE_HE_NSS1_MCS11)
|
#define MP_IS_HE2SS_HRATE(_rate) ((_rate) >= HRATE_HE_NSS2_MCS0 && (_rate) <= HRATE_HE_NSS2_MCS11)
|
#define MP_IS_HE3SS_HRATE(_rate) ((_rate) >= HRATE_HE_NSS3_MCS0 && (_rate) <= HRATE_HE_NSS3_MCS11)
|
#define MP_IS_HE4SS_HRATE(_rate) ((_rate) >= HRATE_HE_NSS4_MCS0 && (_rate) <= HRATE_HE_NSS4_MCS11)
|
|
#define MP_IS_1T_HRATE(_rate) (MP_IS_CCK_HRATE((_rate)) || MP_IS_OFDM_HRATE((_rate)) \
|
|| MP_IS_HT1SS_HRATE((_rate)) || MP_IS_VHT1SS_HRATE((_rate)) \
|
|| MP_IS_HE1SS_HRATE((_rate)))
|
|
#define MP_IS_2T_HRATE(_rate) (MP_IS_HT2SS_HRATE((_rate)) || MP_IS_VHT2SS_HRATE((_rate)) \
|
|| MP_IS_HE2SS_HRATE((_rate)))
|
|
#define MP_IS_3T_HRATE(_rate) (MP_IS_HT3SS_HRATE((_rate)) || MP_IS_VHT3SS_HRATE((_rate)) \
|
|| MP_IS_HE3SS_HRATE((_rate)))
|
|
#define MP_IS_4T_HRATE(_rate) (MP_IS_HT4SS_HRATE((_rate)) || MP_IS_VHT4SS_HRATE((_rate)) \
|
|| MP_IS_HE4SS_HRATE((_rate)))
|
|
|
|
void rtw_mp_get_phl_cmd(_adapter *padapter, void* buf, u32 buflen);
|
void rtw_mp_set_phl_cmd(_adapter *padapter, void* buf, u32 buflen);
|
|
bool rtw_mp_phl_config_arg(_adapter *padapter, enum rtw_mp_config_cmdid cmdid);
|
void rtw_mp_phl_rx_physts(_adapter *padapter, struct rtw_mp_rx_arg *rx_arg, bool bstart);
|
void rtw_mp_phl_rx_rssi(_adapter *padapter, struct rtw_mp_rx_arg *rx_arg);
|
void rtw_mp_phl_rx_gain_offset(_adapter *padapter, struct rtw_mp_rx_arg *rx_arg, u8 path_num);
|
void rtw_mp_phl_query_rx(_adapter *padapter, struct rtw_mp_rx_arg *rx_arg ,u8 rx_qurey_type);
|
u8 rtw_mp_phl_txpower(_adapter *padapter, struct rtw_mp_txpwr_arg *ptxpwr_arg, u8 cmdid);
|
void rtw_mp_set_crystal_cap(_adapter *padapter, u32 xcapvalue);
|
u8 rtw_mp_phl_calibration(_adapter *padapter, struct rtw_mp_cal_arg *pcal_arg, u8 cmdid);
|
u8 rtw_mp_phl_reg(_adapter *padapter, struct rtw_mp_reg_arg *reg_arg, u8 cmdid);
|
|
|
u8 rtw_update_giltf(_adapter *padapter);
|
void rtw_mp_update_coding(_adapter *padapter);
|
u8 rtw_mp_update_ru_tone(_adapter *padapter);
|
u8 rtw_mp_update_ru_alloc(_adapter *padapter);
|
|
bool rtw_mp_is_cck_rate(u16 rate);
|
|
extern s32 init_mp_priv(_adapter *padapter);
|
extern void free_mp_priv(struct mp_priv *pmp_priv);
|
extern s32 MPT_InitializeAdapter(_adapter *padapter, u8 Channel);
|
extern void MPT_DeInitAdapter(_adapter *padapter);
|
extern s32 mp_start_test(_adapter *padapter);
|
extern void mp_stop_test(_adapter *padapter);
|
|
|
extern void write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val);
|
extern u32 read_rfreg(_adapter *padapter, u8 rfpath, u32 addr);
|
extern void write_rfreg(_adapter *padapter, u8 rfpath, u32 addr, u32 val);
|
#ifdef CONFIG_ANTENNA_DIVERSITY
|
u8 rtw_mp_set_antdiv(_adapter *padapter, BOOLEAN bMain);
|
#endif
|
void SetChannel(_adapter *adapter);
|
void SetBandwidth(_adapter *adapter);
|
int rtw_mp_txpoweridx(_adapter *adapter);
|
u16 rtw_mp_txpower_dbm(_adapter *adapter, u8 rf_path);
|
u16 rtw_mp_get_pwrtab_dbm(_adapter *adapter, u8 rfpath);
|
|
void SetAntenna(_adapter *adapter);
|
void SetDataRate(_adapter *adapter);
|
s32 SetThermalMeter(_adapter *adapter, u8 target_ther);
|
void GetThermalMeter(_adapter *adapter, u8 rfpath ,u8 *value);
|
void GetUuid(_adapter *adapter, u32 *uuid);
|
void SetGpio(_adapter *padapter);
|
void rtw_mp_continuous_tx(_adapter *adapter, u8 bstart);
|
void rtw_mp_singlecarrier_tx(_adapter *adapter, u8 bstart);
|
void rtw_mp_singletone_tx(_adapter *adapter, u8 bstart);
|
void rtw_mp_carriersuppr_tx(_adapter *adapter, u8 bstart);
|
void rtw_mp_txpwr_level(_adapter *adapter);
|
void fill_txdesc_for_mp(_adapter *padapter, u8 *ptxdesc);
|
void rtw_set_phl_packet_tx(_adapter *padapter, u8 bStart);
|
void rtw_pre_phl_packet_tx(_adapter *padapter, u8 bStart);
|
|
u8 rtw_phl_mp_tx_cmd(_adapter *padapter, enum rtw_mp_tx_cmd cmdid,
|
enum rtw_mp_tx_method tx_method, boolean bstart);
|
|
void rtw_mp_set_packet_tx(_adapter *padapter);
|
void rtw_mp_reset_phy_count(_adapter *adapter);
|
|
s32 SetPowerTracking(_adapter *padapter, u8 enable);
|
void GetPowerTracking(_adapter *padapter, u8 *enable);
|
u32 mp_query_psd(_adapter *adapter, u8 *data);
|
void rtw_mp_trigger_iqk(_adapter *padapter);
|
void rtw_mp_trigger_lck(_adapter *padapter);
|
void rtw_mp_trigger_dpk(_adapter *padapter);
|
u8 rtw_mp_mode_check(_adapter *padapter);
|
bool rtw_is_mp_tssitrk_on(_adapter *adapter);
|
|
void mpt_ProSetPMacTx(_adapter *adapter);
|
void MP_PHY_SetRFPathSwitch(_adapter *adapter , BOOLEAN bMain);
|
void mp_phy_switch_rf_path_set(_adapter *adapter , u8 *pstate);
|
u8 MP_PHY_QueryRFPathSwitch(_adapter *adapter);
|
u32 mpt_ProQueryCalTxPower(_adapter *adapter, u8 RfPath);
|
u8 mpt_to_mgnt_rate(u32 MptRateIdx);
|
u16 rtw_mp_rate_parse(_adapter *adapter, u8 *target_str);
|
u32 mp_join(_adapter *padapter, u8 mode);
|
u32 hal_mpt_query_phytxok(_adapter *adapter);
|
u32 rtw_mpt_raw2dec_dbm(u32 val);
|
u32 mpt_get_tx_power_finalabs_val(_adapter *padapter, u8 rf_path);
|
void mpt_trigger_tssi_tracking(_adapter *adapter, u8 rf_path);
|
u8 rtw_mpt_set_power_limit_en(_adapter *padapter, bool en_val);
|
bool rtw_mpt_get_power_limit_en(_adapter *padapter);
|
|
u32 rtw_mp_get_tssi_de(_adapter *padapter, u8 rf_path);
|
s32 rtw_mp_get_online_tssi_de(_adapter *padapter, s32 out_pwr, s32 tgdbm, u8 rf_path);
|
u8 rtw_mp_set_tsside2verify(_adapter *padapter, u32 tssi_de, u8 rf_path);
|
u8 rtw_mp_set_tssi_offset(_adapter *padapter, u32 tssi_offset, u8 rf_path);
|
u8 rtw_mp_set_tssi_pwrtrk(_adapter *padapter, u8 tssi_state);
|
u8 rtw_mp_get_tssi_pwrtrk(_adapter *padapter);
|
u8 rtw_mp_set_tx_shape_idx(_adapter *padapter);
|
|
void rtw_mp_cal_trigger(_adapter *padapter, u8 cal_tye);
|
void rtw_mp_cal_capab(_adapter *padapter, u8 cal_tye, u8 benable);
|
|
void rtw_mp_rx_phl_cal_timer(_adapter *padapter);
|
void rtw_mp_halt(_adapter *padapter);
|
|
void rtw_mp_phl_set_mac_loopbk(_adapter *padapter);
|
void rtw_mp_phl_set_mac_loopbk_speed(_adapter *padapter);
|
void rtw_mp_phl_set_mac_io_test(_adapter *padapter);
|
|
u8 rtw_mp_get_tx_req_recycle(_adapter *padapter);
|
|
thread_return mp_xmit_phl_packet_thread(thread_context context);
|
|
void
|
PMAC_Get_Pkt_Param(
|
PRT_PMAC_TX_INFO pPMacTxInfo,
|
PRT_PMAC_PKT_INFO pPMacPktInfo
|
);
|
void
|
CCK_generator(
|
PRT_PMAC_TX_INFO pPMacTxInfo,
|
PRT_PMAC_PKT_INFO pPMacPktInfo
|
);
|
void
|
PMAC_Nsym_generator(
|
PRT_PMAC_TX_INFO pPMacTxInfo,
|
PRT_PMAC_PKT_INFO pPMacPktInfo
|
);
|
void
|
L_SIG_generator(
|
u32 N_SYM, /* Max: 750*/
|
PRT_PMAC_TX_INFO pPMacTxInfo,
|
PRT_PMAC_PKT_INFO pPMacPktInfo
|
);
|
|
void HT_SIG_generator(
|
PRT_PMAC_TX_INFO pPMacTxInfo,
|
PRT_PMAC_PKT_INFO pPMacPktInfo);
|
|
void VHT_SIG_A_generator(
|
PRT_PMAC_TX_INFO pPMacTxInfo,
|
PRT_PMAC_PKT_INFO pPMacPktInfo);
|
|
void VHT_SIG_B_generator(
|
PRT_PMAC_TX_INFO pPMacTxInfo);
|
|
void VHT_Delimiter_generator(
|
PRT_PMAC_TX_INFO pPMacTxInfo);
|
|
u8 rtw_do_mp_iwdata_len_chk(const char *caller, u32 len);
|
|
int rtw_mp_write_reg(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
|
int rtw_mp_read_reg(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
|
int rtw_mp_write_rf(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
|
int rtw_mp_read_rf(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
|
int rtw_mp_start(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
|
int rtw_mp_stop(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
|
int rtw_mp_rate(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
|
int rtw_mp_channel(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
|
int rtw_mp_trxsc_offset(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
|
int rtw_mp_bandwidth(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
|
int rtw_mp_txpower_index(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
|
int rtw_mp_txpower(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
|
int rtw_mp_ant_tx(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
|
int rtw_mp_ant_rx(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
|
int rtw_set_ctx_destAddr(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
|
int rtw_mp_ctx(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
|
int rtw_mp_disable_bt_coexist(struct net_device *dev,
|
struct iw_request_info *info,
|
union iwreq_data *wrqu, char *extra);
|
int rtw_mp_disable_bt_coexist(struct net_device *dev,
|
struct iw_request_info *info,
|
union iwreq_data *wrqu, char *extra);
|
int rtw_mp_arx(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
|
int rtw_mp_trx_query(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
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int rtw_mp_pwrtrk(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
|
int rtw_mp_psd(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
|
int rtw_mp_thermal(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
|
int rtw_mp_UUID(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
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int rtw_mp_reset_stats(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
|
int rtw_mp_dump(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
|
int rtw_mp_phypara(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
|
int rtw_mp_SetRFPath(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
|
int rtw_mp_switch_rf_path(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
|
int rtw_mp_link(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
|
int rtw_mp_QueryDrv(struct net_device *dev,
|
struct iw_request_info *info,
|
union iwreq_data *wrqu, char *extra);
|
int rtw_mp_PwrCtlDM(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
|
int rtw_mp_getver(struct net_device *dev,
|
struct iw_request_info *info,
|
union iwreq_data *wrqu, char *extra);
|
int rtw_mp_mon(struct net_device *dev,
|
struct iw_request_info *info,
|
union iwreq_data *wrqu, char *extra);
|
int rtw_mp_pwrlmt(struct net_device *dev,
|
struct iw_request_info *info,
|
union iwreq_data *wrqu, char *extra);
|
int rtw_mp_dpk_track(struct net_device *dev,
|
struct iw_request_info *info,
|
union iwreq_data *wrqu, char *extra);
|
int rtw_mp_dpk(struct net_device *dev,
|
struct iw_request_info *info,
|
union iwreq_data *wrqu, char *extra);
|
int rtw_mp_mac_loopbk(struct net_device *dev,
|
struct iw_request_info *info,
|
union iwreq_data *wrqu, char *extra);
|
int rtw_mp_mac_iotest(struct net_device *dev,
|
struct iw_request_info *info,
|
union iwreq_data *wrqu, char *extra);
|
#if 0
|
int rtw_efuse_mask_file(struct net_device *dev,
|
struct iw_request_info *info,
|
union iwreq_data *wrqu, char *extra);
|
int rtw_bt_efuse_mask_file(struct net_device *dev,
|
struct iw_request_info *info,
|
union iwreq_data *wrqu, char *extra);
|
|
int rtw_efuse_file_map(struct net_device *dev,
|
struct iw_request_info *info,
|
union iwreq_data *wrqu, char *extra);
|
int rtw_efuse_file_map_store(struct net_device *dev,
|
struct iw_request_info *info,
|
union iwreq_data *wrqu, char *extra);
|
int rtw_bt_efuse_file_map(struct net_device *dev,
|
struct iw_request_info *info,
|
union iwreq_data *wrqu, char *extra);
|
#endif
|
|
int rtw_mp_SetBT(struct net_device *dev,
|
struct iw_request_info *info,
|
union iwreq_data *wrqu, char *extra);
|
int rtw_mp_pretx_proc(_adapter *padapter, u8 bStartTest, char *extra);
|
int rtw_mp_tx(struct net_device *dev,
|
struct iw_request_info *info,
|
union iwreq_data *wrqu, char *extra);
|
int rtw_mp_rx(struct net_device *dev,
|
struct iw_request_info *info,
|
union iwreq_data *wrqu, char *extra);
|
int rtw_mp_hwtx(struct net_device *dev,
|
struct iw_request_info *info,
|
union iwreq_data *wrqu, char *extra);
|
u8 rtw_mp_hwrate2mptrate(u8 rate);
|
int rtw_mp_iqk(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
|
int rtw_mp_lck(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
|
int rtw_mp_get_tsside(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
|
int rtw_mp_set_tsside(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
|
|
int rtw_priv_mp_set(struct net_device *dev,
|
struct iw_request_info *info,
|
union iwreq_data *wdata, char *extra);
|
|
int rtw_priv_mp_get(struct net_device *dev,
|
struct iw_request_info *info,
|
union iwreq_data *wdata, char *extra);
|
|
int rtw_mp_set_phl_io(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
|
|
int rtw_mp_get_phl_io(struct net_device *dev,
|
struct iw_request_info *info,
|
struct iw_point *wrqu, char *extra);
|
|
int rtw_mp_tx_pattern_idx(struct net_device *dev,
|
struct iw_request_info *info,
|
union iwreq_data *wrqu, char *extra);
|
|
int rtw_mp_tx_plcp_tx_data(struct net_device *dev,
|
struct iw_request_info *info,
|
union iwreq_data *wrqu, char *extra);
|
|
int rtw_mp_tx_plcp_tx_user(struct net_device *dev,
|
struct iw_request_info *info,
|
union iwreq_data *wrqu, char *extra);
|
|
int rtw_mp_tx_method(struct net_device *dev,
|
struct iw_request_info *info,
|
union iwreq_data *wrqu, char *extra);
|
|
int rtw_mp_config_phy(struct net_device *dev,
|
struct iw_request_info *info,
|
union iwreq_data *wrqu, char *extra);
|
|
int rtw_mp_phl_rfk(struct net_device *dev,
|
struct iw_request_info *info,
|
union iwreq_data *wrqu, char *extra);
|
int rtw_mp_phl_btc_path(struct net_device *dev,
|
struct iw_request_info *info,
|
union iwreq_data *wrqu, char *extra);
|
int rtw_mp_get_he(struct net_device *dev,
|
struct iw_request_info *info,
|
union iwreq_data *wrqu, char *extra);
|
int rtw_mp_band(struct net_device *dev,
|
struct iw_request_info *info,
|
union iwreq_data *wrqu, char *extra);
|
void rtw_mp_phl_rx_reset_fltr(_adapter *padapter,
|
struct rtw_mp_rx_arg *rx_arg,
|
bool bstart);
|
#endif /* _RTW_MP_H_ */
|
