/* SPDX-License-Identifier: GPL-2.0 */
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/******************************************************************************
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*
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* Copyright(c) 2016 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#define _RTL8821CS_HALINIT_C_
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#include <drv_types.h> /* PADAPTER, basic_types.h and etc. */
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#include <hal_data.h> /* HAL_DATA_TYPE */
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#include "../rtl8821c.h" /* rtl8821c_mac_init(), rtl8821c_phy_init() and etc. */
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#include "../../hal_halmac.h" /* rtw_halmac_get_oqt_size*/
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/*
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#define HALMAC_NORMAL_HPQ_PGNUM_8821C 16
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#define HALMAC_NORMAL_NPQ_PGNUM_8821C 16
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#define HALMAC_NORMAL_LPQ_PGNUM_8821C 16
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#define HALMAC_NORMAL_EXPQ_PGNUM_8821C 14
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#define HALMAC_NORMAL_GAP_PGNUM_8821C 1
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case HALMAC_TRX_MODE_NORMAL:
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pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO] = HALMAC_DMA_MAPPING_NORMAL;
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pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI] = HALMAC_DMA_MAPPING_NORMAL;
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pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE] = HALMAC_DMA_MAPPING_LOW;
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pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK] = HALMAC_DMA_MAPPING_LOW;
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pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG] = HALMAC_DMA_MAPPING_EXTRA;
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pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = HALMAC_DMA_MAPPING_HIGH;
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*/
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static void rtl8821cs_init_xmit_info(_adapter *adapter)
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{
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PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
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u32 page_size;
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rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, &page_size);
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hal_data->tx_high_page = rtw_read16(adapter, REG_FIFOPAGE_INFO_1) & 0xFFF;
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hal_data->tx_low_page = rtw_read16(adapter, REG_FIFOPAGE_INFO_2) & 0xFFF;
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hal_data->tx_normal_page = rtw_read16(adapter, REG_FIFOPAGE_INFO_3) & 0xFFF;
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hal_data->tx_extra_page = rtw_read16(adapter, REG_FIFOPAGE_INFO_4) & 0xFFF;
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hal_data->tx_pub_page = rtw_read16(adapter, REG_FIFOPAGE_INFO_5) & 0xFFF;
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#ifdef DBG_DUMP_RQPN
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{
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u32 tx_fifo_size;
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rtw_halmac_get_tx_fifo_size(adapter_to_dvobj(adapter), &tx_fifo_size);
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RTW_INFO("%s => High Pages:%d, LOW Pages:%d, Normal Pages:%d, Extra Pages:%d, Pub Pages:%d, Total Pages:%d\n"
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, __func__
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, hal_data->tx_high_page
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, hal_data->tx_low_page
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, hal_data->tx_normal_page
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, hal_data->tx_extra_page
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, hal_data->tx_pub_page
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, (tx_fifo_size / page_size));
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}
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#endif
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hal_data->max_xmit_page = PageNum(MAX_XMITBUF_SZ, page_size);
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if (adapter->registrypriv.wifi_spec) {
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/*HALMAC_TRX_MODE_WMM - VO - HQ , VI - NQ , BE - LQ , BK - NQ , MG - HQ , HI -HQ*/
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hal_data->max_xmit_page_vo = hal_data->tx_high_page + hal_data->tx_pub_page;
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hal_data->max_xmit_page_vi = (hal_data->tx_normal_page + hal_data->tx_pub_page) >> 1;
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hal_data->max_xmit_page_be = hal_data->tx_low_page + hal_data->tx_pub_page;
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hal_data->max_xmit_page_bk = (hal_data->tx_normal_page + hal_data->tx_pub_page) >> 1;
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} else {
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/*HALMAC_TRX_MODE_NORMAL - VO - NQ , VI - NQ , BE - LQ , BK - LQ , MG - EXQ , HI -HQ*/
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#ifdef XMIT_BUF_SIZE
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hal_data->max_xmit_size_vovi = ((hal_data->tx_normal_page + hal_data->tx_pub_page) >> 1) * page_size;
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hal_data->max_xmit_size_bebk = ((hal_data->tx_low_page + hal_data->tx_pub_page) >> 1) * page_size;
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#endif
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hal_data->max_xmit_page_vo = (hal_data->tx_normal_page + hal_data->tx_pub_page) >> 1;
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hal_data->max_xmit_page_vi = (hal_data->tx_normal_page + hal_data->tx_pub_page) >> 1;
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hal_data->max_xmit_page_be = (hal_data->tx_low_page + hal_data->tx_pub_page) >> 1;
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hal_data->max_xmit_page_bk = (hal_data->tx_low_page + hal_data->tx_pub_page) >> 1;
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}
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#ifdef DBG_DUMP_RQPN
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#ifdef XMIT_BUF_SIZE
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RTW_INFO("%s => max_xmit_size_vovi:%d, max_xmit_size_bebk:%d\n", __func__, hal_data->max_xmit_size_vovi, hal_data->max_xmit_size_bebk);
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#endif
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RTW_INFO("%s => VO max_xmit_page:%d, VI max_xmit_page:%d\n", __func__, hal_data->max_xmit_page_vo, hal_data->max_xmit_page_vi);
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RTW_INFO("%s => BE max_xmit_page:%d, BK max_xmit_page:%d\n", __func__, hal_data->max_xmit_page_be, hal_data->max_xmit_page_bk);
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#endif
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if (rtw_halmac_get_oqt_size(adapter_to_dvobj(adapter), &hal_data->max_oqt_size)) {
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RTW_WARN("%s: Fail to get Max OQT size! use default max-size : 32\n", __func__);
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hal_data->max_oqt_size = 32;
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}
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}
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#ifdef CONFIG_FWLPS_IN_IPS
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u8 rtl8821cs_fw_ips_init(_adapter *padapter)
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{
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struct sreset_priv *psrtpriv = &GET_HAL_DATA(padapter)->srestpriv;
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struct debug_priv *pdbgpriv = &adapter_to_dvobj(padapter)->drv_dbg;
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struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
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if (pwrctl->bips_processing == _TRUE && psrtpriv->silent_reset_inprogress == _FALSE
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&& GET_HAL_DATA(padapter)->bFWReady == _TRUE && pwrctl->pre_ips_type == 0) {
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systime start_time;
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u8 cpwm_orig, cpwm_now, rpwm;
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u8 bMacPwrCtrlOn = _TRUE;
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RTW_INFO("%s: Leaving FW_IPS\n", __func__);
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/* for polling cpwm */
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cpwm_orig = 0;
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rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig);
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/* set rpwm */
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rtw_hal_get_hwreg(padapter, HW_VAR_RPWM_TOG, &rpwm);
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rpwm += 0x80;
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rpwm |= PS_ACK;
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rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&rpwm));
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RTW_INFO("%s: write rpwm=%02x\n", __func__, rpwm);
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pwrctl->tog = (rpwm + 0x80) & 0x80;
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/* do polling cpwm */
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start_time = rtw_get_current_time();
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do {
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rtw_mdelay_os(1);
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rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_now);
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if ((cpwm_orig ^ cpwm_now) & 0x80) {
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#ifdef DBG_CHECK_FW_PS_STATE
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RTW_INFO("%s: polling cpwm ok when leaving IPS in FWLPS state, cpwm_orig=%02x, cpwm_now=%02x, 0x100=0x%x\n"
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, __func__, cpwm_orig, cpwm_now, rtw_read8(padapter, REG_CR));
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#endif /* DBG_CHECK_FW_PS_STATE */
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break;
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}
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if (rtw_get_passing_time_ms(start_time) > 100) {
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RTW_INFO("%s: polling cpwm timeout when leaving IPS in FWLPS state\n", __func__);
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break;
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}
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} while (1);
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rtl8821c_set_FwPwrModeInIPS_cmd(padapter, 0);
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rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
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#ifdef DBG_CHECK_FW_PS_STATE
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if (rtw_fw_ps_state(padapter) == _FAIL) {
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RTW_INFO("after hal init, fw ps state in 32k\n");
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pdbgpriv->dbg_ips_drvopen_fail_cnt++;
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}
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#endif /* DBG_CHECK_FW_PS_STATE */
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return _SUCCESS;
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}
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return _FAIL;
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}
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u8 rtl8821cs_fw_ips_deinit(_adapter *padapter)
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{
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struct sreset_priv *psrtpriv = &GET_HAL_DATA(padapter)->srestpriv;
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struct debug_priv *pdbgpriv = &adapter_to_dvobj(padapter)->drv_dbg;
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struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
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if (pwrctl->bips_processing == _TRUE && psrtpriv->silent_reset_inprogress == _FALSE
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&& GET_HAL_DATA(padapter)->bFWReady == _TRUE && padapter->netif_up == _TRUE) {
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int cnt = 0;
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u8 val8 = 0, rpwm;
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RTW_INFO("%s: issue H2C to FW when entering IPS\n", __func__);
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rtl8821c_set_FwPwrModeInIPS_cmd(padapter, 0x1);
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/* poll 0x1cc to make sure H2C command already finished by FW; MAC_0x1cc=0 means H2C done by FW. */
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do {
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val8 = rtw_read8(padapter, REG_HMETFR);
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cnt++;
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RTW_INFO("%s polling REG_HMETFR=0x%x, cnt=%d\n", __func__, val8, cnt);
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rtw_mdelay_os(10);
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} while (cnt < 100 && (val8 != 0));
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/* H2C done, enter 32k */
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if (val8 == 0) {
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/* set rpwm to enter 32k */
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rtw_hal_get_hwreg(padapter, HW_VAR_RPWM_TOG, &rpwm);
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rpwm += 0x80;
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rpwm |= BIT_SYS_CLK_8821C;
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rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&rpwm));
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RTW_INFO("%s: write rpwm=%02x\n", __func__, rpwm);
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pwrctl->tog = (val8 + 0x80) & 0x80;
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cnt = val8 = 0;
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do {
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val8 = rtw_read8(padapter, REG_CR);
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cnt++;
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RTW_INFO("%s polling 0x100=0x%x, cnt=%d\n", __func__, val8, cnt);
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rtw_mdelay_os(10);
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} while (cnt < 100 && (val8 != 0xEA));
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#ifdef DBG_CHECK_FW_PS_STATE
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if (val8 != 0xEA)
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RTW_INFO("MAC_1C0=%08x, MAC_1C4=%08x, MAC_1C8=%08x, MAC_1CC=%08x\n"
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, rtw_read32(padapter, 0x1c0), rtw_read32(padapter, 0x1c4)
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, rtw_read32(padapter, 0x1c8), rtw_read32(padapter, REG_HMETFR));
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#endif /* DBG_CHECK_FW_PS_STATE */
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} else {
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RTW_INFO("MAC_1C0=%08x, MAC_1C4=%08x, MAC_1C8=%08x, MAC_1CC=%08x\n"
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, rtw_read32(padapter, 0x1c0), rtw_read32(padapter, 0x1c4)
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, rtw_read32(padapter, 0x1c8), rtw_read32(padapter, REG_HMETFR));
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}
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RTW_INFO("polling done when entering IPS, check result : 0x100=0x%x, cnt=%d, MAC_1cc=0x%02x\n"
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, rtw_read8(padapter, REG_CR), cnt, rtw_read8(padapter, REG_HMETFR));
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pwrctl->pre_ips_type = 0;
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return _SUCCESS;
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}
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pdbgpriv->dbg_carddisable_cnt++;
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pwrctl->pre_ips_type = 1;
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return _FAIL;
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}
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#endif /*CONFIG_FWLPS_IN_IPS*/
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#define MAX_AMPDU_NUMBER 0x1212 /*MAX AMPDU Number = 18*/
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static void rtl8821cs_ampdu_num_cfg(_adapter *adapter)
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{
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struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
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PSDIO_DATA psdio_data = &dvobj->intf_data;
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u16 ampdu_num = MAX_AMPDU_NUMBER;
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if (psdio_data->clock < RTW_SDIO_CLK_80M)
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ampdu_num = 0x1F1F;
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rtw_write16(adapter, REG_PROT_MODE_CTRL_8821C + 2, ampdu_num);
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}
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static void rtl8821cs_init_misc(_adapter *adapter)
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{
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#ifdef DBG_DL_FW_MEM
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rtw_write8(adapter, 0xf6, 0x01);
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rtw_write8(adapter, 0x3a, 0x28);
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#endif
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#ifdef CONFIG_BT_WAKE_HST_OPEN_DRAIN
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/*PAD Type control select for GPIO14 (DEV_WAKE_HST) in USB or SDIO interface
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0: Push-Pull , 1: Open-Drain*/
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rtw_write32(adapter, REG_WL_BT_PWR_CTRL,
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rtw_read32(adapter, REG_WL_BT_PWR_CTRL) | BIT_DEVWAKE_PAD_TYPE_SEL);
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#endif
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rtl8821cs_ampdu_num_cfg(adapter);
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}
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u32 rtl8821cs_hal_init(PADAPTER adapter)
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{
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#ifdef CONFIG_FWLPS_IN_IPS
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if (_SUCCESS == rtl8821cs_fw_ips_init(adapter))
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return _SUCCESS;
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#endif
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if (_FALSE == rtl8821c_hal_init(adapter))
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return _FAIL;
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rtl8821cs_init_xmit_info(adapter);
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rtl8821cs_init_misc(adapter);
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return _SUCCESS;
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}
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u32 rtl8821cs_hal_deinit(PADAPTER adapter)
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{
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#ifdef CONFIG_FWLPS_IN_IPS
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if (_SUCCESS == rtl8821cs_fw_ips_deinit(adapter))
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return _SUCCESS;
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#endif
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return rtl8821c_hal_deinit(adapter);
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}
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void rtl8821cs_init_default_value(PADAPTER adapter)
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{
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PHAL_DATA_TYPE hal;
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hal = GET_HAL_DATA(adapter);
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rtl8821c_init_default_value(adapter);
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/* interface related variable */
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hal->SdioRxFIFOCnt = 0;
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}
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