/* SPDX-License-Identifier: GPL-2.0 */
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/******************************************************************************
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*
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* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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******************************************************************************/
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#include "halmac_sdio_88xx.h"
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#include "halmac_88xx_cfg.h"
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#if (HALMAC_88XX_SUPPORT && HALMAC_SDIO_SUPPORT)
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/* define the SDIO Bus CLK threshold */
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/* for avoiding CMD53 fails that result from SDIO CLK sync to ana_clk fail */
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#define SDIO_CLK_HIGH_SPEED_TH 50 /* 50MHz */
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#define SDIO_CLK_SPEED_MAX 208 /* 208MHz */
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/*only for r_indir_sdio_88xx !!, Soar 20171222*/
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static u8
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r_indir_cmd52_88xx(struct halmac_adapter *adapter, u32 offset);
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/*only for r_indir_sdio_88xx !!, Soar 20171222*/
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static u32
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r_indir_cmd53_88xx(struct halmac_adapter *adapter, u32 offset);
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/*only for r_indir_sdio_88xx !!, Soar 20171222*/
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static u32
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r8_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr);
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/*only for r_indir_sdio_88xx !!, Soar 20171222*/
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static u32
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r16_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr);
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/*only for r_indir_sdio_88xx !!, Soar 20171222*/
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static u32
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r32_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr);
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/*only for w_indir_sdio_88xx !!, Soar 20171222*/
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static enum halmac_ret_status
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w_indir_cmd52_88xx(struct halmac_adapter *adapter, u32 adr, u32 val,
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enum halmac_io_size size);
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/*only for w_indir_sdio_88xx !!, Soar 20171222*/
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static enum halmac_ret_status
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w_indir_cmd53_88xx(struct halmac_adapter *adapter, u32 adr, u32 val,
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enum halmac_io_size size);
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/*only for w_indir_sdio_88xx !!, Soar 20171222*/
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static enum halmac_ret_status
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w8_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val);
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/*only for w_indir_sdio_88xx !!, Soar 20171222*/
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static enum halmac_ret_status
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w16_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val);
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/*only for w_indir_sdio_88xx !!, Soar 20171222*/
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static enum halmac_ret_status
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w32_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val);
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/**
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* init_sdio_cfg_88xx() - init SDIO
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* @adapter : the adapter of halmac
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* Author : KaiYuan Chang/Ivan Lin
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* Return : enum halmac_ret_status
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* More details of status code can be found in prototype document
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*/
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enum halmac_ret_status
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init_sdio_cfg_88xx(struct halmac_adapter *adapter)
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{
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return HALMAC_RET_SUCCESS;
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}
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/**
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* deinit_sdio_cfg_88xx() - deinit SDIO
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* @adapter : the adapter of halmac
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* Author : KaiYuan Chang/Ivan Lin
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* Return : enum halmac_ret_status
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* More details of status code can be found in prototype document
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*/
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enum halmac_ret_status
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deinit_sdio_cfg_88xx(struct halmac_adapter *adapter)
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{
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if (adapter->intf != HALMAC_INTERFACE_SDIO)
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return HALMAC_RET_WRONG_INTF;
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return HALMAC_RET_SUCCESS;
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}
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/**
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* cfg_sdio_rx_agg_88xx() - config rx aggregation
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* @adapter : the adapter of halmac
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* @halmac_rx_agg_mode
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* Author : KaiYuan Chang/Ivan Lin
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* Return : enum halmac_ret_status
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* More details of status code can be found in prototype document
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*/
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enum halmac_ret_status
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cfg_sdio_rx_agg_88xx(struct halmac_adapter *adapter,
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struct halmac_rxagg_cfg *cfg)
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{
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u8 value8;
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u8 size;
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u8 timeout;
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u8 agg_enable;
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u32 value32;
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struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
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PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
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agg_enable = HALMAC_REG_R8(REG_TXDMA_PQ_MAP);
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switch (cfg->mode) {
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case HALMAC_RX_AGG_MODE_NONE:
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agg_enable &= ~(BIT_RXDMA_AGG_EN);
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break;
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case HALMAC_RX_AGG_MODE_DMA:
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case HALMAC_RX_AGG_MODE_USB:
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agg_enable |= BIT_RXDMA_AGG_EN;
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break;
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default:
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PLTFM_MSG_ERR("[ERR]unsupported mode\n");
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agg_enable &= ~BIT_RXDMA_AGG_EN;
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break;
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}
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if (cfg->threshold.drv_define == 0) {
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size = 0xFF;
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timeout = 0x01;
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} else {
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size = cfg->threshold.size;
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timeout = cfg->threshold.timeout;
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}
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value32 = HALMAC_REG_R32(REG_RXDMA_AGG_PG_TH);
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if (cfg->threshold.size_limit_en == 0)
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HALMAC_REG_W32(REG_RXDMA_AGG_PG_TH, value32 & ~BIT_EN_PRE_CALC);
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else
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HALMAC_REG_W32(REG_RXDMA_AGG_PG_TH, value32 | BIT_EN_PRE_CALC);
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HALMAC_REG_W8(REG_TXDMA_PQ_MAP, agg_enable);
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HALMAC_REG_W16(REG_RXDMA_AGG_PG_TH,
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(u16)(size | (timeout << BIT_SHIFT_DMA_AGG_TO_V1)));
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value8 = HALMAC_REG_R8(REG_RXDMA_MODE);
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if (0 != (agg_enable & BIT_RXDMA_AGG_EN))
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HALMAC_REG_W8(REG_RXDMA_MODE, value8 | BIT_DMA_MODE);
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else
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HALMAC_REG_W8(REG_RXDMA_MODE, value8 & ~(BIT_DMA_MODE));
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PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
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return HALMAC_RET_SUCCESS;
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}
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/**
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* sdio_reg_rn_88xx() - read n byte register
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* @adapter : the adapter of halmac
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* @offset : register offset
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* @halmac_size : register value size
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* @value : register value
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* Author : Soar
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* Return : enum halmac_ret_status
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* More details of status code can be found in prototype document
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*/
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enum halmac_ret_status
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sdio_reg_rn_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
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u8 *value)
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{
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u8 *r_val = NULL;
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u32 r_size = size;
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enum halmac_ret_status status = HALMAC_RET_SUCCESS;
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enum halmac_sdio_cmd53_4byte_mode cmd53_4byte =
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adapter->sdio_cmd53_4byte;
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if (0 == (offset & 0xFFFF0000)) {
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PLTFM_MSG_ERR("[ERR]offset 0x%x\n", offset);
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return HALMAC_RET_FAIL;
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}
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status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
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if (status != HALMAC_RET_SUCCESS) {
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PLTFM_MSG_ERR("[ERR]convert offset\n");
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return status;
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}
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if (adapter->pwr_off_flow_flag == 1 ||
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adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) {
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PLTFM_MSG_ERR("[ERR]power off\n");
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return HALMAC_RET_FAIL;
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}
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if ((cmd53_4byte == HALMAC_SDIO_CMD53_4BYTE_MODE_RW ||
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cmd53_4byte == HALMAC_SDIO_CMD53_4BYTE_MODE_R) &&
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(size & 0x03) != 0) {
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if (adapter->sdio_hw_info.io_warn_flag == 1) {
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PLTFM_MSG_WARN("[WARN]reg_rn !align,addr 0x%x,siz %d\n",
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offset, size);
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adapter->watcher.get_watcher.sdio_rn_not_align++;
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}
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r_size = size - (size & 0x03) + 4;
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r_val = (u8 *)PLTFM_MALLOC(r_size);
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if (!r_val) {
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PLTFM_MSG_ERR("[ERR]malloc!!\n");
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return HALMAC_RET_MALLOC_FAIL;
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}
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PLTFM_MEMSET(r_val, 0x00, r_size);
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PLTFM_SDIO_CMD53_RN(offset, r_size, r_val);
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PLTFM_MEMCPY(value, r_val, size);
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PLTFM_FREE(r_val, r_size);
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} else {
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PLTFM_SDIO_CMD53_RN(offset, size, value);
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}
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return HALMAC_RET_SUCCESS;
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}
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/**
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* cfg_txagg_sdio_align_88xx() -config sdio bus tx agg alignment
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* @adapter : the adapter of halmac
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* @enable : function enable(1)/disable(0)
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* @align_size : sdio bus tx agg alignment size (2^n, n = 3~11)
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* Author : Soar Tu
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* Return : enum halmac_ret_status
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* More details of status code can be found in prototype document
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*/
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enum halmac_ret_status
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cfg_txagg_sdio_align_88xx(struct halmac_adapter *adapter, u8 enable,
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u16 align_size)
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{
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u8 i;
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u8 flag = 0;
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struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
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PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
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if (adapter->chip_id == HALMAC_CHIP_ID_8822B)
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return HALMAC_RET_NOT_SUPPORT;
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if ((align_size & 0xF000) != 0) {
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PLTFM_MSG_ERR("[ERR]out of range\n");
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return HALMAC_RET_FAIL;
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}
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for (i = 3; i <= 11; i++) {
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if (align_size == 1 << i) {
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flag = 1;
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break;
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}
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}
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if (flag == 0) {
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PLTFM_MSG_ERR("[ERR]not 2^3 ~ 2^11\n");
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return HALMAC_RET_FAIL;
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}
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adapter->hw_cfg_info.tx_align_size = align_size;
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if (enable)
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HALMAC_REG_W16(REG_RQPN_CTRL_2, 0x8000 | align_size);
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else
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HALMAC_REG_W16(REG_RQPN_CTRL_2, align_size);
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PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
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return HALMAC_RET_SUCCESS;
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}
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/**
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* sdio_indirect_reg_r32_88xx() - read MAC reg by SDIO reg
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* @adapter : the adapter of halmac
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* @offset : register offset
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* Author : Soar
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* Return : enum halmac_ret_status
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* More details of status code can be found in prototype document
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*/
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u32
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sdio_indirect_reg_r32_88xx(struct halmac_adapter *adapter, u32 offset)
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{
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return r_indir_sdio_88xx(adapter, offset, HALMAC_IO_DWORD);
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}
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/**
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* set_sdio_bulkout_num_88xx() - inform bulk-out num
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* @adapter : the adapter of halmac
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* @bulkout_num : usb bulk-out number
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* Author : KaiYuan Chang
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* Return : enum halmac_ret_status
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* More details of status code can be found in prototype document
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*/
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enum halmac_ret_status
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set_sdio_bulkout_num_88xx(struct halmac_adapter *adapter, u8 num)
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{
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return HALMAC_RET_NOT_SUPPORT;
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}
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/**
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* get_sdio_bulkout_id_88xx() - get bulk out id for the TX packet
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* @adapter : the adapter of halmac
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* @halmac_buf : tx packet, include txdesc
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* @halmac_size : tx packet size
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* @bulkout_id : usb bulk-out id
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* Author : KaiYuan Chang
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* Return : enum halmac_ret_status
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* More details of status code can be found in prototype document
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*/
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enum halmac_ret_status
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get_sdio_bulkout_id_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
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u8 *id)
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{
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return HALMAC_RET_NOT_SUPPORT;
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}
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/**
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* sdio_cmd53_4byte_88xx() - cmd53 only for 4byte len register IO
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* @adapter : the adapter of halmac
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* @enable : 1->CMD53 only use in 4byte reg, 0 : No limitation
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* Author : Ivan Lin/KaiYuan Chang
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* Return : enum halmac_ret_status
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* More details of status code can be found in prototype document
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*/
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enum halmac_ret_status
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sdio_cmd53_4byte_88xx(struct halmac_adapter *adapter,
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enum halmac_sdio_cmd53_4byte_mode mode)
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{
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if (adapter->intf != HALMAC_INTERFACE_SDIO)
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return HALMAC_RET_WRONG_INTF;
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if (adapter->api_registry.sdio_cmd53_4byte_en == 0)
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return HALMAC_RET_NOT_SUPPORT;
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adapter->sdio_cmd53_4byte = mode;
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return HALMAC_RET_SUCCESS;
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}
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/**
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* sdio_hw_info_88xx() - info sdio hw info
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* @adapter : the adapter of halmac
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* @HALMAC_SDIO_CMD53_4BYTE_MODE :
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* clock_speed : sdio bus clock. Unit -> MHz
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* spec_ver : sdio spec version
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* Author : Ivan Lin
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* Return : enum halmac_ret_status
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* More details of status code can be found in prototype document
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*/
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enum halmac_ret_status
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sdio_hw_info_88xx(struct halmac_adapter *adapter,
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struct halmac_sdio_hw_info *info)
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{
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PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
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if (adapter->intf != HALMAC_INTERFACE_SDIO)
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return HALMAC_RET_WRONG_INTF;
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PLTFM_MSG_TRACE("[TRACE]SDIO clock:%d, spec:%d\n",
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info->clock_speed, info->spec_ver);
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if (info->clock_speed > SDIO_CLK_SPEED_MAX)
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return HALMAC_RET_SDIO_CLOCK_ERR;
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if (info->clock_speed > SDIO_CLK_HIGH_SPEED_TH)
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adapter->sdio_hw_info.io_hi_speed_flag = 1;
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adapter->sdio_hw_info.io_indir_flag = info->io_indir_flag;
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if (info->clock_speed > SDIO_CLK_HIGH_SPEED_TH &&
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adapter->sdio_hw_info.io_indir_flag == 0)
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PLTFM_MSG_WARN("[WARN]SDIO clock:%d, indir access is better\n",
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info->clock_speed);
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adapter->sdio_hw_info.clock_speed = info->clock_speed;
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adapter->sdio_hw_info.spec_ver = info->spec_ver;
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adapter->sdio_hw_info.block_size = info->block_size;
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/*SW*/
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adapter->sdio_hw_info.io_warn_flag = info->io_warn_flag;
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PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
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return HALMAC_RET_SUCCESS;
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}
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void
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cfg_sdio_tx_page_threshold_88xx(struct halmac_adapter *adapter,
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struct halmac_tx_page_threshold_info *info)
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{
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struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
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u32 threshold = info->threshold;
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PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
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if (info->enable == 1) {
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threshold = BIT(31) | threshold;
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PLTFM_MSG_TRACE("[TRACE]enable\n");
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} else {
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threshold = ~(BIT(31)) & threshold;
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PLTFM_MSG_TRACE("[TRACE]disable\n");
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}
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switch (info->dma_queue_sel) {
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case HALMAC_MAP2_HQ:
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HALMAC_REG_W32(REG_TQPNT1, threshold);
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break;
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case HALMAC_MAP2_NQ:
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HALMAC_REG_W32(REG_TQPNT2, threshold);
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break;
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case HALMAC_MAP2_LQ:
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HALMAC_REG_W32(REG_TQPNT3, threshold);
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break;
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case HALMAC_MAP2_EXQ:
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HALMAC_REG_W32(REG_TQPNT4, threshold);
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break;
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default:
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break;
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}
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PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
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}
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enum halmac_ret_status
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cnv_to_sdio_bus_offset_88xx(struct halmac_adapter *adapter, u32 *offset)
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{
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switch ((*offset) & 0xFFFF0000) {
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case WLAN_IOREG_OFFSET:
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*offset &= HALMAC_WLAN_MAC_REG_MSK;
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*offset |= HALMAC_SDIO_CMD_ADDR_MAC_REG << 13;
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break;
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case SDIO_LOCAL_OFFSET:
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*offset &= HALMAC_SDIO_LOCAL_MSK;
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*offset |= HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13;
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break;
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default:
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*offset = 0xFFFFFFFF;
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PLTFM_MSG_ERR("[ERR]base address!!\n");
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return HALMAC_RET_CONVERT_SDIO_OFFSET_FAIL;
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}
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return HALMAC_RET_SUCCESS;
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}
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enum halmac_ret_status
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leave_sdio_suspend_88xx(struct halmac_adapter *adapter)
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{
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u8 value8;
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u32 cnt;
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struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
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value8 = HALMAC_REG_R8(REG_SDIO_HSUS_CTRL);
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HALMAC_REG_W8(REG_SDIO_HSUS_CTRL, value8 & ~(BIT(0)));
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cnt = 10000;
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while (!(HALMAC_REG_R8(REG_SDIO_HSUS_CTRL) & 0x02)) {
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cnt--;
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if (cnt == 0)
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return HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL;
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}
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value8 = HALMAC_REG_R8(REG_HCI_OPT_CTRL + 2);
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if (adapter->sdio_hw_info.spec_ver == HALMAC_SDIO_SPEC_VER_3_00)
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HALMAC_REG_W8(REG_HCI_OPT_CTRL + 2, value8 | BIT(2));
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else
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HALMAC_REG_W8(REG_HCI_OPT_CTRL + 2, value8 & ~(BIT(2)));
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return HALMAC_RET_SUCCESS;
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}
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/*only for r_indir_sdio_88xx !!, Soar 20171222*/
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static u8
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r_indir_cmd52_88xx(struct halmac_adapter *adapter, u32 offset)
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{
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u8 value8, tmp, cnt = 50;
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u32 reg_cfg = REG_SDIO_INDIRECT_REG_CFG;
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u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
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enum halmac_ret_status status = HALMAC_RET_SUCCESS;
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status = cnv_to_sdio_bus_offset_88xx(adapter, ®_cfg);
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if (status != HALMAC_RET_SUCCESS)
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return status;
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status = cnv_to_sdio_bus_offset_88xx(adapter, ®_data);
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if (status != HALMAC_RET_SUCCESS)
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return status;
|
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PLTFM_SDIO_CMD52_W(reg_cfg, (u8)offset);
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PLTFM_SDIO_CMD52_W(reg_cfg + 1, (u8)(offset >> 8));
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PLTFM_SDIO_CMD52_W(reg_cfg + 2, (u8)(BIT(3) | BIT(4)));
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do {
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tmp = PLTFM_SDIO_CMD52_R(reg_cfg + 2);
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cnt--;
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} while (((tmp & BIT(4)) == 0) && (cnt > 0));
|
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if (((tmp & BIT(4)) == 0) && cnt == 0)
|
PLTFM_MSG_ERR("[ERR]sdio indirect CMD52 read\n");
|
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value8 = PLTFM_SDIO_CMD52_R(reg_data);
|
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return value8;
|
}
|
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/*only for r_indir_sdio_88xx !!, Soar 20171222*/
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static u32
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r_indir_cmd53_88xx(struct halmac_adapter *adapter, u32 offset)
|
{
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u8 cnt = 50;
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u8 value[8];
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u32 reg_cfg = REG_SDIO_INDIRECT_REG_CFG;
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u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
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enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
|
union {
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__le32 dword;
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u8 byte[4];
|
} value32 = { 0x00000000 };
|
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status = cnv_to_sdio_bus_offset_88xx(adapter, ®_cfg);
|
if (status != HALMAC_RET_SUCCESS)
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return status;
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status = cnv_to_sdio_bus_offset_88xx(adapter, ®_data);
|
if (status != HALMAC_RET_SUCCESS)
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return status;
|
|
PLTFM_SDIO_CMD53_W32(reg_cfg, offset | BIT(19) | BIT(20));
|
|
do {
|
PLTFM_SDIO_CMD53_RN(reg_cfg + 2, sizeof(value), value);
|
cnt--;
|
} while (((value[0] & BIT(4)) == 0) && (cnt > 0));
|
|
if (((value[0] & BIT(4)) == 0) && cnt == 0)
|
PLTFM_MSG_ERR("[ERR]sdio indirect CMD53 read\n");
|
|
value32.byte[0] = value[2];
|
value32.byte[1] = value[3];
|
value32.byte[2] = value[4];
|
value32.byte[3] = value[5];
|
|
return rtk_le32_to_cpu(value32.dword);
|
}
|
|
/*only for r_indir_sdio_88xx !!, Soar 20171222*/
|
static u32
|
r8_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr)
|
{
|
union {
|
__le32 dword;
|
u8 byte[4];
|
} val = { 0x00000000 };
|
|
if (adapter->pwr_off_flow_flag == 1 ||
|
adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) {
|
val.byte[0] = r_indir_cmd52_88xx(adapter, adr);
|
return rtk_le32_to_cpu(val.dword);
|
}
|
|
return r_indir_cmd53_88xx(adapter, adr);
|
}
|
|
/*only for r_indir_sdio_88xx !!, Soar 20171222*/
|
static u32
|
r16_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr)
|
{
|
u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
|
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
|
union {
|
__le32 dword;
|
u8 byte[4];
|
} val = { 0x00000000 };
|
|
status = cnv_to_sdio_bus_offset_88xx(adapter, ®_data);
|
if (status != HALMAC_RET_SUCCESS)
|
return status;
|
|
if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) {
|
if (0 != (adr & (2 - 1))) {
|
val.byte[0] = r_indir_cmd52_88xx(adapter, adr);
|
val.byte[1] = r_indir_cmd52_88xx(adapter, adr + 1);
|
} else {
|
val.byte[0] = r_indir_cmd52_88xx(adapter, adr);
|
val.byte[1] = PLTFM_SDIO_CMD52_R(reg_data + 1);
|
}
|
|
return rtk_le32_to_cpu(val.dword);
|
}
|
|
if (0 != (adr & (2 - 1))) {
|
val.byte[0] = (u8)r_indir_cmd53_88xx(adapter, adr);
|
val.byte[1] = (u8)r_indir_cmd53_88xx(adapter, adr + 1);
|
|
return rtk_le32_to_cpu(val.dword);
|
}
|
|
return r_indir_cmd53_88xx(adapter, adr);
|
}
|
|
/*only for r_indir_sdio_88xx !!, Soar 20171222*/
|
static u32
|
r32_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr)
|
{
|
u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
|
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
|
union {
|
__le32 dword;
|
u8 byte[4];
|
} val = { 0x00000000 };
|
|
status = cnv_to_sdio_bus_offset_88xx(adapter, ®_data);
|
if (status != HALMAC_RET_SUCCESS)
|
return status;
|
|
if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) {
|
if (0 != (adr & (4 - 1))) {
|
val.byte[0] = r_indir_cmd52_88xx(adapter, adr);
|
val.byte[1] = r_indir_cmd52_88xx(adapter, adr + 1);
|
val.byte[2] = r_indir_cmd52_88xx(adapter, adr + 2);
|
val.byte[3] = r_indir_cmd52_88xx(adapter, adr + 3);
|
} else {
|
val.byte[0] = r_indir_cmd52_88xx(adapter, adr);
|
val.byte[1] = PLTFM_SDIO_CMD52_R(reg_data + 1);
|
val.byte[2] = PLTFM_SDIO_CMD52_R(reg_data + 2);
|
val.byte[3] = PLTFM_SDIO_CMD52_R(reg_data + 3);
|
}
|
|
return rtk_le32_to_cpu(val.dword);
|
}
|
|
if (0 != (adr & (4 - 1))) {
|
val.byte[0] = (u8)r_indir_cmd53_88xx(adapter, adr);
|
val.byte[1] = (u8)r_indir_cmd53_88xx(adapter, adr + 1);
|
val.byte[2] = (u8)r_indir_cmd53_88xx(adapter, adr + 2);
|
val.byte[3] = (u8)r_indir_cmd53_88xx(adapter, adr + 3);
|
|
return rtk_le32_to_cpu(val.dword);
|
}
|
|
return r_indir_cmd53_88xx(adapter, adr);
|
}
|
|
u32
|
r_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr,
|
enum halmac_io_size size)
|
{
|
u32 value32 = 0;
|
|
PLTFM_MUTEX_LOCK(&adapter->sdio_indir_mutex);
|
|
switch (size) {
|
case HALMAC_IO_BYTE:
|
value32 = r8_indir_sdio_88xx(adapter, adr);
|
break;
|
case HALMAC_IO_WORD:
|
value32 = r16_indir_sdio_88xx(adapter, adr);
|
break;
|
case HALMAC_IO_DWORD:
|
value32 = r32_indir_sdio_88xx(adapter, adr);
|
break;
|
default:
|
break;
|
}
|
|
PLTFM_MUTEX_UNLOCK(&adapter->sdio_indir_mutex);
|
|
return value32;
|
}
|
|
/*only for w_indir_sdio_88xx !!, Soar 20171222*/
|
static enum halmac_ret_status
|
w_indir_cmd52_88xx(struct halmac_adapter *adapter, u32 adr, u32 val,
|
enum halmac_io_size size)
|
{
|
u8 tmp, cnt = 50;
|
u32 reg_cfg = REG_SDIO_INDIRECT_REG_CFG;
|
u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
|
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
|
status = cnv_to_sdio_bus_offset_88xx(adapter, ®_cfg);
|
if (status != HALMAC_RET_SUCCESS)
|
return status;
|
status = cnv_to_sdio_bus_offset_88xx(adapter, ®_data);
|
if (status != HALMAC_RET_SUCCESS)
|
return status;
|
|
PLTFM_SDIO_CMD52_W(reg_cfg, (u8)adr);
|
PLTFM_SDIO_CMD52_W(reg_cfg + 1, (u8)(adr >> 8));
|
switch (size) {
|
case HALMAC_IO_BYTE:
|
PLTFM_SDIO_CMD52_W(reg_data, (u8)val);
|
PLTFM_SDIO_CMD52_W(reg_cfg + 2, (u8)(BIT(2) | BIT(4)));
|
break;
|
case HALMAC_IO_WORD:
|
PLTFM_SDIO_CMD52_W(reg_data, (u8)val);
|
PLTFM_SDIO_CMD52_W(reg_data + 1, (u8)(val >> 8));
|
PLTFM_SDIO_CMD52_W(reg_cfg + 2,
|
(u8)(BIT(0) | BIT(2) | BIT(4)));
|
break;
|
case HALMAC_IO_DWORD:
|
PLTFM_SDIO_CMD52_W(reg_data, (u8)val);
|
PLTFM_SDIO_CMD52_W(reg_data + 1, (u8)(val >> 8));
|
PLTFM_SDIO_CMD52_W(reg_data + 2, (u8)(val >> 16));
|
PLTFM_SDIO_CMD52_W(reg_data + 3, (u8)(val >> 24));
|
PLTFM_SDIO_CMD52_W(reg_cfg + 2,
|
(u8)(BIT(1) | BIT(2) | BIT(4)));
|
break;
|
default:
|
break;
|
}
|
|
do {
|
tmp = PLTFM_SDIO_CMD52_R(reg_cfg + 2);
|
cnt--;
|
} while (((tmp & BIT(4)) == 0) && (cnt > 0));
|
|
if (((tmp & BIT(4)) == 0) && cnt == 0)
|
PLTFM_MSG_ERR("[ERR]sdio indirect CMD52 write\n");
|
|
return status;
|
}
|
|
/*only for w_indir_sdio_88xx !!, Soar 20171222*/
|
static enum halmac_ret_status
|
w_indir_cmd53_88xx(struct halmac_adapter *adapter, u32 adr, u32 val,
|
enum halmac_io_size size)
|
{
|
u8 tmp, cnt = 50;
|
u32 reg_cfg = REG_SDIO_INDIRECT_REG_CFG;
|
u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
|
u32 value32 = 0;
|
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
|
status = cnv_to_sdio_bus_offset_88xx(adapter, ®_cfg);
|
if (status != HALMAC_RET_SUCCESS)
|
return status;
|
status = cnv_to_sdio_bus_offset_88xx(adapter, ®_data);
|
if (status != HALMAC_RET_SUCCESS)
|
return status;
|
|
switch (size) {
|
case HALMAC_IO_BYTE:
|
value32 = adr | BIT(18) | BIT(20);
|
break;
|
case HALMAC_IO_WORD:
|
value32 = adr | BIT(16) | BIT(18) | BIT(20);
|
break;
|
case HALMAC_IO_DWORD:
|
value32 = adr | BIT(17) | BIT(18) | BIT(20);
|
break;
|
default:
|
return HALMAC_RET_FAIL;
|
}
|
|
PLTFM_SDIO_CMD53_W32(reg_data, val);
|
PLTFM_SDIO_CMD53_W32(reg_cfg, value32);
|
|
do {
|
tmp = PLTFM_SDIO_CMD52_R(reg_cfg + 2);
|
cnt--;
|
} while (((tmp & BIT(4)) == 0) && (cnt > 0));
|
|
if (((tmp & BIT(4)) == 0) && cnt == 0)
|
PLTFM_MSG_ERR("[ERR]sdio indirect CMD53 read\n");
|
|
return status;
|
}
|
|
/*only for w_indir_sdio_88xx !!, Soar 20171222*/
|
static enum halmac_ret_status
|
w8_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val)
|
{
|
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
|
if (adapter->pwr_off_flow_flag == 1 ||
|
adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF)
|
status = w_indir_cmd52_88xx(adapter, adr, val, HALMAC_IO_BYTE);
|
else
|
status = w_indir_cmd53_88xx(adapter, adr, val, HALMAC_IO_BYTE);
|
return status;
|
}
|
|
/*only for w_indir_sdio_88xx !!, Soar 20171222*/
|
static enum halmac_ret_status
|
w16_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val)
|
{
|
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
|
if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) {
|
if (0 != (adr & (2 - 1))) {
|
status = w_indir_cmd52_88xx(adapter, adr, val,
|
HALMAC_IO_BYTE);
|
if (status != HALMAC_RET_SUCCESS)
|
return status;
|
status = w_indir_cmd52_88xx(adapter, adr + 1, val >> 8,
|
HALMAC_IO_BYTE);
|
} else {
|
status = w_indir_cmd52_88xx(adapter, adr, val,
|
HALMAC_IO_WORD);
|
}
|
} else {
|
if (0 != (adr & (2 - 1))) {
|
status = w_indir_cmd53_88xx(adapter, adr, val,
|
HALMAC_IO_BYTE);
|
if (status != HALMAC_RET_SUCCESS)
|
return status;
|
status = w_indir_cmd53_88xx(adapter, adr + 1, val >> 8,
|
HALMAC_IO_BYTE);
|
} else {
|
status = w_indir_cmd53_88xx(adapter, adr, val,
|
HALMAC_IO_WORD);
|
}
|
}
|
return status;
|
}
|
|
/*only for w_indir_sdio_88xx !!, Soar 20171222*/
|
static enum halmac_ret_status
|
w32_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val)
|
{
|
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
|
if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) {
|
if (0 != (adr & (4 - 1))) {
|
status = w_indir_cmd52_88xx(adapter, adr, val,
|
HALMAC_IO_BYTE);
|
if (status != HALMAC_RET_SUCCESS)
|
return status;
|
status = w_indir_cmd52_88xx(adapter, adr + 1, val >> 8,
|
HALMAC_IO_BYTE);
|
if (status != HALMAC_RET_SUCCESS)
|
return status;
|
status = w_indir_cmd52_88xx(adapter, adr + 2, val >> 16,
|
HALMAC_IO_BYTE);
|
if (status != HALMAC_RET_SUCCESS)
|
return status;
|
status = w_indir_cmd52_88xx(adapter, adr + 3, val >> 24,
|
HALMAC_IO_BYTE);
|
} else {
|
status = w_indir_cmd52_88xx(adapter, adr, val,
|
HALMAC_IO_DWORD);
|
}
|
} else {
|
if (0 != (adr & (4 - 1))) {
|
status = w_indir_cmd53_88xx(adapter, adr, val,
|
HALMAC_IO_BYTE);
|
if (status != HALMAC_RET_SUCCESS)
|
return status;
|
status = w_indir_cmd53_88xx(adapter, adr + 1, val >> 8,
|
HALMAC_IO_BYTE);
|
if (status != HALMAC_RET_SUCCESS)
|
return status;
|
status = w_indir_cmd53_88xx(adapter, adr + 2, val >> 16,
|
HALMAC_IO_BYTE);
|
if (status != HALMAC_RET_SUCCESS)
|
return status;
|
status = w_indir_cmd53_88xx(adapter, adr + 3, val >> 24,
|
HALMAC_IO_BYTE);
|
} else {
|
status = w_indir_cmd53_88xx(adapter, adr, val,
|
HALMAC_IO_DWORD);
|
}
|
}
|
return status;
|
}
|
|
enum halmac_ret_status
|
w_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val,
|
enum halmac_io_size size)
|
{
|
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
|
PLTFM_MUTEX_LOCK(&adapter->sdio_indir_mutex);
|
|
switch (size) {
|
case HALMAC_IO_BYTE:
|
status = w8_indir_sdio_88xx(adapter, adr, val);
|
break;
|
case HALMAC_IO_WORD:
|
status = w16_indir_sdio_88xx(adapter, adr, val);
|
break;
|
case HALMAC_IO_DWORD:
|
status = w32_indir_sdio_88xx(adapter, adr, val);
|
break;
|
default:
|
break;
|
}
|
|
PLTFM_MUTEX_UNLOCK(&adapter->sdio_indir_mutex);
|
|
return status;
|
}
|
|
enum halmac_ret_status
|
en_ref_autok_sdio_88xx(struct halmac_adapter *adapter, u8 en)
|
{
|
return HALMAC_RET_NOT_SUPPORT;
|
}
|
#endif /* HALMAC_88XX_SUPPORT */
|
