/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* BCM47XX Sonics SiliconBackplane embedded ram core
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*
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* Copyright (C) 1999-2017, Broadcom Corporation
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2 (the "GPL"),
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* available at http://www.broadcom.com/licenses/GPLv2.php, with the
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* following added to such license:
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*
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* As a special exception, the copyright holders of this software give you
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* permission to link this software with independent modules, and to copy and
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* distribute the resulting executable under terms of your choice, provided that
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* you also meet, for each linked independent module, the terms and conditions of
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* the license of that module. An independent module is a module which is not
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* derived from this software. The special exception does not apply to any
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* modifications of the software.
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a license
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* other than the GPL, without Broadcom's express prior written consent.
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*
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*
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* <<Broadcom-WL-IPTag/Open:>>
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*
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* $Id: sbsocram.h 604712 2015-12-08 08:05:42Z $
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*/
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#ifndef _SBSOCRAM_H
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#define _SBSOCRAM_H
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#ifndef _LANGUAGE_ASSEMBLY
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/* cpp contortions to concatenate w/arg prescan */
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#ifndef PAD
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#define _PADLINE(line) pad ## line
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#define _XSTR(line) _PADLINE(line)
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#define PAD _XSTR(__LINE__)
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#endif /* PAD */
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/* Memcsocram core registers */
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typedef volatile struct sbsocramregs {
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uint32 coreinfo;
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uint32 bwalloc;
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uint32 extracoreinfo;
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uint32 biststat;
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uint32 bankidx;
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uint32 standbyctrl;
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uint32 errlogstatus; /* rev 6 */
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uint32 errlogaddr; /* rev 6 */
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/* used for patching rev 3 & 5 */
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uint32 cambankidx;
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uint32 cambankstandbyctrl;
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uint32 cambankpatchctrl;
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uint32 cambankpatchtblbaseaddr;
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uint32 cambankcmdreg;
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uint32 cambankdatareg;
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uint32 cambankmaskreg;
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uint32 PAD[1];
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uint32 bankinfo; /* corev 8 */
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uint32 bankpda;
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uint32 PAD[14];
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uint32 extmemconfig;
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uint32 extmemparitycsr;
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uint32 extmemparityerrdata;
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uint32 extmemparityerrcnt;
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uint32 extmemwrctrlandsize;
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uint32 PAD[84];
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uint32 workaround;
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uint32 pwrctl; /* corerev >= 2 */
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uint32 PAD[133];
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uint32 sr_control; /* corerev >= 15 */
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uint32 sr_status; /* corerev >= 15 */
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uint32 sr_address; /* corerev >= 15 */
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uint32 sr_data; /* corerev >= 15 */
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} sbsocramregs_t;
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#endif /* _LANGUAGE_ASSEMBLY */
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/* Register offsets */
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#define SR_COREINFO 0x00
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#define SR_BWALLOC 0x04
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#define SR_BISTSTAT 0x0c
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#define SR_BANKINDEX 0x10
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#define SR_BANKSTBYCTL 0x14
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#define SR_PWRCTL 0x1e8
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/* Coreinfo register */
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#define SRCI_PT_MASK 0x00070000 /* corerev >= 6; port type[18:16] */
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#define SRCI_PT_SHIFT 16
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/* port types : SRCI_PT_<processorPT>_<backplanePT> */
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#define SRCI_PT_OCP_OCP 0
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#define SRCI_PT_AXI_OCP 1
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#define SRCI_PT_ARM7AHB_OCP 2
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#define SRCI_PT_CM3AHB_OCP 3
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#define SRCI_PT_AXI_AXI 4
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#define SRCI_PT_AHB_AXI 5
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/* corerev >= 3 */
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#define SRCI_LSS_MASK 0x00f00000
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#define SRCI_LSS_SHIFT 20
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#define SRCI_LRS_MASK 0x0f000000
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#define SRCI_LRS_SHIFT 24
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/* In corerev 0, the memory size is 2 to the power of the
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* base plus 16 plus to the contents of the memsize field plus 1.
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*/
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#define SRCI_MS0_MASK 0xf
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#define SR_MS0_BASE 16
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/*
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* In corerev 1 the bank size is 2 ^ the bank size field plus 14,
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* the memory size is number of banks times bank size.
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* The same applies to rom size.
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*/
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#define SRCI_ROMNB_MASK 0xf000
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#define SRCI_ROMNB_SHIFT 12
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#define SRCI_ROMBSZ_MASK 0xf00
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#define SRCI_ROMBSZ_SHIFT 8
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#define SRCI_SRNB_MASK 0xf0
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#define SRCI_SRNB_SHIFT 4
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#define SRCI_SRBSZ_MASK 0xf
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#define SRCI_SRBSZ_SHIFT 0
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#define SRCI_SRNB_MASK_EXT 0x100
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#define SR_BSZ_BASE 14
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/* Standby control register */
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#define SRSC_SBYOVR_MASK 0x80000000
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#define SRSC_SBYOVR_SHIFT 31
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#define SRSC_SBYOVRVAL_MASK 0x60000000
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#define SRSC_SBYOVRVAL_SHIFT 29
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#define SRSC_SBYEN_MASK 0x01000000 /* rev >= 3 */
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#define SRSC_SBYEN_SHIFT 24
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/* Power control register */
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#define SRPC_PMU_STBYDIS_MASK 0x00000010 /* rev >= 3 */
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#define SRPC_PMU_STBYDIS_SHIFT 4
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#define SRPC_STBYOVRVAL_MASK 0x00000008
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#define SRPC_STBYOVRVAL_SHIFT 3
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#define SRPC_STBYOVR_MASK 0x00000007
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#define SRPC_STBYOVR_SHIFT 0
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/* Extra core capability register */
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#define SRECC_NUM_BANKS_MASK 0x000000F0
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#define SRECC_NUM_BANKS_SHIFT 4
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#define SRECC_BANKSIZE_MASK 0x0000000F
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#define SRECC_BANKSIZE_SHIFT 0
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#define SRECC_BANKSIZE(value) (1 << (value))
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/* CAM bank patch control */
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#define SRCBPC_PATCHENABLE 0x80000000
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#define SRP_ADDRESS 0x0001FFFC
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#define SRP_VALID 0x8000
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/* CAM bank command reg */
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#define SRCMD_WRITE 0x00020000
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#define SRCMD_READ 0x00010000
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#define SRCMD_DONE 0x80000000
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#define SRCMD_DONE_DLY 1000
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/* bankidx and bankinfo reg defines corerev >= 8 */
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#define SOCRAM_BANKINFO_SZMASK 0x7f
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#define SOCRAM_BANKIDX_ROM_MASK 0x100
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#define SOCRAM_BANKIDX_MEMTYPE_SHIFT 8
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/* socram bankinfo memtype */
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#define SOCRAM_MEMTYPE_RAM 0
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#define SOCRAM_MEMTYPE_R0M 1
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#define SOCRAM_MEMTYPE_DEVRAM 2
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#define SOCRAM_BANKINFO_REG 0x40
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#define SOCRAM_BANKIDX_REG 0x10
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#define SOCRAM_BANKINFO_STDBY_MASK 0x400
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#define SOCRAM_BANKINFO_STDBY_TIMER 0x800
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/* bankinfo rev >= 10 */
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#define SOCRAM_BANKINFO_DEVRAMSEL_SHIFT 13
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#define SOCRAM_BANKINFO_DEVRAMSEL_MASK 0x2000
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#define SOCRAM_BANKINFO_DEVRAMPRO_SHIFT 14
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#define SOCRAM_BANKINFO_DEVRAMPRO_MASK 0x4000
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#define SOCRAM_BANKINFO_SLPSUPP_SHIFT 15
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#define SOCRAM_BANKINFO_SLPSUPP_MASK 0x8000
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#define SOCRAM_BANKINFO_RETNTRAM_SHIFT 16
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#define SOCRAM_BANKINFO_RETNTRAM_MASK 0x00010000
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#define SOCRAM_BANKINFO_PDASZ_SHIFT 17
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#define SOCRAM_BANKINFO_PDASZ_MASK 0x003E0000
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#define SOCRAM_BANKINFO_DEVRAMREMAP_SHIFT 24
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#define SOCRAM_BANKINFO_DEVRAMREMAP_MASK 0x01000000
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/* extracoreinfo register */
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#define SOCRAM_DEVRAMBANK_MASK 0xF000
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#define SOCRAM_DEVRAMBANK_SHIFT 12
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/* bank info to calculate bank size */
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#define SOCRAM_BANKINFO_SZBASE 8192
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#define SOCRAM_BANKSIZE_SHIFT 13 /* SOCRAM_BANKINFO_SZBASE */
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#endif /* _SBSOCRAM_H */
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