/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
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*
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* Copyright (C) 1999-2017, Broadcom Corporation
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2 (the "GPL"),
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* available at http://www.broadcom.com/licenses/GPLv2.php, with the
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* following added to such license:
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*
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* As a special exception, the copyright holders of this software give you
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* permission to link this software with independent modules, and to copy and
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* distribute the resulting executable under terms of your choice, provided that
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* you also meet, for each linked independent module, the terms and conditions of
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* the license of that module. An independent module is a module which is not
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* derived from this software. The special exception does not apply to any
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* modifications of the software.
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a license
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* other than the GPL, without Broadcom's express prior written consent.
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*
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*
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* <<Broadcom-WL-IPTag/Open:>>
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*
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* $Id: sbpcmcia.h 616054 2016-01-29 13:22:24Z $
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*/
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#ifndef _SBPCMCIA_H
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#define _SBPCMCIA_H
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/* All the addresses that are offsets in attribute space are divided
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* by two to account for the fact that odd bytes are invalid in
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* attribute space and our read/write routines make the space appear
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* as if they didn't exist. Still we want to show the original numbers
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* as documented in the hnd_pcmcia core manual.
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*/
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/* PCMCIA Function Configuration Registers */
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#define PCMCIA_FCR (0x700 / 2)
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#define FCR0_OFF 0
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#define FCR1_OFF (0x40 / 2)
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#define FCR2_OFF (0x80 / 2)
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#define FCR3_OFF (0xc0 / 2)
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#define PCMCIA_FCR0 (0x700 / 2)
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#define PCMCIA_FCR1 (0x740 / 2)
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#define PCMCIA_FCR2 (0x780 / 2)
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#define PCMCIA_FCR3 (0x7c0 / 2)
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/* Standard PCMCIA FCR registers */
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#define PCMCIA_COR 0
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#define COR_RST 0x80
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#define COR_LEV 0x40
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#define COR_IRQEN 0x04
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#define COR_BLREN 0x01
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#define COR_FUNEN 0x01
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#define PCICIA_FCSR (2 / 2)
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#define PCICIA_PRR (4 / 2)
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#define PCICIA_SCR (6 / 2)
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#define PCICIA_ESR (8 / 2)
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#define PCM_MEMOFF 0x0000
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#define F0_MEMOFF 0x1000
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#define F1_MEMOFF 0x2000
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#define F2_MEMOFF 0x3000
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#define F3_MEMOFF 0x4000
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/* Memory base in the function fcr's */
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#define MEM_ADDR0 (0x728 / 2)
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#define MEM_ADDR1 (0x72a / 2)
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#define MEM_ADDR2 (0x72c / 2)
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/* PCMCIA base plus Srom access in fcr0: */
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#define PCMCIA_ADDR0 (0x072e / 2)
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#define PCMCIA_ADDR1 (0x0730 / 2)
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#define PCMCIA_ADDR2 (0x0732 / 2)
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#define MEM_SEG (0x0734 / 2)
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#define SROM_CS (0x0736 / 2)
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#define SROM_DATAL (0x0738 / 2)
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#define SROM_DATAH (0x073a / 2)
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#define SROM_ADDRL (0x073c / 2)
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#define SROM_ADDRH (0x073e / 2)
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#define SROM_INFO2 (0x0772 / 2) /* Corerev >= 2 && <= 5 */
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#define SROM_INFO (0x07be / 2) /* Corerev >= 6 */
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/* Values for srom_cs: */
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#define SROM_IDLE 0
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#define SROM_WRITE 1
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#define SROM_READ 2
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#define SROM_WEN 4
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#define SROM_WDS 7
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#define SROM_DONE 8
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/* Fields in srom_info: */
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#define SRI_SZ_MASK 0x03
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#define SRI_BLANK 0x04
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#define SRI_OTP 0x80
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#define SROM16K_BANK_SEL_MASK (3 << 11)
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#define SROM16K_BANK_SHFT_MASK 11
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#define SROM16K_ADDR_SEL_MASK ((1 << SROM16K_BANK_SHFT_MASK) - 1)
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/* Standard tuples we know about */
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#define CISTPL_NULL 0x00
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#define CISTPL_END 0xff /* End of the CIS tuple chain */
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#define CISTPL_BRCM_HNBU 0x80
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#define HNBU_BOARDREV 0x02 /* One byte board revision */
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#define HNBU_BOARDTYPE 0x1b /* 2 bytes; boardtype */
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#define HNBU_HNBUCIS 0x1d /* what follows is proprietary HNBU CIS format */
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/* sbtmstatelow */
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#define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */
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#define SBTML_INT_EN 0x20000 /* enable sb interrupt */
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/* sbtmstatehigh */
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#define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */
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#endif /* _SBPCMCIA_H */
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