/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Broadcom SiliconBackplane hardware register definitions.
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*
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* Copyright (C) 1999-2017, Broadcom Corporation
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2 (the "GPL"),
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* available at http://www.broadcom.com/licenses/GPLv2.php, with the
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* following added to such license:
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*
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* As a special exception, the copyright holders of this software give you
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* permission to link this software with independent modules, and to copy and
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* distribute the resulting executable under terms of your choice, provided that
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* you also meet, for each linked independent module, the terms and conditions of
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* the license of that module. An independent module is a module which is not
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* derived from this software. The special exception does not apply to any
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* modifications of the software.
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a license
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* other than the GPL, without Broadcom's express prior written consent.
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*
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*
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* <<Broadcom-WL-IPTag/Open:>>
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*
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* $Id: sbconfig.h 530150 2015-01-29 08:43:40Z $
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*/
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#ifndef _SBCONFIG_H
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#define _SBCONFIG_H
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/* cpp contortions to concatenate w/arg prescan */
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#ifndef PAD
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#define _PADLINE(line) pad ## line
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#define _XSTR(line) _PADLINE(line)
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#define PAD _XSTR(__LINE__)
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#endif
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/* enumeration in SB is based on the premise that cores are contiguos in the
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* enumeration space.
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*/
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#define SB_BUS_SIZE 0x10000 /**< Each bus gets 64Kbytes for cores */
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#define SB_BUS_BASE(b) (SI_ENUM_BASE + (b) * SB_BUS_SIZE)
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#define SB_BUS_MAXCORES (SB_BUS_SIZE / SI_CORE_SIZE) /**< Max cores per bus */
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/*
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* Sonics Configuration Space Registers.
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*/
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#define SBCONFIGOFF 0xf00 /**< core sbconfig regs are top 256bytes of regs */
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#define SBCONFIGSIZE 256 /**< sizeof (sbconfig_t) */
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#define SBIPSFLAG 0x08
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#define SBTPSFLAG 0x18
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#define SBTMERRLOGA 0x48 /**< sonics >= 2.3 */
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#define SBTMERRLOG 0x50 /**< sonics >= 2.3 */
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#define SBADMATCH3 0x60
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#define SBADMATCH2 0x68
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#define SBADMATCH1 0x70
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#define SBIMSTATE 0x90
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#define SBINTVEC 0x94
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#define SBTMSTATELOW 0x98
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#define SBTMSTATEHIGH 0x9c
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#define SBBWA0 0xa0
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#define SBIMCONFIGLOW 0xa8
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#define SBIMCONFIGHIGH 0xac
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#define SBADMATCH0 0xb0
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#define SBTMCONFIGLOW 0xb8
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#define SBTMCONFIGHIGH 0xbc
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#define SBBCONFIG 0xc0
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#define SBBSTATE 0xc8
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#define SBACTCNFG 0xd8
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#define SBFLAGST 0xe8
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#define SBIDLOW 0xf8
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#define SBIDHIGH 0xfc
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/* All the previous registers are above SBCONFIGOFF, but with Sonics 2.3, we have
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* a few registers *below* that line. I think it would be very confusing to try
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* and change the value of SBCONFIGOFF, so I'm definig them as absolute offsets here,
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*/
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#define SBIMERRLOGA 0xea8
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#define SBIMERRLOG 0xeb0
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#define SBTMPORTCONNID0 0xed8
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#define SBTMPORTLOCK0 0xef8
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#if !defined(_LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLY__)
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typedef volatile struct _sbconfig {
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uint32 PAD[2];
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uint32 sbipsflag; /**< initiator port ocp slave flag */
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uint32 PAD[3];
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uint32 sbtpsflag; /**< target port ocp slave flag */
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uint32 PAD[11];
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uint32 sbtmerrloga; /**< (sonics >= 2.3) */
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uint32 PAD;
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uint32 sbtmerrlog; /**< (sonics >= 2.3) */
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uint32 PAD[3];
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uint32 sbadmatch3; /**< address match3 */
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uint32 PAD;
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uint32 sbadmatch2; /**< address match2 */
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uint32 PAD;
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uint32 sbadmatch1; /**< address match1 */
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uint32 PAD[7];
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uint32 sbimstate; /**< initiator agent state */
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uint32 sbintvec; /**< interrupt mask */
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uint32 sbtmstatelow; /**< target state */
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uint32 sbtmstatehigh; /**< target state */
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uint32 sbbwa0; /**< bandwidth allocation table0 */
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uint32 PAD;
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uint32 sbimconfiglow; /**< initiator configuration */
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uint32 sbimconfighigh; /**< initiator configuration */
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uint32 sbadmatch0; /**< address match0 */
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uint32 PAD;
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uint32 sbtmconfiglow; /**< target configuration */
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uint32 sbtmconfighigh; /**< target configuration */
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uint32 sbbconfig; /**< broadcast configuration */
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uint32 PAD;
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uint32 sbbstate; /**< broadcast state */
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uint32 PAD[3];
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uint32 sbactcnfg; /**< activate configuration */
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uint32 PAD[3];
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uint32 sbflagst; /**< current sbflags */
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uint32 PAD[3];
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uint32 sbidlow; /**< identification */
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uint32 sbidhigh; /**< identification */
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} sbconfig_t;
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#endif /* !_LANGUAGE_ASSEMBLY && !__ASSEMBLY__ */
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/* sbipsflag */
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#define SBIPS_INT1_MASK 0x3f /**< which sbflags get routed to mips interrupt 1 */
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#define SBIPS_INT1_SHIFT 0
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#define SBIPS_INT2_MASK 0x3f00 /**< which sbflags get routed to mips interrupt 2 */
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#define SBIPS_INT2_SHIFT 8
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#define SBIPS_INT3_MASK 0x3f0000 /**< which sbflags get routed to mips interrupt 3 */
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#define SBIPS_INT3_SHIFT 16
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#define SBIPS_INT4_MASK 0x3f000000 /**< which sbflags get routed to mips interrupt 4 */
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#define SBIPS_INT4_SHIFT 24
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/* sbtpsflag */
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#define SBTPS_NUM0_MASK 0x3f /**< interrupt sbFlag # generated by this core */
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#define SBTPS_F0EN0 0x40 /**< interrupt is always sent on the backplane */
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/* sbtmerrlog */
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#define SBTMEL_CM 0x00000007 /**< command */
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#define SBTMEL_CI 0x0000ff00 /**< connection id */
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#define SBTMEL_EC 0x0f000000 /**< error code */
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#define SBTMEL_ME 0x80000000 /**< multiple error */
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/* sbimstate */
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#define SBIM_PC 0xf /**< pipecount */
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#define SBIM_AP_MASK 0x30 /**< arbitration policy */
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#define SBIM_AP_BOTH 0x00 /**< use both timeslaces and token */
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#define SBIM_AP_TS 0x10 /**< use timesliaces only */
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#define SBIM_AP_TK 0x20 /**< use token only */
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#define SBIM_AP_RSV 0x30 /**< reserved */
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#define SBIM_IBE 0x20000 /**< inbanderror */
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#define SBIM_TO 0x40000 /**< timeout */
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#define SBIM_BY 0x01800000 /**< busy (sonics >= 2.3) */
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#define SBIM_RJ 0x02000000 /**< reject (sonics >= 2.3) */
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/* sbtmstatelow */
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#define SBTML_RESET 0x0001 /**< reset */
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#define SBTML_REJ_MASK 0x0006 /**< reject field */
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#define SBTML_REJ 0x0002 /**< reject */
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#define SBTML_TMPREJ 0x0004 /**< temporary reject, for error recovery */
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#define SBTML_SICF_SHIFT 16 /**< Shift to locate the SI control flags in sbtml */
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/* sbtmstatehigh */
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#define SBTMH_SERR 0x0001 /**< serror */
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#define SBTMH_INT 0x0002 /**< interrupt */
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#define SBTMH_BUSY 0x0004 /**< busy */
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#define SBTMH_TO 0x0020 /**< timeout (sonics >= 2.3) */
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#define SBTMH_SISF_SHIFT 16 /**< Shift to locate the SI status flags in sbtmh */
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/* sbbwa0 */
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#define SBBWA_TAB0_MASK 0xffff /**< lookup table 0 */
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#define SBBWA_TAB1_MASK 0xffff /**< lookup table 1 */
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#define SBBWA_TAB1_SHIFT 16
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/* sbimconfiglow */
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#define SBIMCL_STO_MASK 0x7 /**< service timeout */
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#define SBIMCL_RTO_MASK 0x70 /**< request timeout */
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#define SBIMCL_RTO_SHIFT 4
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#define SBIMCL_CID_MASK 0xff0000 /**< connection id */
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#define SBIMCL_CID_SHIFT 16
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/* sbimconfighigh */
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#define SBIMCH_IEM_MASK 0xc /**< inband error mode */
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#define SBIMCH_TEM_MASK 0x30 /**< timeout error mode */
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#define SBIMCH_TEM_SHIFT 4
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#define SBIMCH_BEM_MASK 0xc0 /**< bus error mode */
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#define SBIMCH_BEM_SHIFT 6
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/* sbadmatch0 */
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#define SBAM_TYPE_MASK 0x3 /**< address type */
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#define SBAM_AD64 0x4 /**< reserved */
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#define SBAM_ADINT0_MASK 0xf8 /**< type0 size */
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#define SBAM_ADINT0_SHIFT 3
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#define SBAM_ADINT1_MASK 0x1f8 /**< type1 size */
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#define SBAM_ADINT1_SHIFT 3
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#define SBAM_ADINT2_MASK 0x1f8 /**< type2 size */
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#define SBAM_ADINT2_SHIFT 3
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#define SBAM_ADEN 0x400 /**< enable */
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#define SBAM_ADNEG 0x800 /**< negative decode */
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#define SBAM_BASE0_MASK 0xffffff00 /**< type0 base address */
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#define SBAM_BASE0_SHIFT 8
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#define SBAM_BASE1_MASK 0xfffff000 /**< type1 base address for the core */
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#define SBAM_BASE1_SHIFT 12
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#define SBAM_BASE2_MASK 0xffff0000 /**< type2 base address for the core */
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#define SBAM_BASE2_SHIFT 16
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/* sbtmconfiglow */
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#define SBTMCL_CD_MASK 0xff /**< clock divide */
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#define SBTMCL_CO_MASK 0xf800 /**< clock offset */
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#define SBTMCL_CO_SHIFT 11
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#define SBTMCL_IF_MASK 0xfc0000 /**< interrupt flags */
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#define SBTMCL_IF_SHIFT 18
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#define SBTMCL_IM_MASK 0x3000000 /**< interrupt mode */
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#define SBTMCL_IM_SHIFT 24
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/* sbtmconfighigh */
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#define SBTMCH_BM_MASK 0x3 /**< busy mode */
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#define SBTMCH_RM_MASK 0x3 /**< retry mode */
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#define SBTMCH_RM_SHIFT 2
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#define SBTMCH_SM_MASK 0x30 /**< stop mode */
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#define SBTMCH_SM_SHIFT 4
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#define SBTMCH_EM_MASK 0x300 /**< sb error mode */
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#define SBTMCH_EM_SHIFT 8
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#define SBTMCH_IM_MASK 0xc00 /**< int mode */
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#define SBTMCH_IM_SHIFT 10
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/* sbbconfig */
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#define SBBC_LAT_MASK 0x3 /**< sb latency */
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#define SBBC_MAX0_MASK 0xf0000 /**< maxccntr0 */
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#define SBBC_MAX0_SHIFT 16
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#define SBBC_MAX1_MASK 0xf00000 /**< maxccntr1 */
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#define SBBC_MAX1_SHIFT 20
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/* sbbstate */
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#define SBBS_SRD 0x1 /**< st reg disable */
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#define SBBS_HRD 0x2 /**< hold reg disable */
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/* sbidlow */
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#define SBIDL_CS_MASK 0x3 /**< config space */
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#define SBIDL_AR_MASK 0x38 /**< # address ranges supported */
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#define SBIDL_AR_SHIFT 3
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#define SBIDL_SYNCH 0x40 /**< sync */
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#define SBIDL_INIT 0x80 /**< initiator */
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#define SBIDL_MINLAT_MASK 0xf00 /**< minimum backplane latency */
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#define SBIDL_MINLAT_SHIFT 8
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#define SBIDL_MAXLAT 0xf000 /**< maximum backplane latency */
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#define SBIDL_MAXLAT_SHIFT 12
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#define SBIDL_FIRST 0x10000 /**< this initiator is first */
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#define SBIDL_CW_MASK 0xc0000 /**< cycle counter width */
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#define SBIDL_CW_SHIFT 18
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#define SBIDL_TP_MASK 0xf00000 /**< target ports */
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#define SBIDL_TP_SHIFT 20
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#define SBIDL_IP_MASK 0xf000000 /**< initiator ports */
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#define SBIDL_IP_SHIFT 24
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#define SBIDL_RV_MASK 0xf0000000 /**< sonics backplane revision code */
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#define SBIDL_RV_SHIFT 28
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#define SBIDL_RV_2_2 0x00000000 /**< version 2.2 or earlier */
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#define SBIDL_RV_2_3 0x10000000 /**< version 2.3 */
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/* sbidhigh */
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#define SBIDH_RC_MASK 0x000f /**< revision code */
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#define SBIDH_RCE_MASK 0x7000 /**< revision code extension field */
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#define SBIDH_RCE_SHIFT 8
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#define SBCOREREV(sbidh) \
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((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
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#define SBIDH_CC_MASK 0x8ff0 /**< core code */
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#define SBIDH_CC_SHIFT 4
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#define SBIDH_VC_MASK 0xffff0000 /**< vendor code */
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#define SBIDH_VC_SHIFT 16
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#define SB_COMMIT 0xfd8 /**< update buffered registers value */
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/* vendor codes */
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#define SB_VEND_BCM 0x4243 /**< Broadcom's SB vendor code */
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#endif /* _SBCONFIG_H */
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